DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification Applicant is reminded of the proper content of an abstract of the disclosure. A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art. If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives. Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps. Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length. See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts. The abstract of the disclosure is objected to because it refers to purported merits of the invention and the last sentence is not complete. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b). Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim s 1, 5, 6, 10, 11, 14 and 15 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chinese Patent Document Number CN 115249676 to Lee et al . Regarding claim 1 , Lee et al. teach a method of fabricating a semiconductor structure with buried power rails (BPRs), the method comprising: providing a semiconductor substrate (110) having opposing first and second surfaces; forming the BPRs (BPR,174) in the semiconductor substrate, the BPRs extending from the first surface of the semiconductor substrate into the semiconductor substrate; forming device structures (140) on a side of the second surface of the semiconductor substrate; forming connections (156) on the side of the second surface of the semiconductor substrate, the connections electrically connected to the device structures and the BPRs; forming a signal delivery network (SDN)(SBEOL) layer on the side of the second surface of the semiconductor substrate, the SDN layer electrically connected to the connections, and the SDN layer electrically connected to the device structures and the BPRs via the connections; and forming a power delivery network (PDN)(PBEOL) layer on a side of the first surface of the semiconductor substrate, the PDN layer electrically connected to the BPRs, and the PDN layer electrically connected to the device structures via the BPRs and the connections. Regarding claim 5 , Lee et al. teach a method of manufacturing a semiconductor structure, wherein the SDN layer comprises an SDN dielectric layer (158) and SDN wires (152) within the SDN dielectric layer, the SDN wires electrically connected to the connections, and the SDN wires electrically connected to the device structures and the BPRs via the connections. Regarding claim 6 , Lee et al. teach a method of fabricating a semiconductor structure, wherein the PDN layer comprises a PDN dielectric layer ( 186 ) and PDN wires (182) within the PDN dielectric layer, the PDN wires electrically connected to the BPRs, and the PDN wires electrically connected to the device structures via the BPRs and the connections. Regarding claim 10 , Lee et al. teach a semiconductor structure with buried power rails (BPRs), the semiconductor structure comprising: a semiconductor substrate (110) having opposing first and second surfaces; the BPRs (BPR, 174) , which extend from the first surface of the semiconductor substrate into the semiconductor substrate; device structures (140) located on a side of the second surface of the semiconductor substrate; connections (156) located on the side of the second surface of the semiconductor substrate and electrically connected to the device structures and the BPRs; a signal delivery network (SDN) layer (SBEOL) located on the side of the second surface of the semiconductor substrate and electrically connected to the connections, and the SDN layer electrically connected to the device structures and the BPRs via the connections; and a power delivery network (PDN)layer (PBEOL) located on a side of the first surface of the semiconductor substrate and electrically connected to the BPRs, and the PDN layer electrically connected to the device structures via the BPRs and the connections. Regarding claim 11 , Lee et al. teach a semiconductor structure wherein the semiconductor substrate is formed with first openings, inner walls of the first openings covered with an isolation layer (134, 172) , the BPRs filled in the first openings, and the connections extending through the isolation layer and are then connected to the BPRs. Regarding claim 14 , Lee et al. teach a semiconductor structure, wherein the SDN layer comprises an SDN dielectric layer (158) and SDN wires (152) within the SDN dielectric layer, the SDN wires electrically connected to the connections, and the SDN wires electrically connected to the device structures and the BPRs via the connections. Regarding claim 16 , Lee et al. teach a semiconductor device, wherein the PDN layer comprises a PDN dielectric layer (186) and PDN wires (182) within the PDN dielectric layer, the PDN wires electrically connected to the BPRs, and the PDN wires electrically connected to the device structures via the BPRs and the connections. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 7, 8, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. Regarding claims 7, 8, 12, and 13 , Lee et al. do not teach a method or semiconductor structure wherein the BPRs have a height of 50 nm to 500 nm, nor a width of 30 nm to 200 nm. Lee et al. do not teach or suggest optimal dimensions of the BPRs. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to arrive at the optimal dimensions through obvious and routine experimentation since it is desirable to provide a device that is both electrically and mechanically sound, as well as proportioned to meet the needs of the design objectives. Allowable Subject Matter Claims 2 – 4, 9, 15, and 17 – 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication No. 2023/0378026 to Kuo et al. teach a device and method of making including a BPR, SDN, and PDN, device structures and connections. Kuo et al. do not teach the PBEOL being formed on a side of the first surface of the substrate. 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