DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 04/22/2026 have been fully considered but they are not persuasive. Applicant argued that the prior art does not provide “the auxiliary layer having higher strength the first protective layer”. Examiner respectfully disagreed, INAGAKI et al provides a first protective layer (70F that is made of a solder resist material) and an auxiliary layer (158Fb that is made of copper) which inherently has a higher strength than a solder resist material. A copper has a strength of 200 – 250 MPa while a solder-resist material typically has a strength of 50 – 100 MPa.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 2, 6 – 10 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by INAGAKI et al. (US 20160064318 A1, “INAGAKI”).
Regarding claim 1, INAGAKI discloses (Fig. 1, 2) a circuit board (10) comprising: a substrate portion that includes a first insulation layer (150Fb & 150Fa) and a first wiring layer (158Fa) buried by the first insulation layer, and a first element mounting portion and a second element mounting portion disposed on an upper surface of the substrate portion (See annotated figure below); a first protective layer (70F) disposed on the substrate portion; and an auxiliary layer (158Fb, 158FbP) that is disposed to overlap at least a part of a first boundary area including a region between the first element mounting portion and the second element mounting portion, the auxiliary layer having higher strength than the first protective layer (See para [0038] & [0052]).
Regarding claim 2, INAGAKI discloses the circuit board of claim 1, wherein the first boundary area extends to an edge of the substrate portion (See Fig. 7A – B).
Regarding claim 6, INAGAKI discloses the circuit board of claim 1, further comprising: a pad layer that is disposed below the substrate portion; a second protective layer (70S) that is disposed below the substrate portion and includes an opening partially exposing the pad layer; and an external connection terminal (76S) connected to the pad layer through the opening of the second protective layer (See the lower part of Fig. 1).
Regarding claim 7, INAGAKI discloses the circuit board of claim 1,further comprising: a first link pad that is disposed on the substrate portion and connected with the first element mounting portion; and a second link pad that is disposed on the substrate portion and connected with the second element mounting portion, wherein the auxiliary layer (158Fb, 158FbP) is disposed between the first link pad and the second link pad (See the upper part of Fig. 1).
Regarding claim 8, INAGAKI discloses the circuit board of claim 7, wherein the first link pad, the second link pad, and the auxiliary layer are disposed on the upper surface of the substrate (See the upper part of Fig. 1).
Regarding claim 9, INAGAKI discloses the circuit board of claim 8, wherein the first link pad, the second link pad, and the auxiliary layer are disposed on the same layer (See the upper part of Fig. 1).
Regarding claim 10, INAGAKI discloses the circuit board of claim 8, wherein the auxiliary layer (158Fb, 158FbP) has a thickness smaller than a thickness of the first (72+76Ff) or second link pad (72+76Fs) (See the upper part of Fig. 1).
Regarding claim 12, INAGAKI discloses the circuit board of claim 1, wherein the auxiliary layer is completely embedded in the first protective layer (See the upper part of Fig. 1).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over INAGAKI et al. (US 20160064318 A1, “INAGAKI”) in view LIANG et al. (US 20210043817 A1, “LIANG”).
Regarding claim 4, INAGAKI discloses the circuit board of claim 1,
INAGAKI is silent on wherein at least one or more holes are disposed inside the auxiliary layer.
However, LIANG discloses (Fig. 5e – 5g) wherein at least one or more holes (261, 262) are disposed inside the auxiliary layer (26).
INAGAKI and LIANG are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified INAGAKI to incorporate the teachings of LIANG and provide wherein at least one or more holes (261, 262) are disposed inside the auxiliary layer (26). Doing so would provide physical integrity, manufacturable precision and mechanical robustness.
Claim(s) 13 – 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over INAGAKI et al. (US 20160064318 A1, “INAGAKI”) in view Nakatani (US 20040227258 A1, “Nakatani”).
Regarding claim 13, INAGAKI discloses the circuit board of claim 1, further comprising: an electronic element that is disposed on each of the first element mounting portion and the second element mounting portion (See Fig. 2); and
INAGAKI is silent on an interposer substrate portion that is disposed on the substrate portion and the electronic element, wherein the interposer substrate portion comprises: an interposer insulation layer that includes a first side facing the substrate portion and a second side opposite to the first side; a first pad layer that is disposed on the first side of the interposer insulation layer; and a first auxiliary layer that is disposed on the first pad layer.
However, Nakatani discloses (Fig. 13) an interposer substrate portion (180) that is disposed on the substrate portion (181) and the electronic element (191), wherein the interposer substrate portion comprises: an interposer insulation layer (182) that includes a first side facing the substrate portion and a second side opposite to the first side (See annotated figure above); a first pad layer that is disposed on the first side of the interposer insulation layer; and a first auxiliary layer that is disposed on the first pad layer (See annotated figure above)
INAGAKI and Nakatani are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified INAGAKI to incorporate the teachings of Nakatani and provide an interposer substrate portion (180) that is disposed on the substrate portion (181) and the electronic element (191), wherein the interposer substrate portion comprises: an interposer insulation layer (182) that includes a first side facing the substrate portion and a second side opposite to the first side (See annotated figure above); a first pad layer that is disposed on the first side of the interposer insulation layer; and a first auxiliary layer that is disposed on the first pad layer (See annotated figure above). Doing so would provide mechanically robust and electrically reliable connection (para [0093], [0149]).
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Regarding claim 14, INAGAKI in view of Nakatani discloses the circuit board of claim 13, wherein the interposer substrate portion further comprises a third protective layer that is disposed to cover the first auxiliary layer under the first pad layer (See annotated figure above).
Regarding claim 15, INAGAKI in view of Nakatani discloses the circuit board of claim 13, wherein the first auxiliary layer is disposed to overlap with the first boundary area at least partially (INAGAKI provide the auxiliary layer to overlap with the first boundary, INAGAKI in view of Nakatani provide the first auxiliary layer that face the auxiliary layer. Hence, overlap with the first boundary).
Regarding claim 16, INAGAKI in view of Nakatani discloses the circuit board of claim 15, wherein the first auxiliary layer is disposed to face the auxiliary layer (See annotated figure above).
Allowable Subject Matter
Claim 3, 5 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIDI MOHAMED MAIGA whose telephone number is (703)756-1870. The examiner can normally be reached Monday - Friday 8 am 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached on 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SIDI M MAIGA/
Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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