DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species E, claims 1-6 and 8-20 in the reply filed on 04/21/2026 is acknowledged.
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2023-0003346, filed on 01/10/2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/30/2024 and 12/28/2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-5, 8, and 10-14 are rejected under 35 U.S.C. 102 as being anticipated by Kwon et al. ( US 2011/0133333 A1; hereinafter Kwon )
Regarding claim 1, Kwon teaches a semiconductor device ( see fig. 13, 14, 19, 20 ) comprising: a first semiconductor substrate ( Fig. 13: semiconductor substrate 10 ) having a first surface and a second surface disposed opposite to each other ( as shown in Fig. 13 ) and having an active pattern ( Fig. 13: integrated circuit 13; [0050] The integrated circuit 13 may include a transistor, a passive device and/or a memory device ) extending on the first surface in a first direction ( as shown in Fig. 13 ); a gate structure disposed in one region of the active pattern and extending in a second direction intersecting the first direction ( schematically indicated in Fig. 13 ); a source/drain region disposed in the active pattern on a side of the gate structure ( inherent to the transistor ); an interlayer insulating film ( Fig. 13: interlayer insulation layer 31 ) disposed on the first semiconductor substrate ( Fig. 13 #10 ) and covering the source/drain region ( as shown in Fig. 13 ); a contact structure ( Fig. 13: contacts 41 ) penetrating through the interlayer insulating film ( Fig. 13 #31 ) and connected to the source/drain region ( as shown in Fig. 13 ); a front wiring structure ( Fig. 13 second contact plug 47 ) having a front insulating layer ( Fig. 13: second interlayer insulation layer 31’ ) disposed on the interlayer insulating film ( Fig. 13 #31 ) and a front wiring layer ( Fig. 13 wiring pattern 45 ) disposed in the front insulating layer ( Fig. 13 #31’ ) and electrically connected to the contact structure ( Fig. 13 #41 ); a conductive through-via ( Fig. 13 through-substrate via 20 ) electrically connected to the contact structure ( Fig. 13 #41 ) or the front wiring layer and penetrating through the interlayer insulating film ( Fig. 13 #31 ) and the first semiconductor substrate ( Fig. 13 #10 ), wherein the second surface of the first semiconductor substrate has a non-planarized surface in a region around the conductive through-via ( Fig. 13 #20 ), wherein the second surface curves downward thereby forming a dishing portion ( see Fig. 14B and paragraph [0102] ); a planarized insulating layer ( Fig. 14D first sub-insulation layer 32 ) disposed on the second surface of the first semiconductor substrate ( Fig. 14D #10 ) and having a lower surface on substantially a same level as a bottom of the conductive through-via ( Fig. 14D #20 ); and a backside wiring structure ( Fig. 19, 20: backside wiring 70 or 74 ) having a backside insulating layer ( Fig. 19, 20: insulating layer 34 and 72 ) disposed on the planarized insulating layer ( Fig. 19, 20 #32 ) and a backside metal ( Fig. 19 conductive cap 60 ), wherein the backside metal ( Fig. 19 #60 ) is disposed in the backside insulating layer ( Fig. 19, 20 #34 and #72 ) and connected to the bottom of the conductive through-via ( Fig. 19,20 #20 ).
Regarding claim 2, Kwon teaches the semiconductor device of claim 1 ( as discussed above), wherein the conductive through-via has a first portion ( Fig. 14D #20 ), wherein the first portion protrudes from the second surface of the first semiconductor substrate ( Fig. 14D #10 ), and the planarized insulating layer ( Fig. 14D #32 ) surrounds the first portion ( Fig. 14D #20 ).
Regarding claim 4, Kwon teaches the semiconductor device of claim 1 ( as discussed above ), wherein the planarized insulating layer ( Fig. 14D #32 ) includes SiO2, SiN, SiCN, SiC, SiCOH, or SiON ( [0057] The first sub-insulation layer 32 may be a silicon oxide layer ).
Regarding claim 5, Kwon teaches the semiconductor device of claim 1 ( as discussed above ), further comprising an etch stop layer ( [0102] The etching process may include wet etching and/or dry etching, for example plasma etching. The etching process may be performed using etchant or gas having etch selectivity with respect to the via hole insulation layer 22 and may leave the via hole insulation layer 22 ) disposed between the planarized insulating layer ( Fig. 14D #32 ) and the backside insulating layer ( Fig. 19, 20 #34 and #72 ).
Regarding claim 8, Kwon teaches the semiconductor device of claim 1 ( as discussed above), wherein the front wiring layer ( Fig. 13 #45 ) has a metal via (Fig. 13: second contact plug 47 ) connected to the conductive through-via ( Fig. 13 #20 ).
Regarding claim 10, Kwon teaches the semiconductor device of claim 1 ( as discussed above ), wherein the backside wiring structure ( Fig. 24A #66 ) further includes a first bonding pad ( Fig. 24A #40’ ) having a surface substantially coplanar with a surface of the backside insulating layer ( Fig. 24A: protective material 80 ).
Regarding claim 11, Kwon teaches the semiconductor device of claim 10 ( as discussed above ), further comprising: a bonding structure ( Fig. 24A: 60, 66, 40’ ) disposed on the backside wiring structure ( as shown in Fig. 24A ), and having a bonding insulating layer ( Fig. 24A #34 ) bonded to the backside insulating layer ( Fig. 24A #32 ) and a second bonding pad ( Fig. 24A #60 ) embedded in the bonding insulating layer ( Fig. 24A #34 ) and bonded to the first bonding pad ( Fig. 24A #40’ ); a lower wiring structure ( Fig. 24A #60 and #66 ) disposed on the bonding structure ( Fig. 24A: 60, 66, 40’ ) and having a lower wiring layer ( Fig. 24A #60) connected to the second bonding pad ( Fig. 24B #66 ) ; and a second semiconductor substrate ( Fig. 24A upper substrate #10 ) disposed on the lower wiring structure ( Fig. 24A: 60, 66, and 40’ ).
Regarding claim 12, Kwon teaches the semiconductor device of claim 11 ( as discussed above ), wherein the second semiconductor substrate ( Fig. 24A #10 ) includes a contact via ( Fig. 24A #21 ) penetrating through the second semiconductor substrate ( as shown in Fig. 24A ) and connected to the lower wiring layer ( Fig. 24A #60 ).
Regarding claim 13, Kwon teaches the semiconductor device of claim 11 ( as discussed above ), wherein the second semiconductor substrate ( Fig. 24A #10 ) includes a logic device or a memory device ( Fig. 24A #13 ).
Regarding claim 14, Kwon teaches the semiconductor device of claim 1 ( as discussed above ), further comprising a support substrate ( Fig. 24A package substrate 200 ) disposed on the front wiring structure ( as shown in Fig. 24A ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under U.S.C. 103 as being unpatentable over Kwon et al.; US 2011/0133333 A1; 11/2010 in view of Kuramochi; US 2024/0429149 A1; 11/2022
Claim 3: Kwon discloses the semiconductor device of claim 1 ( as discussed above).
Kwon does not appear to disclose a difference between the bottom of the conductive through-via and a lowest level of the second surface of the first semiconductor substrate ranges from 2 nm to 15 nm.
However, Kuramochi teaches a difference between the bottom of the conductive through-via ( Fig. 12: through via 22 ) and a lowest level of the second surface of the first semiconductor substrate ( Fig. 12 through-via substrate 10 ) ranges from 2 nm to 15 nm ( [0146] The thickness T5 is for example 5.0 μm or less ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kuramochi with Kwon to implement a difference between the bottom of the conductive through-via and a lowest level of the second surface of the first semiconductor substrate ranges from 2 nm to 15 nm because the gap provides electrical isolation and insolation.
Claim 6 is rejected under U.S.C. 103 as being unpatentable over Kwon et al.; US 2011/0133333 A1; 11/2010 in view of Kreiner et al.; US 2024/0313148 A1; 07/2022
Claim 6: Kwon discloses the semiconductor device of claim 5 ( as discussed above).
Kwon does not appear to disclose the etch stop layer includes a compound containing aluminum.
However, Kreiner teaches the etch stop layer ( Fig. 1 etch stop layer 7 ) includes a compound containing aluminum ( [0104] The etch stop layer 7 comprises InN, AlN or GaN and comprises a thickness in the vertical direction of approximately 50 nm ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kreiner with Kwon to implement the etch stop layer includes a compound containing aluminum because adding this material provides high etch selectivity.
Claim 9 is rejected under U.S.C. 103 as being unpatentable over Kwon et al.; US 2011/0133333 A1; 11/2010 in view of Li et al.; US 12,666,886 B2; 05/2021
Claim 9: Kwon discloses the semiconductor device of claim 1 ( as discussed above).
Kwon does not appear to disclose the first semiconductor substrate has a thickness of 2 µm or less.
However, Li teaches the first semiconductor substrate ( Fig. 2 substrate 120 ) has a thickness of 2 µm or less ( Col. 5 lines 18-22 In one or more embodiments, the flowable CVD film that is formed on the pre-treated substrate surface has a thickness in a range of about 5 nm to about 50 nm, including about 10 nm, about 15 nm, about 20 nm, about 25 nm, about 30 nm, about 35 nm, about 40 nm, or about 45 nm ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Li with Kwon to implement the first semiconductor substrate has a thickness of 2 µm or less because thin initial layers are used to relieve stress between layers.
Claim 15 is rejected under U.S.C. 103 as being unpatentable over Kwon et al.; US 2011/0133333 A1; 11/2010 in view of Do et al.; US 2022/0059460 A1; 05/2021
Claim 15: Kwon discloses the semiconductor device of claim 1 ( as discussed above ).
Kwon does not appear to disclose a plurality of channel layers stacked on the active pattern in a third direction perpendicular to the first direction and the second direction, and spaced apart from each other, wherein the gate structure includes a gate electrode surrounding the plurality of channel layers, and a gate insulating film disposed between the plurality of channel layers and the gate electrode.
However, Do teaches a plurality of channel layers ( Fig. 11: channel layers 120 ) stacked on the active pattern ( Fig. 11: active pattern 105 ) in a third direction perpendicular to the first direction and the second direction ( as shown in Fig. 11 ), and spaced apart from each other ( as shown in Fig. 11 ) , wherein the gate structure ( Fig. 11: gate structure GS ) includes a gate electrode ( Fig. 11: gate electrode 145 ) surrounding the plurality of channel layers ( as shown in Fig. 11 ), and a gate insulating film ( [0089] a gate structure surrounding the same, or a semiconductor device including a negative capacitance FET (NCFET) using a gate insulating film having ferroelectric properties ) disposed between the plurality of channel layers ( Fig. 11 #120 ) and the gate electrode ( Fig. 11 #145 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Do with Kwon to implement a plurality of channel layers stacked on the active pattern in a third direction perpendicular to the first direction and the second direction, and spaced apart from each other, wherein the gate structure includes a gate electrode surrounding the plurality of channel layers, and a gate insulating film disposed between the plurality of channel layers and the gate electrode because this approach optimizes layout and integration density.
Claims 16, 17, and 19 are rejected under U.S.C. 103 as being unpatentable over Kwon et al.; US 2011/0133333 A1; 11/2010 in view of Kreiner et al.; US 2024/0313148 A1; 07/2022 and further in view of Wang et al.; US 12,374,602 B2; 04/2022
Claim 16: Kwon discloses a semiconductor device ( see fig. 13, 14, 19, 20 ) comprising: a first semiconductor substrate ( Fig. 13: semiconductor substrate 10 ) having a first surface and a second surface disposed opposite to each other ( as shown in Fig. 13 ) and having an active pattern ( Fig. 13: integrated circuit 13; [0050] The integrated circuit 13 may include a transistor, a passive device and/or a memory device ) extending on the first surface in a first direction ( as shown in Fig. 13 ); a gate structure disposed in one region of the active pattern and extending in a second direction intersecting the first direction ( schematically indicated in Fig. 13 ); a source/drain region disposed in the active pattern on a side of the gate structure ( inherent to the transistor ); an interlayer insulating film ( Fig. 13: interlayer insulation layer 31 ) disposed on the first semiconductor substrate ( Fig. 13 #10 ) and covering the source/drain region ( as shown in Fig. 13 ); a contact structure ( Fig. 13: contacts 41 ) penetrating through the interlayer insulating film ( Fig. 13 #31 ) and connected to the source/drain region ( as shown in Fig. 13 ); a first wiring structure ( Fig. 13 second contact plug 47 ) having a first insulating layer ( Fig. 13: second interlayer insulation layer 31’ ) disposed on the interlayer insulating film ( Fig. 13 #31 ) and a first wiring layer ( Fig. 13 wiring pattern 45 ) disposed in the first insulating layer ( Fig. 13 #31’ ) and electrically connected to the contact structure ( Fig. 13 #41 ); a conductive through-via ( Fig. 13 through-substrate via 20 ) electrically connected to the first wiring layer ( Fig. 13 #45 ) and penetrating through the interlayer insulating film ( Fig. 13 #31 ) and the first semiconductor substrate ( Fig. 13 #10 ), wherein the conductive through-via ( Fig. 13 #20 ) has a protruding portion from the second surface ( as shown in Fig. 13 ) of the first semiconductor substrate ( Fig. 13 #10 ) and the second surface of the first semiconductor substrate ( Fig. 13 #10 ) has a non-planarized surface in a region around the protruding portion ( as shown in Fig. 13 ), wherein the second surface curves downward thereby forming a dishing portion ( see Fig. 14B and paragraph [0102] ); a planarized insulating layer ( Fig. 24A first sub-insulation layer 32 ) disposed on the second surface of the first semiconductor substrate ( Fig. 24A #10 ), surrounding the protruding portion of the conductive through-via ( Fig. 24A #20 ), the planarized insulating layer ( Fig. 24A #32 ) having a surface substantially coplanar with a contact region of the conductive through-via ( Fig. 24A #20 ); a first bonding structure ( Fig. 24A: 60,66,40’) having a first bonding insulating layer ( Fig. 24A #34 ) disposed on the planarized insulating layer ( Fig. 24A #32 ), and a first bonding pad ( Fig. 24A #60 ) embedded in the first bonding insulating layer ( Fig. 24A #34 ) and connected to the contact region of the conductive through-via ( Fig. 24A #20 );
Kwon does not appear to disclose an etch stop layer disposed between the planarized insulating layer and the first bonding insulating layer and including a material different from the first bonding insulating layer; a second bonding structure disposed on the first bonding structure, and having a second bonding insulating layer bonded to the first bonding insulating layer and a second bonding pad embedded in the second bonding insulating layer and bonded to the first bonding pad; a second wiring structure disposed on the second bonding structure, and having a second wiring layer connected to the second bonding pad; and a second semiconductor substrate having a contact via disposed on the second wiring structure and electrically connected to the second wiring layer.
Kreiner discloses an etch stop layer ( Fig. 1 #7 ) disposed between the planarized insulating layer ( Fig. 1 first semiconductor layer 10 ) and the first bonding insulating layer ( Fig. 1 further semiconductor layer 6; [0102] The further semiconductor layer 6 comprises, for example, GaN, which comprises first dopants ) and including a material different from the first bonding insulating layer ( [0104] The etch stop layer 7 comprises InN, AlN or GaN and comprises a thickness in the vertical direction of approximately 50 nm so layer 7 could be made of AlN which is different from GaN );
Kreiner does not appear to disclose a second bonding structure disposed on the first bonding structure, and having a second bonding insulating layer bonded to the first bonding insulating layer and a second bonding pad embedded in the second bonding insulating layer and bonded to the first bonding pad; a second wiring structure disposed on the second bonding structure, and having a second wiring layer connected to the second bonding pad; and a second semiconductor substrate having a contact via disposed on the second wiring structure and electrically connected to the second wiring layer.
However, Wang teaches a second bonding structure ( Fig. 8 bonding structure 206 ) disposed on the first bonding structure ( Fig. 8 bonding structure 106 ), and having a second bonding insulating layer ( Fig. 8 2061b ) bonded to the first bonding insulating layer ( Fig. 8 1061b ) and a second bonding pad ( Fig. 8 pad portion 2062b ) embedded in the second bonding insulating layer ( Fig. 8 2061b ) and bonded to the first bonding pad ( Fig. 8 pad portion 1062b ); a second wiring structure ( Fig. 8 via portion 2062a ) disposed on the second bonding structure ( Fig. 8 #206 ), and having a second wiring layer ( Fig. 8 contact pad 204 ) connected to the second bonding pad ( Fig. 8 #2062b ); and a second semiconductor substrate ( Fig. 8 201 ) having a contact via ( Fig. 8 203 ) disposed on the second wiring structure ( Fig. 8 #2062a ) and electrically connected to the second wiring layer ( Col. 9 lines 16-21 In some embodiments, the integrated circuit devices (not shown) formed in/on the semiconductor substrate 201 and the conductive pattern 203 may be interconnected to perform one or more functions including memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry, or the like ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wang with Kwon and Kreiner to implement an etch stop layer disposed between the planarized insulating layer and the first bonding insulating layer and including a material different from the first bonding insulating layer; a second bonding structure disposed on the first bonding structure, and having a second bonding insulating layer bonded to the first bonding insulating layer and a second bonding pad embedded in the second bonding insulating layer and bonded to the first bonding pad; a second wiring structure disposed on the second bonding structure, and having a second wiring layer connected to the second bonding pad; and a second semiconductor substrate having a contact via disposed on the second wiring structure and electrically connected to the second wiring layer because this approach provides better etch depth control and selectivity.
Claim 17: Kwon, Kreiner, and Wang disclose the semiconductor device of claim 16 ( as discussed above ).
Kwon teaches the first bonding insulating layer ( Fig. 24A #32 ) comprises SiG2, SiN, SiCN, SiC, SiCOH, or SiON ( [0057] The first sub-insulation layer 32 may be a silicon oxide layer ), the second bonding insulating layer ( Fig. 24A #34 ) comprises Si02, SiN, SiCN, SiC, SiCOH, or SiON ( [0057] the second sub-insulation layer 34 may be a silicon nitride layer ).
Neither Kwon nor Wang appear to disclose the etch stop layer comprises A1203 or AIN.
However, Kreiner teaches the etch stop layer( Fig. 1 #7 ) comprises A1203 or AIN ( [0104] The etch stop layer 7 comprises InN, AlN or GaN ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wang with Kwon and Kreiner to implement the etch stop layer comprises A1203 or AIN because these materials provide high etch selectivity.
Claim 19: Kwon, Kreiner, and Wang disclose the semiconductor device of claim 16 ( as discussed above).
Neither Kwon nor Kreiner appear to disclose the conductive through-via narrows in width as it approaches the second surface of the first semiconductor substrate, and the contact via narrows in width as it approaches the second bonding structure.
However, Wang teaches the conductive through-via ( Fig. 8: TSV 105 ) narrows in width ( as shown in Fig. 8 ) as it approaches the second surface ( Fig. 8 bottom of #101 ) of the first semiconductor substrate ( Fig. 8: substrate 101 ), and the contact via ( Fig. 8 via portion 1062a ) narrows in width ( as shown in Fig. 8 top of the connection 103 is wider than the bottom of 1062a that connects to 1062b ) as it approaches the second bonding structure ( Fig. 8 #206 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wang with Kwon and Kreiner to implement the conductive through-via narrows in width as it approaches the second surface of the first semiconductor substrate, and the contact via narrows in width as it approaches the second bonding structure because a taper is used to prevent over etching.
Claim 18 is rejected under U.S.C. 103 as being unpatentable over Kwon et al.; US 2011/0133333 A1; 11/2010 in view of Kreiner et al.; US 2024/0313148 A1; 07/2022 and Wang et al.; US 12,374,602 B2; 04/2022 as it relates to claim 16 above and further in view of Kuramochi; US 2024/0429149 A1; 11/2022
Claim 18: Kwon, Kreiner, and Wang disclose the semiconductor device of claim 16 ( as discussed above ).
Neither Kwon nor Kreiner nor Wang appear to disclose a difference between a level of the contact region of the conductive through-via and a lowest level of the second surface of the first semiconductor substrate ranges from 2 nm to 15 nm.
However, Kuramochi teaches a difference between the bottom of the conductive through-via ( Fig. 12: through via 22 ) and a lowest level of the second surface of the first semiconductor substrate ( Fig. 12 through-via substrate 10 ) ranges from 2 nm to 15 nm ( [0146] The thickness T5 is for example 5.0 μm or less ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kuramochi with Kwon, Kreiner, and Wang to implement a difference between a level of the contact region of the conductive through-via and a lowest level of the second surface of the first semiconductor substrate ranges from 2 nm to 15 nm because this approach can be used to control contact resistance through geometric effects.
Claim 20 is rejected under U.S.C. 103 as being unpatentable over Kwon et al.; US 2011/0133333 A1; 11/2010 in view of Wang et al.; US 12,374,602 B2; 04/2022
Claim 20: Kwon discloses a semiconductor device ( see fig. 13, 14, 19, 20 ) comprising: a device structure including a first semiconductor substrate ( Fig. 13: semiconductor substrate 10 ) having a first surface and a second surface disposed opposite to each other ( as shown in Fig. 13 ) and having an active pattern ( Fig. 13: integrated circuit 13; [0050] The integrated circuit 13 may include a transistor, a passive device and/or a memory device ) extending from the first surface in a first direction ( as shown in Fig. 13 ), an interlayer insulating film ( Fig. 13: interlayer insulation layer 31 ) disposed on the active pattern ( as discussed above ), a first wiring layer ( Fig. 13 wiring pattern 45 ) disposed on the interlayer insulating film ( Fig. 13 #31 ), and a conductive through-via ( Fig. 13 through-substrate via 20 ) electrically connected to the first wiring layer ( Fig. 13 #45 ) and penetrating through the interlayer insulating film ( Fig. 13 #31 ) and the first semiconductor substrate ( Fig. 13 #10 ), wherein the second surface ( as shown in Fig. 13 ) of the first semiconductor substrate ( Fig. 13 #10 ) has a non-planarized surface in a region around the conductive through-via ( Fig. 13 #20 ), wherein the second surface curves downward ( see Fig. 14B and paragraph [0102] ); a first bonding structure ( Fig. 24A: 60,66,40’) including a planarized insulating layer ( Fig. 24A first sub-insulation layer 32 ) disposed on the second surface of the first semiconductor substrate and having a planarized upper surface, having a first bonding insulating layer ( Fig. 24A #34 ) disposed on the planarized insulating layer ( Fig. 24A #32 ), and a first bonding pad ( Fig. 24A #60 ) embedded in the first bonding insulating layer ( Fig. 24A #34 ) and connected to the contact region of the conductive through-via ( Fig. 24A #20 );
Kwon does not appear to disclose a second bonding structure disposed on the first bonding structure, and including a second bonding insulating layer bonded to the first bonding insulating layer and a second bonding pad embedded in the second bonding insulating layer and bonded to the first bonding pad; a power supply structure including a second wiring layer disposed on the second bonding structure and a second semiconductor substrate with a contact via connected to the second wiring layer; and a support structure disposed on the first wiring layer of the device structure.
However, Wang teaches a second bonding structure ( Fig. 8 bonding structure 206 ) disposed on the first bonding structure ( Fig. 8 bonding structure 106 ), and including a second bonding insulating layer ( Fig. 8 2061b ) bonded to the first bonding insulating layer ( Fig. 8 1061b ) and a second bonding pad ( Fig. 8 pad portion 2062b ) embedded in the second bonding insulating layer ( Fig. 8 2061b ) and bonded to the first bonding pad ( Fig. 8 pad portion 1062b ); a power supply structure ( Col 8 lines 26 – 31 The integrated circuit devices (not shown) formed in/on the semiconductor substrate 101 and the conductive pattern 103′ may be interconnected to perform one or more functions including memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry, or the like ) including a second wiring layer ( Fig. 8: contact pad 204 ) disposed on the second bonding structure ( Fig. 8 #206) and a second semiconductor substrate ( Fig. 8 #201 ) with a contact via connected to the second wiring layer ( Fig. 8 #204 ); and a support structure ( Fig. 8 #103 ) disposed on the first wiring layer ( Fig. 8 #1062a ) of the device structure ( Fig. 8 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Wang with Kwon, to implement a second bonding structure disposed on the first bonding structure, and including a second bonding insulating layer bonded to the first bonding insulating layer and a second bonding pad embedded in the second bonding insulating layer and bonded to the first bonding pad; a power supply structure including a second wiring layer disposed on the second bonding structure and a second semiconductor substrate with a contact via connected to the second wiring layer; and a support structure disposed on the first wiring layer of the device structure because this approach can increase functionality and integration while also enhancing electrical performance.
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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