Prosecution Insights
Last updated: April 19, 2026
Application No. 18/399,204

INTERPOSER INSTRUMENTATION METHOD AND APPARATUS

Non-Final OA §103
Filed
Dec 28, 2023
Examiner
VELEZ, ROBERTO
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
3 (Non-Final)
66%
Grant Probability
Favorable
3-4
OA Rounds
2y 10m
To Grant
88%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allow Rate
173 granted / 260 resolved
-1.5% vs TC avg
Strong +22% interview lift
Without
With
+21.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
21 currently pending
Career history
281
Total Applications
across all art units

Statute-Specific Performance

§101
2.3%
-37.7% vs TC avg
§103
52.5%
+12.5% vs TC avg
§102
27.9%
-12.1% vs TC avg
§112
14.7%
-25.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 260 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application is being examined under the pre-AIA first to invent provisions. Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/09/2026 has been entered. Response to Arguments Applicant’s arguments with respect to claim(s) 1-11, 13-19 and 23-24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action: (a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made. The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1, 4 and 8 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over MOOYMAN-BECK et al. (US PGPUB 2011/0148456) in view of Song et al. (US PGPUB 2009/0168840). Regarding claim 1, MOOYMAN-BECK et al. teaches device comprising: a plurality of first terminals (as shown in fig. 9, terminals on top surface of 60); an intermediate die (62) (Note that a die is known as a block of semiconducting material, usually silicon, on which a given functional integrated circuit (IC) is fabricated. MOOYMAN-BECK et al. teaches in para. 0034 that 62 is a semiconductor interposer. Also it teaches that 62 is a silicon-carrier substrate having signal paths 64 and measurement instrument 50 embedded thereon.) including: a first surface (bottom surface) on which a plurality of first contact points (22) are formed (as shown in fig. 9), wherein each of the first contact points (22) is physically coupled to at least corresponding one of the first terminals (as shown in fig. 9); a second surface (top surface) on which a plurality of second contact points are formed (as shown in fig. 9); a plurality of through holes (TSV 64) filled with conductive material (as disclosed in para. 0034), wherein the conductive material of each of the through holes electrically couples at least corresponding one of the first contact points (22) and at least corresponding one of the second contact points (as shown in fig. 9); and at least one die (12) including a plurality of second terminals (22) and a die circuit electrically coupled to the second terminals (as shown in fig. 9), wherein each of the second terminals (22) is physically coupled to at least corresponding one of the second contact points (as shown in fig. 9 and disclosed in para. 0034-0037). MOOYMAN-BECK et al. fails to specifically teach a first temperature sensor; a second temperature sensor; and a temperature monitor circuit coupled to the first temperature sensor, coupled to the second temperature sensor and configurable to: receive a test data input from the plurality of first terminals; and select the first temperature sensor or the second temperature sensor based on the test data input. However, Song et al. teaches (as shown in fig. 4) a first temperature sensor (200); a second temperature sensor (300); and a temperature monitor circuit (204, 206, 304 and 306) coupled to the first temperature sensor (200), coupled to the second temperature sensor (300) and configurable to: receive a test data input from the plurality of first terminals (202 or 302); and select the first temperature sensor (200) or the second temperature sensor (300) based on the test data input (as disclosed in para. 0026-0030). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have a first temperature sensor; a second temperature sensor; and a temperature monitor circuit coupled to the first temperature sensor, coupled to the second temperature sensor and configurable to: receive a test data input from the plurality of first terminals; and select the first temperature sensor or the second temperature sensor based on the test data input as taught by Song et al. with the invention of MOOYMAN-BECK et al. in order to monitor the operating state of the device. Regarding claim 4, the combination of MOOYMAN-BECK et al. and Song et al. teaches the limitations of claim 1, in addition, MOOYMAN-BECK et al. teaches wherein a signal propagating in the conductive material is a data signal used by the die circuit (as disclosed in para. 0005, data signals will be sent to the die using the JTAG architecture in conjunction with monitor circuit 50). Regarding claim 8, the combination of MOOYMAN-BECK et al. and Nagoya teaches the limitations of claim 1, in addition, MOOYMAN-BECK et al. teaches wherein the intermediate die (62) comprises a second monitor circuit (50) electrically coupled to the conductive material of at least one of the through holes (as disclosed in para. 0029), and wherein the second monitor circuit (50) further includes a memory (54) operable to store the state of the signal propagating in the conductive material (as disclosed in para. 0029). Claim 2 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over MOOYMAN-BECK et al. (US PGPUB 2011/0148456) and Song et al. (US PGPUB 2009/0168840) as applied to claim 1 above, and further in view of Rahman et al. (US Pat. 7,518,398). Regarding claim 2, the combination of MOOYMAN-BECK et al. and Song et al. teaches the limitations of claim 1. The combination of MOOYMAN-BECK et al. and Song et al. fails to specifically teach wherein a signal propagating in the conductive material is an analog signal used by the die circuit. However, Rahman et al. teaches wherein the signal propagating in the conductive material is an analog signal used by the die circuit (204) (as shown in fig. 1-2 and disclosed in col. 3, lines 19-37 and col. 4, lines 33-48). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the signal propagating in the conductive material is an analog signal used by the die circuit as taught by Rahman et al. with the invention of the combination of MOOYMAN-BECK et al. and Song et al. in order to use an energy efficient circuit. Claims 3, 13 and 23-24 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over MOOYMAN-BECK et al. (US PGPUB 2011/0148456) and Song et al. (US PGPUB 2009/0168840) as applied to claim 1 above, and further in view of Raese et al. (US PGPUB 2005/0286396). Regarding claim 3, the combination of MOOYMAN-BECK et al. and Song et al. teaches the limitations of claim 1. The combination of MOOYMAN-BECK et al. and Song et al. fails to specifically teach wherein the temperature monitor circuit further includes an analog-to-digital converter operable to: receive an analog signal from the first temperature sensor or the second temperature sensor; and convert the analog signal to a digital value. However, Raese et al. teaches wherein the temperature monitor circuit (474, 480 and 482) further includes an analog-to-digital converter (474) operable to: receive an analog signal from the first temperature sensor (470) or the second temperature sensor (472); and convert (using 474) the analog signal to a digital value (as shown in fig. 4). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the temperature monitor circuit further include an analog-to-digital converter operable to: receive an analog signal from the first temperature sensor or the second temperature sensor; and convert the analog signal to a digital value as taught by Raese et al. with the invention of the combination of MOOYMAN-BECK et al. and Song et al. in order to transmit and store data more efficiently. Regarding claim 13, MOOYMAN-BECK et al. teaches a device comprising: an intermediate die (62) including: a first surface (bottom surface) on which a plurality of first contact points (22) are formed (as shown in fig. 9), wherein each of the first contact points (22) is physically coupled to at least corresponding one of the first terminals (as shown in fig. 9); a second surface (top surface) on which a plurality of second contact points are formed (as shown in fig. 9); wherein the first surface is positioned on an opposite side of the intermediate die (62) from the second surface (as shown in fig. 9); a plurality of through holes (TSV 64) filled with conductive material (as disclosed in para. 0034), wherein the conductive material of each of the through holes electrically couples at least corresponding one of the first contact points (22) and at least corresponding one of the second contact points (as shown in fig. 9); and at least one die (12) including a plurality of second terminals (22) and a die circuit electrically coupled to the second terminals (as shown in fig. 9), wherein each of the second terminals (22) is physically coupled to at least corresponding one of the second contact points (as shown in fig. 9 and disclosed in para. 0034-0037). MOOYMAN-BECK et al. fails to specifically teach a first temperature sensor; a second temperature sensor; and a temperature monitor circuit coupled to the first temperature sensor, coupled to the second temperature sensor. However, Song et al. teaches (as shown in fig. 4) a first temperature sensor (200); a second temperature sensor (300); and a temperature monitor circuit (204, 206, 304 and 306) coupled to the first temperature sensor (200), coupled to the second temperature sensor (300). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have a first temperature sensor; a second temperature sensor; and a temperature monitor circuit coupled to the first temperature sensor, coupled to the second temperature sensor as taught by Song et al. with the invention of MOOYMAN-BECK et al. in order to monitor the operating state of the device. The combination of MOOYMAN-BECK et al. and Song et al. fails to specifically teach a temperature monitor circuit including an analog-to-digital converter operable to convert an analog signal from the first temperature sensor or from the second temperature sensor to a digital value. However, Raese et al. teaches wherein the temperature monitor circuit (474, 480 and 482) further includes an analog-to-digital converter (474) operable to: receive an analog signal from the first temperature sensor (470) or the second temperature sensor (472); and convert (using 474) the analog signal to a digital value (as shown in fig. 4). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the temperature monitor circuit further include an analog-to-digital converter operable to: receive an analog signal from the first temperature sensor or the second temperature sensor; and convert the analog signal to a digital value as taught by Raese et al. with the invention of the combination of MOOYMAN-BECK et al. and Song et al. in order to transmit and store data more efficiently. Regarding claims 23-24, the combination of MOOYMAN-BECK et al., Song et al. and Raese et al. teaches the limitations of claim 1 and 13, in addition, Raese et al. teaches (as shown in fig. 4) wherein the first temperature sensor (470) is integrated in the intermediate die (462), and wherein the second temperature sensor (472) is integrated in the at least one die (466). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the first temperature sensor integrated in the intermediate die, and wherein the second temperature sensor integrated in the at least one die as taught by Raese et al. with the invention of the combination of MOOYMAN-BECK et al. and Song et al. in order to more efficiently monitor the temperature operation of the device. Claim 5 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over MOOYMAN-BECK et al. (US PGPUB 2011/0148456) and Song et al. (US PGPUB 2009/0168840) as applied to claim 1 above, and further in view of Lunde et al. (US Pat. 6,630,685). Regarding claim 5, the combination of MOOYMAN-BECK et al. and Song et al. teaches the limitations of claim 1. The combination of MOOYMAN-BECK et al. and Song et al. fails to specifically teach wherein a signal propagating in the conductive material is an address signal used by the die circuit. However, Lunde et al. teaches wherein the signal propagating in the conductive material is an address signal used by the die circuit (as disclosed in col. 12, lines 34-40). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the signal propagating in the conductive material is an address signal used by the die circuit as taught by Lunde et al. with the invention of the combination of MOOYMAN-BECK et al. and Song et al. in order to properly and accurately test the die circuit. Claims 6-7 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over MOOYMAN-BECK et al. (US PGPUB 2011/0148456) and Song et al. (US PGPUB 2009/0168840) as applied to claim 1 above, and further in view of KALIDAS et al. (US PGPUB 2001/0013654). Regarding claim 6, the combination of MOOYMAN-BECK et al. and Song et al. teaches the limitations of claim 1, in addition, MOOYMAN-BECK et al. teaches wherein the intermediate die (62) comprises a second monitor circuit (50) electrically coupled to the conductive material of at least one of the through holes (as disclosed in para. 0029). The combination of MOOYMAN-BECK et al. and Song et al. fails to specifically teach wherein the conductive material electrically coupled to the second monitor circuit is a voltage bus provided to the die circuit and a state of a signal propagating in the conductive material is voltage. However, KALIDAS et al. teaches wherein the conductive material electrically coupled to the second monitor circuit is a voltage bus provided to the die circuit and a state of a signal propagating in the conductive material is voltage (as disclosed in para. 0010 and 0028). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the conductive material electrically coupled to the second monitor circuit is a voltage bus provided to the die circuit and a state of a signal propagating in the conductive material is voltage as taught by KALIDAS et al. with the invention of the combination of MOOYMAN-BECK et al. and Song et al. in order to have the ability apply multiple operating voltages. Regarding claim 7, the combination of MOOYMAN-BECK et al. and Song et al. teaches the limitations of claim 1, in addition, MOOYMAN-BECK et al. teaches wherein the intermediate die (62) comprises a second monitor circuit (50) electrically coupled to the conductive material of at least one of the through holes (as disclosed in para. 0029). The combination of MOOYMAN-BECK et al. and Song et al. fails to specifically teach wherein the conductive material electrically coupled to the second monitor circuit is a ground bus provided to the die circuit and a state of a signal propagating in the conductive material is ground. However, KALIDAS et al. wherein the conductive material electrically coupled to the second monitor circuit is a ground bus provided to the die circuit and a state of a signal propagating in the conductive material is ground (as disclosed in para. 0010 and 0028). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the conductive material electrically coupled to the second monitor circuit is a ground bus provided to the die circuit and a state of a signal propagating in the conductive material is ground as taught by KALIDAS et al. with the invention of the combination of MOOYMAN-BECK et al. and Song et al. in order to have the ability apply multiple operating voltages. Claims 9-11 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over MOOYMAN-BECK et al. (US PGPUB 2011/0148456) and Song et al. (US PGPUB 2009/0168840) as applied to claim 1 above, and further in view of Nagoya (US Pat. 6,671,840). Regarding claim 9, the combination of MOOYMAN-BECK et al. and Song et al. teaches the limitations of claim 1, in addition, MOOYMAN-BECK et al. teaches wherein the intermediate die (62) further includes a trigger circuit (51) (as discussed in para. 0034-0035). The combination of MOOYMAN-BECK et al. and Nagoya fails to specifically teach a trigger circuit coupled to the temperature monitor circuit and operable to enable the temperature monitor circuit. However, Nagoya teaches a trigger circuit (2) coupled to the temperature monitor circuit (3a) and operable to enable the temperature monitor circuit (3a) (as disclosed in col. 7, lines 38-60). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have a trigger circuit coupled to the temperature monitor circuit and operable to enable the temperature monitor circuit as taught by Nagoya with the invention of the combination of MOOYMAN-BECK et al. and Song et al. in order to save energy and improve the operation management of the device. Regarding claims 10-11, the combination of MOOYMAN-BECK et al. and Song et al. teaches the limitations of claim 1; in addition, MOOYMAN-BECK et al. teaches wherein the intermediate die (62) further includes a circuit (51). The combination of MOOYMAN-BECK et al. and Song et al. fails to specifically teach a test-access-port (TAP) circuit coupled to the temperature monitor circuit and operable to control the temperature monitor circuit; further comprising: TCK terminal; TMS terminal; TDI terminal; and TDO terminal, wherein the TAP circuit is coupled to the TCK, TMS, TDI and TDO terminals and operable to control the temperature monitor circuit. However, Nagoya teaches a test-access-port (TAP) circuit (as shown in fig. 4) coupled to the temperature monitor circuit and operable to control the temperature monitor circuit (as disclosed in col. 5, lines 1-38); further comprising: TCK terminal (222); TMS terminal (223); TDI terminal (220); and TDO terminal (221), wherein the TAP circuit is coupled to the TCK, TMS, TDI and TDO terminals and operable to control the monitor circuit (as shown in fig. 1-4). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have a test-access-port (TAP) circuit coupled to the temperature monitor circuit and operable to control the temperature monitor circuit; further comprising: TCK terminal; TMS terminal; TDI terminal; and TDO terminal, wherein the TAP circuit is coupled to the TCK, TMS, TDI and TDO terminals and operable to control the temperature monitor circuit as taught by Nagoya with the invention of the combination of MOOYMAN-BECK et al. and Song et al. in order to provide a reliable and secure network. Claims 14-15 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over MOOYMAN-BECK et al. (US PGPUB 2011/0148456), Song et al. (US PGPUB 2009/0168840) and Raese et al. (US PGPUB 2005/0286396) as applied to claim 13 above, further in view of KALIDAS et al. (US PGPUB 2001/0013654). Regarding claim 14, the combination of MOOYMAN-BECK et al., Song et al. and Raese et al. teaches the limitations of claim 13, in addition, MOOYMAN-BECK et al. teaches wherein the intermediate die (62) comprises a second monitor circuit (50) electrically coupled to the conductive material of at least one of the through holes (as disclosed in para. 0029). The combination of MOOYMAN-BECK et al., Nagoya and Rahman et al. fails to specifically teach wherein the conductive material electrically coupled to the second monitor circuit is a voltage bus provided to the die circuit. However, KALIDAS et al. teaches wherein the conductive material electrically coupled to the second monitor circuit is a voltage bus provided to the die circuit (as disclosed in para. 0010 and 0028). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the conductive material electrically coupled to the second monitor circuit is a voltage bus provided to the die circuit as taught by KALIDAS et al. with the invention of the combination of MOOYMAN-BECK et al., Song et al. and Raese et al. in order to have the ability apply multiple operating voltages. Regarding claim 15, the combination of MOOYMAN-BECK et al., Song et al. and Raese et al. teaches the limitations of claim 13, in addition, MOOYMAN-BECK et al. teaches wherein the intermediate die (62) comprises a second monitor circuit (50) electrically coupled to the conductive material of at least one of the through holes (as disclosed in para. 0029). The combination of MOOYMAN-BECK et al., Song et al. and Raese et al. fails to specifically teach wherein the conductive material electrically coupled to the second monitor circuit is a ground bus provided to the die circuit. However, KALIDAS et al. wherein the conductive material electrically coupled to the second monitor circuit is a ground bus provided to the die circuit (as disclosed in para. 0010 and 0028). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the conductive material electrically coupled to the second monitor circuit is a ground bus provided to the die circuit as taught by KALIDAS et al. with the invention of the combination of MOOYMAN-BECK et al., Song et al. and Raese et al. in order to have the ability apply multiple operating voltages. Claim 16 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over MOOYMAN-BECK et al. (US PGPUB 2011/0148456), Song et al. (US PGPUB 2009/0168840) and Raese et al. (US PGPUB 2005/0286396) as applied to claim 13 above, further in view of (Bowers et al. FR 2799550 A1). Regarding claim 16, the combination of MOOYMAN-BECK et al., Song et al. and Raese et al. teaches the limitations of claim 13. The combination of MOOYMAN-BECK et al., Song et al. and Raese et al. fails to specifically teach wherein the temperature monitor circuit further includes a memory operable to store the digital value. However, Bowers et al. teaches wherein the temperature monitor circuit (24) further includes a memory (62) operable to store the digital value (as shown in fig. 3 and disclosed in page 23 of the translated document). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the temperature monitor circuit further include a memory operable to store the digital value as taught by Bowers et al. with the invention of the combination of MOOYMAN-BECK et al., Song et al. and Raese et al. in order to have the ability to compare and analyze the level of operation of the device. Claims 17-19 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over MOOYMAN-BECK et al. (US PGPUB 2011/0148456), Song et al. (US PGPUB 2009/0168840) and Raese et al. (US PGPUB 2005/0286396) as applied to claim 13 above, further in view of Nagoya (US Pat. 6,671,840). Regarding claim 17, the combination of MOOYMAN-BECK et al., Song et al. and Raese et al. teaches the limitations of claim 13, in addition, MOOYMAN-BECK et al. teaches wherein the intermediate die (62) further includes a trigger circuit (51) (as discussed in para. 0034-0035). The combination of MOOYMAN-BECK et al., Song et al. and Raese et al. fails to specifically teach a trigger circuit coupled to the temperature monitor circuit and operable to enable the temperature monitor circuit. However, Nagoya teaches a trigger circuit (2) coupled to the temperature monitor circuit (3a) and operable to enable the temperature monitor circuit (3a) (as disclosed in col. 7, lines 38-60). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have a trigger circuit coupled to the temperature monitor circuit and operable to enable the temperature monitor circuit as taught by Nagoya with the invention of the combination of MOOYMAN-BECK et al., Song et al. and Raese et al. in order to save energy and improve the operation management of the device. Regarding claims 18-19, the combination of MOOYMAN-BECK et al., Song et al. and Raese et al. teaches the limitations of claim 13; in addition, MOOYMAN-BECK et al. teaches wherein the intermediate die (62) further includes a circuit (51). The combination of MOOYMAN-BECK et al., Song et al. and Raese et al. fails to specifically teach a test-access-port (TAP) circuit coupled to the temperature monitor circuit and operable to control the temperature monitor circuit; further comprising: TCK terminal; TMS terminal; TDI terminal; and TDO terminal, wherein the TAP circuit is coupled to the TCK, TMS, TDI and TDO terminals and operable to control the temperature monitor circuit. However, Nagoya teaches a test-access-port (TAP) circuit (as shown in fig. 4) coupled to the temperature monitor circuit and operable to control the temperature monitor circuit (as disclosed in col. 5, lines 1-38); further comprising: TCK terminal (222); TMS terminal (223); TDI terminal (220); and TDO terminal (221), wherein the TAP circuit is coupled to the TCK, TMS, TDI and TDO terminals and operable to control the monitor circuit (as shown in fig. 1-4). It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have a test-access-port (TAP) circuit coupled to the temperature monitor circuit and operable to control the temperature monitor circuit; further comprising: TCK terminal; TMS terminal; TDI terminal; and TDO terminal, wherein the TAP circuit is coupled to the TCK, TMS, TDI and TDO terminals and operable to control the temperature monitor circuit as taught by Nagoya with the invention of the combination of MOOYMAN-BECK et al., Song et al. and Raese et al. in order to provide a reliable and secure network. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERTO VELEZ whose telephone number is (571)272-8597. The examiner can normally be reached Mon-Fri 5:30am-3:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at (571)272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ROBERTO VELEZ/Primary Examiner, Art Unit 2858
Read full office action

Prosecution Timeline

Dec 28, 2023
Application Filed
Jul 17, 2025
Non-Final Rejection — §103
Oct 22, 2025
Response Filed
Nov 05, 2025
Final Rejection — §103
Feb 09, 2026
Request for Continued Examination
Feb 17, 2026
Response after Non-Final Action
Feb 18, 2026
Non-Final Rejection — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
66%
Grant Probability
88%
With Interview (+21.6%)
2y 10m
Median Time to Grant
High
PTA Risk
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