CTNF 18/399,242 CTNF 101464 DETAILED ACTION Priority Claim 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. IDS All references provided in the IDS have been considered. Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because: Reference numerals "11" and "302" have both been used to designate “second plate” or “wiring portion” in Figure 3. 06-22-03 Reference numerals “11” and “301” have both been used to designate “first plate” or “wiring portion” in Figure 9. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. 07-34-01 AIA Claim s 5-6, 10-11, and 16-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Dependent claim 5 recite(s) the limitation "the first gate layer is opposite to the first gate layer" in line 4. A layer cannot be opposite to itself. It has been interpreted to mean that the first active layer is opposite to the first gate layer. Appropriate correction is needed. Claim 6 is rejected by virtue of its dependency on Claim 5. Dependent claim 10 (last line) recites “the first gate insulating sub-layer and the third gate insulating sub-layer comprise a same material, and the second gate insulating sub-layer and the fourth gate insulating sub-layer comprise a same material”. It is unclear if the recitation of “a same material” for the first gate insulating sub-layer and the third gate insulating sub-layer and “a same material” for the second gate insulating sub-layer and the fourth gate insulating sub-layer requires all four layers to be comprised of the same material. It has been interpreted as the first gate insulating sub-layer and the third gate insulating sub-layer have a common material and the second gate insulating sub-layer and the fourth gate insulating sub-layer have a different common material. Appropriate correction is needed. Claim 11 is rejected by virtue of its dependency on claim 10. Dependent claim 16 recite(s) the limitation "the first gate layer to be opposite to the first gate layer" in line 4. A layer cannot be opposite to itself. It has been interpreted to mean that the first active layer is opposite to the first gate layer. Appropriate correction is needed. Claim 17 is rejected by virtue of its dependency on Claim 16. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim (s) 1-2, 12-13 are rejected under 35 U.S.C. 102( a)(1) and 35 U.S.C. 102(a)(2 ) as being anticipated by Hwang (US 20190206969 A1) . Re: Independent Claim 1, Hwang discloses: An array substrate (Hwang, Fig. 8, not numbered), comprising: a substrate (Hwang, substrate; Fig. 8, element 110) having a pixel area (Hwang, area containing transistor, T6, can be considered a pixel area, ¶ [0066]) and a capacitor area (Hwang, area which contains storage capacitor; Fig. 8, element Cst, can be considered the capacitor area); a first thin film transistor (Hwang, light emission control transistor; Fig. 8, element T6, can be considered a first thin film transistor) disposed in the pixel area on the substrate, the first thin film transistor comprising a first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively), a first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f) disposed on a side of the first active layer close to the substrate or on a side of the first active layer away from the substrate (Hwang, Fig. 8), and a first source-drain layer (Hwang, third data connection member; Fig. 8, element 179) disposed on the side of the first active layer away from the substrate, the first source-drain layer being electrically connected to the first active layer (Hwang, ¶ [0107]); and a first capacitor (Hwang, storage capacitor; Fig. 8, element Cst) disposed on the substrate, the first capacitor comprising a first plate (Hwang, the driving gate electrode; Fig. 8, element 155a), a second plate (Hwang, storage electrode; Fig. 8, element 178), and a first dielectric layer (Hwang, second insulating layer; Fig. 8, element 160, ¶ [0110]) disposed between the first plate and the second plate, wherein the first plate and the second plate are disposed respectively in different layers to be opposite to each other in the capacitor area (Hwang, Fig. 8 shows these plates to be in different vertical layers within the capacitor area); the first dielectric layer comprises a first dielectric sub-layer (Hwang, second dielectric constant layer; Fig. 8, element 162) and a second dielectric sub-layer (Hwang, first dielectric constant layer; Fig. 8, element 161) disposed on a side of the first dielectric sub-layer close to the first active layer, the second dielectric sub-layer being disposed in the pixel area and the capacitor area (Hwang, Fig. 8); a dielectric constant of the first dielectric sub-layer is greater than a dielectric constant of the second dielectric sub-layer (Hwang, ¶ [0127]); and and an orthographic projection of the first active layer on the substrate is within an orthographic projection of the second dielectric sub-layer on the substrate (Hwang, Fig. 8). Re: Dependent Claim 2, Hwang disclose(s) all the limitations of claim 1 on which this claim depends. Hwang further discloses: wherein the first dielectric sub-layer (Hwang, second dielectric constant layer; Fig. 8, element 162) comprises at least one of aluminum oxide or zirconium oxide (Hwang, ¶ [0009]), and the second dielectric sub-layer (Hwang, first dielectric constant layer; Fig. 8, element 161) comprises silicon oxide (Hwang, ¶ [0009]). Re: Independent Claim 12, Hwang discloses: A display panel (Hwang, display device; Fig. 8, ¶ [0005]), comprising: an array substrate (Hwang, Fig. 8, not numbered) comprising: a substrate (Hwang, substrate; Fig. 8, element 110) having a pixel area (Hwang, area containing transistor, T6, can be considered a pixel area, ¶ [0066]) and a capacitor area (Hwang, area which contains storage capacitor; Fig. 8, element Cst, can be considered the capacitor area); a first thin film transistor (Hwang, light emission control transistor; Fig. 8, element T6, can be considered a first thin film transistor) disposed in the pixel area on the substrate, the first thin film transistor comprising a first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively), a first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f) disposed on a side of the first active layer close to the substrate away from the substrate, and a first source-drain layer (Hwang, third data connection member; Fig. 8, element 179) disposed on the side of the first active layer away from the substrate, the first source-drain layer being electrically connected to the first active layer (Hwang, ¶ [0107]); and a first capacitor (Hwang, storage capacitor; Fig. 8, element Cst) disposed on the substrate, the first capacitor comprising a first plate (Hwang, the driving gate electrode; Fig. 8, element 155a), a second plate (Hwang, storage electrode; Fig. 8, element 178), and a first dielectric layer (Hwang, second insulating layer; Fig. 8, element 160, ¶ [0110]) disposed between the first plate and the second plate; a metal connection layer (Hwang, pixel electrode, Fig. 6, element 191, ¶ [0140]) disposed on a side of the first thin film transistor away from the substrate (Hwang, Fig. 8); and and a pixel layer (Hwang, emission member, Fig. 6, LD 370) disposed on a side of the metal connection layer away from the substrate (Hwang, Fig. 8), wherein the metal connection layer is electrically connected to the first source-drain layer and the pixel layer (Hwang, Fig. 8, ¶ [0140]); the first plate and the second plate are disposed respectively in different layers to be opposite to each other in the capacitor area (Hwang, Fig. 8 shows these plates to be in different vertical layers within the capacitor area); the first dielectric layer comprises a first dielectric sub-layer (Hwang, second dielectric constant layer; Fig. 8, element 162) and a second dielectric sub-layer (Hwang, first dielectric constant layer; Fig. 8, element 161) disposed on a side of the first dielectric sub-layer close to the first active layer, the second dielectric sub-layer being disposed in the pixel area and the capacitor area (Hwang, Fig. 8); a dielectric constant of the first dielectric sub-layer is greater than a dielectric constant of the second dielectric sub-layer (Hwang, ¶ [0127]); and an orthographic projection of the first active layer on the substrate is within an orthographic projection of the second dielectric sub-layer on the substrate (Hwang, Fig. 8). Re: Dependent Claim 13, Hwang disclose(s) all the limitations of claim 12 on which this claim depends. Hwang further discloses: wherein the first dielectric sub-layer (Hwang, second dielectric constant layer; Fig. 8, element 162) comprises at least one of aluminum oxide or zirconium oxide (Hwang, ¶ [0009]) and the second dielectric sub-layer (Hwang, first dielectric constant layer; Fig. 8, element 161) comprises silicon oxide (Hwang, ¶ [0009])) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 3-7, 14-18 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hwang (US 20190206969 A1). Re: Dependent Claim 3, Hwang disclose(s) all the limitations of claim 1 on which this claim depends. Hwang further discloses: wherein the first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f) is disposed on the side of the first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively) away from the substrate (Hwang, substrate; Fig. 8, element 110); and the first plate (Hwang, the driving gate electrode; Fig. 8, element 155a) and the first gate layer are disposed in a same layer (Hwang, Fig. 8, elements 155a and 155f disposed in the same layer); and and the second plate (Hwang, storage electrode; Fig. 8, element 178) is disposed on a side of the first plate away from the substrate or on a side of the first plate close to the substrate. Hwang is silent regarding: The first plate and the first gate layer comprise a same material; Hwang discloses that elements on the same layer can be formed of the same material to prevent having to form the element on a different layer using a different material (Hwang, ¶ [0124]), which increases the complexity of the manufacturing process, but does not explicitly disclose that the first gate layer and the first plate are the same material. It would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date to make the first plate and the first gate layer, which are already on the same layer, the same material to reduce the number of masks needed during manufacturing (Hwang, ¶ [0124]). Re: Dependent Claim 4, Hwang disclose(s) all the limitations of claim 3 on which this claim depends. Hwang further discloses: wherein the second plate (Hwang, storage electrode; Fig. 8, element 178) is disposed on the side of the first plate (Hwang, the driving gate electrode; Fig. 8, element 155a) away from the substrate (Hwang, substrate; Fig. 8, element 110); and and the second plate is disposed between the first plate and the first source-drain layer (Hwang, third data connection member; Fig. 8, element 179), or the second plate and the first source-drain layer are disposed in a same layer (Hwang, Fig. 8, element 178 and element 179 are disposed in the same passivation layer, element 180). Re: Dependent Claim 5, Hwang disclose(s) all the limitations of claim 3 on which this claim depends. Hwang further discloses: wherein the second plate (Hwang, storage electrode; Fig. 8, element 178) is disposed on the side of the first plate (Hwang, the driving gate electrode; Fig. 8, element 155a); the first thin film transistor (Hwang, light emission control transistor; Fig. 8, element T6, can be considered a first transistor) comprises a gate insulating layer (Hwang, first insulating layer; Fig. 8, element 140) disposed between the first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively) and the first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f) to be opposite to the first gate layer; and and the first dielectric layer (Hwang, second insulating layer; Fig. 8, element 160, ¶ [0110]) and the gate insulating layer are disposed in a same layer (Hwang, Fig. 8, element 140 and element 160 can be considered to be a same layer). Hwang is silent regarding: wherein the second plate is disposed on the side of the first plate close to the substrate; Hwang discloses a second plate, but does not disclose this second plate to be disposed on the side of the first plate close to the substrate. In the absence of any indication that the claimed location is critical or produces unexpected results, a POSITA would have recognized that rearranging the second plate on the side of the first plate closer to the substrate, such as in buffer layer (element 120), will yield a change in capacitance while maintaining the operation of the device unchanged. Re: Dependent Claim 6 , Hwang disclose(s) all the limitations of claim 3 on which this claim depends. Hwang further discloses: further comprising a light-shielding layer (Hwang, buffer layer; Fig. 8, element 120) disposed on the side of the first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively) close to the substrate (Hwang, substrate; Fig. 8, element 110), wherein the second plate (Hwang, storage electrode; Fig. 8, element 178) and the light- shielding layer are disposed in a same layer (Hwang, Fig. 8). Re: Dependent Claim 7 , Hwang disclose(s) all the limitations of claim 1 on which this claim depends. Hwang further discloses: wherein the first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f) is disposed on the side of the first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively); the first plate (Hwang, the driving gate electrode; Fig. 8, element 155a) and the first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f) are disposed in a same layer (Hwang, Fig. 8, elements 155a and 155f are disposed in layer 161); and the second plate (Hwang, storage electrode; Fig. 8, element 178) is disposed on a side of the first plate away from the substrate (Hwang, substrate; Fig. 8, element 110). Hwang is silent regarding: wherein the first gate layer is disposed on the first active layer close to the substrate; Hwang discloses a gate layer in a multilayer stack which includes a first active layer, but does not disclose this gate layer to be disposed on the side of the first active layer close to the substrate. The claimed modification merely relocates the gate layer to the side of first active layer closer to the substrate. In the absence of any indication that the claimed location is critical or produces unexpected results, a POSITA would have recognized that placing the gate layer on the side of the first active layer closer to the substrate as a routine and predicable modification based on known layer arrangements. Rearranging the relative order of known layers in a stack, where each layer performs a known function, would have been an obvious matter of design choice because positional adjustments are routinely made to optimize fabrication or electrical characteristics, and would have yielded predictable results. Hwang is silent regarding: The first plate and the first gate layer comprise a same material; Hwang discloses that elements on the same layer can be formed of the same material to prevent having to form the element on a different layer using a different material (Hwang, ¶ [0124]), increasing the complexity of the manufacturing process. Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date to make the first plate and the first gate layer, which are already on the same layer, the same material to reduce the number of masks needed during manufacturing (Hwang, ¶ [0124]). Re: Dependent Claim 14 , Hwang disclose(s) all the limitations of claim 12 on which this claim depends. Hwang further discloses: wherein the first gate layer (Hwang, a light emission control gate electrode; Fig. 8, element 155f) is disposed on the side of the first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively) away from the substrate (Hwang, substrate; Fig. 8, element 110); the first plate (Hwang, the driving gate electrode; Fig. 8, element 155a) and the first gate layer are disposed in a same layer (Hwang, Fig. 8, elements 155a and 155f disposed in the same layer); and the second plate (Hwang, storage electrode; Fig. 8, element 178) is disposed on a side of the first plate away from the substrate or on a side of the first plate close to the substrate. Hwang is silent regarding: The first plate and the first gate layer comprise a same material; Hwang discloses that elements on the same layer can be formed of the same material to prevent having to form the element on a different layer using a different material (Hwang, ¶ [0124]), increasing the complexity of the manufacturing process. Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date to make the first plate and the first gate layer, which are already on the same layer, the same material to reduce the number of masks needed during manufacturing (Hwang, ¶ [0124]). Re: Dependent Claim 15 , Hwang disclose(s) all the limitations of claim 14 on which this claim depends. Hwang further discloses: wherein the second plate (Hwang, storage electrode; Fig. 8, element 178) is disposed on the side of the first plate (Hwang, the driving gate electrode; Fig. 8, element 155a) away from the substrate (Hwang, substrate; Fig. 8, element 110); and and the second plate is disposed between the first plate and the first source-drain layer (Hwang, third data connection member; Fig. 8, element 179), or the second plate and the first source-drain layer are disposed in a same layer (Hwang, Fig. 8, element 178 and element 179 are disposed in the same passivation layer, element 180). Re: Dependent Claim 16 , Hwang disclose(s) all the limitations of claim 14 on which this claim depends. Hwang further discloses: wherein the second plate (Hwang, storage electrode; Fig. 8, element 178) is disposed on the side of the first plate (Hwang, the driving gate electrode; Fig. 8, element 155a); the first thin film transistor (Hwang, light emission control transistor; Fig. 8, element T6, can be considered a first transistor) comprises a gate insulating layer (Hwang, first insulating layer; Fig. 8, element 140) disposed between the first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively) and the first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f) to be opposite to the first gate layer; and and the first dielectric layer (Hwang, second insulating layer; Fig. 8, element 160, ¶ [0110]) and the gate insulating layer are disposed in a same layer (Hwang, Fig. 8, element 140 and element 160 can be considered to be in a same layer). Hwang is silent regarding: wherein the second plate is disposed on the side of the first plate close to the substrate; Hwang discloses a second plate, but does not disclose this second plate to be disposed on the side of the first plate close to the substrate. In the absence of any indication that the claimed location is critical or produces unexpected results, a POSITA would have recognized that placing the second plate on the side of the first plate close to the substrate, such as in buffer layer (element 120), changes the distance between the plates, which is a known result-effective variable affecting the capacitance, yielding a predictable result. Re: Dependent Claim 17 , Hwang disclose(s) all the limitations of claim 16 on which this claim depends. Hwang further discloses: wherein the array substrate (Hwang, Fig. 8) further comprises a light-shielding layer (Hwang, buffer layer; Fig. 8, element 120) disposed on the side of the first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively) close to the substrate (Hwang, substrate; Fig. 8, element 110); and and the second plate (Hwang, storage electrode; Fig. 8, element 178) and the light-shielding layer are disposed in a same layer (Hwang, Fig. 8). Re: Dependent Claim 18 , Hwang disclose(s) all the limitations of claim 12 on which this claim depends. Hwang further discloses: wherein the first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f) is disposed on the side of the first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively); the first plate (Hwang, the driving gate electrode; Fig. 8, element 155a) and the first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f ) are disposed in a same layer (Hwang, Fig. 8, elements 155a and 155f are disposed in layer 161); and the second plate (Hwang, storage electrode; Fig. 8, element 178) is disposed on a side of the first plate away from the substrate (Hwang, substrate; Fig. 8, element 110); Hwang is silent regarding: wherein the first gate layer is disposed on the side of the first active layer close to the substrate; Hwang discloses a gate layer in a multilayer stack which includes a first active layer, but does not disclose this gate layer to be disposed on the side of the first active layer close to the substrate. The claimed modification merely relocates the gate layer to the side of first active layer closer to the substrate. In the absence of any indication that the claimed location is critical or produces unexpected results, a POSITA would have recognized that placing the gate layer on the side of the first active layer closer to the substrate as a routine and predicable modification based on known layer arrangements. Rearranging the relative order of known layers in a stack, where each layer performs a known function would have been an obvious matter of design choice because positional adjustments are routinely made to optimize fabrication or electrical characteristics, and would have yielded predictable results. Hwang is also silent regarding: The first plate and the first gate layer comprise a same material; Hwang discloses that elements on the same layer can be formed of the same material to prevent having to form the element on a different layer using a different material (Hwang, ¶ [0124]), increasing the complexity of the manufacturing process. Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date to make the first plate and the first gate layer, which are already on the same layer, the same material to reduce the number of masks needed during manufacturing (Hwang, ¶ [0124]). Claim(s) 10-11 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hwang (US 20190206969 A1) in view of Kim (US 8716702 B2). Re: Dependent Claim 10 , Hwang disclose(s) all the limitations of claim 1 on which this claim depends. Hwang further discloses: wherein the substrate (Hwang, substrate; Fig. 8, element 110) further has a non-display area (Hwang, Fig. 8, the region outside of the LD region can be considered a non-display area), and the array substrate further comprises a second thin film transistor (Hwang, switching transistor; Fig. 8, element T2, can be considered the second thin film transistor) disposed in the non-display area on the substrate; there is a gap between an orthographic projection of the second thin film transistor on the substrate and an orthographic projection of the first thin film transistor (Hwang, light emission control transistor; Fig. 8, element T6, can be considered a first transistor) on the substrate; the second thin film transistor comprises a second active layer (Hwang, second active layer includes: a switching source electrode, a switching channel, and the switching drain electrode; Fig. 8, element 136b, 131b, and 137b, respectively), and the first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively) is disposed on a side of the second active layer close to the substrate; a first gate insulating sub-layer (Hwang, first dielectric constant layer; Fig. 8, element 161) and a second gate layer (Hwang, switching gate electrode; Fig. 8, element 155b) are disposed in sequence on a side of the second active layer away from the substrate; a second gate insulating sub-layer (Hwang, second dielectric constant layer; Fig. 8, element 162), a third gate insulating sub-layer (Hwang, third dielectric constant layer; Fig. 8, element 163) and the first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f) are disposed in sequence on the side of the first active layer away from the substrate; a fourth gate insulating sub-layer (Hwang, buffer layer; Fig. 8, ¶ [0117]) is disposed on the side of the second active layer close to the substrate (Hwang, Fig. 8); and the first gate insulating sub-layer and the third gate insulating sub-layer comprise a same material (Hwang, ¶ [0128]), Hwang is silent regarding: the second gate insulating sub-layer and the fourth gate insulating sub-layer comprise a same material. Kim discloses: a fourth gate insulating sub-layer (Kim, a buffer layer; Fig. 4, element 11, Col. 2, lines 18-24). Hwang discloses that the second gate insulating sub-layer may include a zirconium oxide or a titanium oxide. Hwang discloses that the fourth gate insulating sub-layer (buffer layer) is used to block impurities from the substrate (Hwang, ¶ [0117]), but does not disclose the material. Kim discloses a fourth gate insulating sub-layer (buffer layer) with many suitable materials, including titanium dioxide and zirconium dioxide (Kim, Col. 2, lines 18-24) to flatten the substrate (Kim, Col. 4, lines 59-60). Both Hwang and Kim disclose organic light emitting display devices and their structure and are therefore analogous art. It would have been obvious to a POSITA before the effective filing date to make the buffer layer of Hwang with materials including titanium dioxide or zirconium dioxide, arriving at the claimed invention, for preventing impure elements from penetrating into the substrate (Kim, Col. 4, lines 59-62). Re: Dependent Claim 11 , Hwang and Kim disclose(s) all the limitations of claim 10 on which this claim depends. Hwang further discloses: wherein the second dielectric sub-layer (Hwang, first dielectric constant layer; Fig. 8, element 161) is further disposed in the non-display area (Hwang, Fig. 8, the region outside of the LD region can be considered a non-display area), and an orthographic projection of the second active layer (Hwang, second active layer includes: a switching source electrode, a switching channel, and the switching drain electrode; Fig. 8, element 136b, 131b, and 137b, respectively) on the substrate (Hwang, substrate; Fig. 8, element 110) is within the orthographic projection of the second dielectric sub-layer on the substrate. Claim(s) 8-9, 19-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hwang (US 20190206969 A1) in view of Dong (US 12342620 B2). Re: Dependent Claim 8 , Hwang disclose(s) all the limitations of claim 1 on which this claim depends. Hwang further discloses: wherein the first thin film transistor (Hwang, light emission control transistor; Fig. 8, element T6, can be considered a first transistor); and the first gate layer (Hwang, a light emission control gate electrode; Fig. 8, element 155f) Hwang is silent regarding: wherein the first thin film transistor is a dual-gate thin film transistor, Hwang teaches transistors to be configured to be dual gate structure transistors (Hwang, ¶ [0092]) but does not disclose the first thin film transistor to be a dual gate transistor. It would have been obvious to a POSITA before the effective filing date to configure the first thin film transistor to be a dual gate structured transistor to better block the leakage current (Hwang, ¶ [0092]). Hwang is also silent regarding: comprises a first gate sub-layer disposed on the side of the first active layer away from the substrate, and a second gate sub-layer disposed on the side of the first active layer close to the substrate. Dong discloses: and the first gate layer (Dong, second gate layer; Fig. 2, element 350), comprises a first gate sub-layer (Dong, second gate of the driving transistor; Fig. 2, element 351) disposed on the side of the first active layer (Dong, active layer of the driving transistor; Fig. 2, element 331) away from the substrate (Dong, substrate; Fig. 2, element 110) and a second gate sub-layer (Dong, first gate of the driving transistor; Fig. 2, element 311) disposed on the side of the first active layer close to the substrate. Hwang discloses a first gate layer but does not disclose this gate layer to have sub-layers and for these sub-layers to have a specific configuration. Dong discloses a first gate sub-layer disposed on the side of the first active layer away from the substrate and a second gate sub-layer disposed on the side of the first active layer close to the substrate for to avoid a patterning operation on another layer (Dong, Col. 7, lines 49-52). Both Hwang and Dong disclose transistor structures and arrangements for use in display devices and are therefore analogous art. It would have been obvious to a POSITA before the effective filing date to use the gate and plate layers and placements taught by Dong to the structure of Hwang to reduce the operations performed on the substrate, reducing overall manufacturing processing and costs (Dong, Col. 7, lines 53-57). Re: Dependent Claim 9 , Hwang and Dong disclose(s) all the limitations of claim 8 on which this claim depends. Dong further discloses: wherein the first plate (Dong, second electrode plate of the storage capacitor; Fig. 2, element 351(352)) and the first gate sub-layer (Dong, second gate of the driving transistor; Fig. 2, element 351) are disposed in a same layer (Dong, Col. 7, lines 17-18 & Col. 16, lines 38-40) and comprise a same material (Col. 9&10, lines 59- 6, and Col. 11, lines 16-18), and the second plate (Dong, first electrode plate of the storage capacitor; Fig. 2, element 312) is disposed on a side of the first plate away from the substrate or on a side of the first plate close to the substrate (Dong, Fig. 2); or the first plate and the second gate sub-layer are disposed in a same layer and comprise a same material, and the second plate is disposed on the side of the first plate away from the substrate or on the side of the first plate close to the substrate (Dong discloses the first plate and the first gate sub-layer are disposed in the same layer and the second plate is disposed on a side of the first plate away from the substrate or on a side of the first plate close to the substrate). Re: Dependent Claim 19 , Hwang disclose(s) all the limitations of claim 12 on which this claim depends. Hwang further discloses: wherein the first thin film transistor (Hwang, light emission control transistor; Fig. 8, element T6, can be considered a first transistor); and the first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f); Hwang is silent regarding: wherein the first thin film transistor is a dual-gate thin film transistor, Hwang teaches transistors to be configured to be dual gate structure transistors (Hwang, ¶ [0092]) but does not disclose the first thin film transistor to be a dual gate transistor. It would have been obvious to a POSITA before the effective filing date to configure the first thin film transistor to be a dual gate structured transistor to better block the leakage current (Hwang, ¶ [0092]). Hwang is also silent regarding: comprises a first gate sub-layer disposed on the side of the first active layer away from the substrate and a second gate sub-layer disposed on the side of the first active layer close to the substrate. Dong discloses: and the first gate layer (Dong, second gate layer; Fig. 2, element 350), comprises a first gate sub-layer (Dong, second gate of the driving transistor; Fig. 2, element 351) disposed on the side of the first active layer (Dong, active layer of the driving transistor; Fig. 2, element 331) away from the substrate (Dong, substrate; Fig. 2, element 110) and a second gate sub-layer (Dong, first gate of the driving transistor; Fig. 2, element 311) disposed on the side of the first active layer close to the substrate. Hwang discloses a first gate layer but does not disclose this gate layer to have sub-layers and for these sub-layers to have a specific configuration. Dong discloses a first gate sub-layer disposed on the side of the first active layer away from the substrate and a second gate sub-layer disposed on the side of the first active layer close to the substrate for to avoid a patterning operation on another layer (Dong, Col. 7, lines 49-52). Both Hwang and Dong disclose transistor structures and arrangements for use in display devices and are therefore analogous art. It would have been obvious to a POSITA before the effective filing date to use the gate and plate layers and placements taught by Dong to the structure of Hwang to reduce the operations performed on the substrate, reducing overall manufacturing processing and costs (Dong, Col. 7, lines 53-57). Re: Dependent Claim 20 , Hwang and Dong disclose(s) all the limitations of claim 19 on which this claim depends. Dong further discloses: wherein the first plate (Dong, second electrode plate of the storage capacitor; Fig. 2, element 351(352)) and the first gate sub-layer (Dong, second gate of the driving transistor; Fig. 2, element 351) are disposed in a same layer (Dong, Col. 7, lines 17-18 & Col. 16, lines 38-40) and comprise a same material (Col. 9&10, lines 59- 6, and Col. 11, lines 16-18), and the second plate (Dong, first electrode plate of the storage capacitor; Fig. 2, element 312) is disposed on a side of the first plate away from the substrate or on a side of the first plate close to the substrate (Dong, Fig. 2); or the first plate and the second gate sub-layer are disposed in a same layer and comprise a same material, and the second plate is disposed on the side of the first plate away from the substrate or on the side of the first plate close to the substrate (Dong discloses the first plate and the first gate sub-layer are disposed in the same layer and the second plate is disposed on a side of the first plate away from the substrate or on a side of the first plate close to the substrate) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIMARTA KAUR CHOWDHARY whose telephone number is (571)272-7679. The examiner can normally be reached usually Monday - Thursday, 7:00 AM - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NIMARTA KAUR CHOWDHARY/ Examiner, Art Unit 2898 /Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898 Application/Control Number: 18/399,242 Page 2 Art Unit: 2898 Application/Control Number: 18/399,242 Page 3 Art Unit: 2898 Application/Control Number: 18/399,242 Page 4 Art Unit: 2898 Application/Control Number: 18/399,242 Page 5 Art Unit: 2898 Application/Control Number: 18/399,242 Page 6 Art Unit: 2898 Application/Control Number: 18/399,242 Page 7 Art Unit: 2898 Application/Control Number: 18/399,242 Page 8 Art Unit: 2898 Application/Control Number: 18/399,242 Page 9 Art Unit: 2898 Application/Control Number: 18/399,242 Page 10 Art Unit: 2898 Application/Control Number: 18/399,242 Page 11 Art Unit: 2898 Application/Control Number: 18/399,242 Page 12 Art Unit: 2898 Application/Control Number: 18/399,242 Page 13 Art Unit: 2898 Application/Control Number: 18/399,242 Page 14 Art Unit: 2898 Application/Control Number: 18/399,242 Page 15 Art Unit: 2898 Application/Control Number: 18/399,242 Page 16 Art Unit: 2898 Application/Control Number: 18/399,242 Page 17 Art Unit: 2898 Application/Control Number: 18/399,242 Page 18 Art Unit: 2898 Application/Control Number: 18/399,242 Page 19 Art Unit: 2898 Application/Control Number: 18/399,242 Page 20 Art Unit: 2898 Application/Control Number: 18/399,242 Page 21 Art Unit: 2898 Application/Control Number: 18/399,242 Page 22 Art Unit: 2898 Application/Control Number: 18/399,242 Page 23 Art Unit: 2898