DETAILED ACTION
Response to Amendments
The amendment filed on 06/22/2026 has been entered. Claims 1, 3-12, 14-20 are pending in the application. Claims 1, 5, 10, 12, 16, have been amended. Claims 2 and 13 are canceled without prejudice or disclaimer. Examiner notes the amendments to claims 5, claim 10, and 16 overcome the 112b rejections for claims 5-6, 10-11, and 16-17. Examiner further notes that the drawings filed on 06/22/2026 overcome the drawing objection.
Response to Arguments
Applicant’s arguments, see pgs. 8-10, filed 06/22/2026, with respect to the rejection(s) of amended independent claim(s) 1 and 12 under Hwang have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art teaching the limitations of the material of the first dielectric sub-layer and the second sub-dielectric layer.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-7, 12, 15-18 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hwang (US 20190206969 A1) in view of Peng (US 20050023533 A1).
Re: Independent Claim 1, Hwang discloses:
An array substrate (Hwang, Fig. 8, not numbered), comprising: a substrate (Hwang, substrate; Fig. 8, element 110) having a pixel area (Hwang, area containing transistor, T6, can be considered a pixel area, ¶ [0066]) and a capacitor area (Hwang, area which contains storage capacitor; Fig. 8, element Cst, can be considered the capacitor area);
a first thin film transistor (Hwang, light emission control transistor; Fig. 8, element T6, can be considered a first thin film transistor) disposed in the pixel area on the substrate, the first thin film transistor comprising a first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively), a first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f) disposed on a side of the first active layer close to the substrate or on a side of the first active layer away from the substrate (Hwang, Fig. 8), and a first source-drain layer (Hwang, third data connection member; Fig. 8, element 179) disposed on the side of the first active layer away from the substrate, the first source-drain layer being electrically connected to the first active layer (Hwang, ¶ [0107]); and
a first capacitor (Hwang, storage capacitor; Fig. 8, element Cst) disposed on the substrate, the first capacitor comprising a first plate (Hwang, the driving gate electrode; Fig. 8, element 155a), a second plate (Hwang, storage electrode; Fig. 8, element 178), and a first dielectric layer (Hwang, second insulating layer; Fig. 8, element 160, ¶ [0110]) disposed between the first plate and the second plate,
wherein the first plate and the second plate are disposed respectively in different layers to be opposite to each other in the capacitor area (Hwang, Fig. 8 shows these plates to be in different vertical layers within the capacitor area);
the first dielectric layer comprises a first dielectric sub-layer (Hwang, second dielectric constant layer; Fig. 8, element 162) and a second dielectric sub-layer (Hwang, first dielectric constant layer; Fig. 8, element 161) disposed on a side of the first dielectric sub-layer close to the first active layer, the second dielectric sub-layer being disposed in the pixel area and the capacitor area (Hwang, Fig. 8);
a dielectric constant of the first dielectric sub-layer is greater than a dielectric constant of the second dielectric sub-layer (Hwang, ¶ [0127]);
and an orthographic projection of the first active layer on the substrate is within an orthographic projection of the second dielectric sub-layer on the substrate (Hwang, Fig. 8); and
and the second dielectric sub-layer comprises silicon oxide (Hwang, Fig. 8, ¶ [0168] discloses element 161 may include a silicon oxide)
Hwang does not explicitly disclose:
the first dielectric sub-layer comprises aluminum oxide
Peng discloses:
the first dielectric sub-layer (Peng, dielectric layer; Fig. 2C, element 220) comprises aluminum oxide (Peng, ¶ [0030]).
Hwang discloses a first dielectric sub-layer but does not explicitly disclose this sub-layer to comprise aluminum oxide. Peng discloses a dielectric layer to comprise aluminum oxide for use in an array substrate. Both Hwang and Peng disclose array substrates and are therefore analogous art. It would be obvious to a person of ordinary skill in the art (POSITA) before the effective filing date to make the first dielectric sub-layer, as disclosed by Hwang, of aluminum oxide, as disclosed by Peng, for the known benefit of selecting specific dielectric constants of the layer (Peng, ¶ [0030]).
Re: Dependent Claim 3, Hwang and Peng disclose(s) all the limitations of claim 1 on which this claim depends. Hwang further discloses:
wherein the first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f) is disposed on the side of the first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively) away from the substrate (Hwang, substrate; Fig. 8, element 110); and
the first plate (Hwang, the driving gate electrode; Fig. 8, element 155a) and the first gate layer are disposed in a same layer (Hwang, Fig. 8, elements 155a and 155f disposed in the same layer); and
and the second plate (Hwang, storage electrode; Fig. 8, element 178) is disposed on a side of the first plate away from the substrate or on a side of the first plate close to the substrate.
Hwang is silent regarding:
The first plate and the first gate layer comprise a same material;
Hwang discloses that elements on the same layer can be formed of the same material to prevent having to form the element on a different layer using a different material (Hwang, ¶ [0124]), which increases the complexity of the manufacturing process, but does not explicitly disclose that the first gate layer and the first plate are the same material. It would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date to make the first plate and the first gate layer, which are already on the same layer, the same material to reduce the number of masks needed during manufacturing (Hwang, ¶ [0124]).
Re: Dependent Claim 4, Hwang and Peng disclose(s) all the limitations of claim 3 on which this claim depends. Hwang further discloses:
wherein the second plate (Hwang, storage electrode; Fig. 8, element 178) is disposed on the side of the first plate (Hwang, the driving gate electrode; Fig. 8, element 155a) away from the substrate (Hwang, substrate; Fig. 8, element 110); and
and the second plate is disposed between the first plate and the first source-drain layer (Hwang, third data connection member; Fig. 8, element 179), or the second plate and the first source-drain layer are disposed in a same layer (Hwang, Fig. 8, element 178 and element 179 are disposed in the same passivation layer, element 180).
Re: Dependent Claim 5, Hwang and Peng disclose(s) all the limitations of claim 3 on which this claim depends. Hwang further discloses:
wherein the second plate (Hwang, storage electrode; Fig. 8, element 178) is disposed on the side of the first plate (Hwang, the driving gate electrode; Fig. 8, element 155a);
the first thin film transistor (Hwang, light emission control transistor; Fig. 8, element T6, can be considered a first transistor) comprises a gate insulating layer (Hwang, first insulating layer; Fig. 8, element 140) disposed between the first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively) and the first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f), and disposed opposite to the first gate layer (Hwang, Fig. 8 shows elements 140 and 155f are disposed opposite each other); and
and the first dielectric layer (Hwang, second insulating layer; Fig. 8, element 160, ¶ [0110]) and the gate insulating layer are disposed in a same layer (Hwang, Fig. 8, element 140 and element 160 can be considered to be a same layer).
Hwang is silent regarding:
wherein the second plate is disposed on the side of the first plate close to the substrate;
Hwang discloses a second plate, but does not disclose this second plate to be disposed on the side of the first plate close to the substrate. In the absence of any indication that the claimed location is critical or produces unexpected results, a POSITA would have recognized that rearranging the second plate on the side of the first plate closer to the substrate, such as in buffer layer (element 120), will yield a change in capacitance while maintaining the operation of the device unchanged.
Re: Dependent Claim 6, Hwang and Peng disclose(s) all the limitations of claim 5 on which this claim depends. Hwang further discloses:
further comprising a light-shielding layer (Hwang, buffer layer; Fig. 8, element 120) disposed on the side of the first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively) close to the substrate (Hwang, substrate; Fig. 8, element 110),
wherein the second plate (Hwang, storage electrode; Fig. 8, element 178) and the light-shielding layer are disposed in a same layer (Hwang, Fig. 8).
Re: Dependent Claim 7, Hwang and Peng disclose(s) all the limitations of claim 1 on which this claim depends. Hwang further discloses:
wherein the first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f) is disposed on the side of the first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively);
the first plate (Hwang, the driving gate electrode; Fig. 8, element 155a) and the first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f) are disposed in a same layer (Hwang, Fig. 8, elements 155a and 155f are disposed in layer 161);
and the second plate (Hwang, storage electrode; Fig. 8, element 178) is disposed on a side of the first plate away from the substrate (Hwang, substrate; Fig. 8, element 110).
Hwang is silent regarding:
wherein the first gate layer is disposed on the first active layer close to the substrate;
Hwang discloses a gate layer in a multilayer stack which includes a first active layer, but does not disclose this gate layer to be disposed on the side of the first active layer close to the substrate. The claimed modification merely relocates the gate layer to the side of first active layer closer to the substrate. In the absence of any indication that the claimed location is critical or produces unexpected results, a POSITA would have recognized that placing the gate layer on the side of the first active layer closer to the substrate as a routine and predicable modification based on known layer arrangements. Rearranging the relative order of known layers in a stack, where each layer performs a known function, would have been an obvious matter of design choice because positional adjustments are routinely made to optimize fabrication or electrical characteristics, and would have yielded predictable results.
Hwang is silent regarding:
The first plate and the first gate layer comprise a same material;
Hwang discloses that elements on the same layer can be formed of the same material to prevent having to form the element on a different layer using a different material (Hwang, ¶ [0124]), increasing the complexity of the manufacturing process. Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date to make the first plate and the first gate layer, which are already on the same layer, the same material to reduce the number of masks needed during manufacturing (Hwang, ¶ [0124]).
Re: Independent Claim 12, Hwang discloses:
A display panel (Hwang, display device; Fig. 8, ¶ [0005]), comprising:
an array substrate (Hwang, Fig. 8, not numbered) comprising:
a substrate (Hwang, substrate; Fig. 8, element 110) having a pixel area (Hwang, area containing transistor, T6, can be considered a pixel area, ¶ [0066]) and a capacitor area (Hwang, area which contains storage capacitor; Fig. 8, element Cst, can be considered the capacitor area);
a first thin film transistor (Hwang, light emission control transistor; Fig. 8, element T6, can be considered a first thin film transistor) disposed in the pixel area on the substrate, the first thin film transistor comprising a first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively), a first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f) disposed on a side of the first active layer close to the substrate away from the substrate, and a first source-drain layer (Hwang, third data connection member; Fig. 8, element 179) disposed on the side of the first active layer away from the substrate, the first source-drain layer being electrically connected to the first active layer (Hwang, ¶ [0107]); and
a first capacitor (Hwang, storage capacitor; Fig. 8, element Cst) disposed on the substrate, the first capacitor comprising a first plate (Hwang, the driving gate electrode; Fig. 8, element 155a), a second plate (Hwang, storage electrode; Fig. 8, element 178), and a first dielectric layer (Hwang, second insulating layer; Fig. 8, element 160, ¶ [0110]) disposed between the first plate and the second plate;
a metal connection layer (Hwang, pixel electrode, Fig. 6, element 191, ¶ [0140]) disposed on a side of the first thin film transistor away from the substrate (Hwang, Fig. 8); and
and a pixel layer (Hwang, emission member, Fig. 6, LD 370) disposed on a side of the metal connection layer away from the substrate (Hwang, Fig. 8), wherein the metal connection layer is electrically connected to the first source-drain layer and the pixel layer (Hwang, Fig. 8, ¶ [0140]);
the first plate and the second plate are disposed respectively in different layers to be opposite to each other in the capacitor area (Hwang, Fig. 8 shows these plates to be in different vertical layers within the capacitor area);
the first dielectric layer comprises a first dielectric sub-layer (Hwang, second dielectric constant layer; Fig. 8, element 162) and a second dielectric sub-layer (Hwang, first dielectric constant layer; Fig. 8, element 161) disposed on a side of the first dielectric sub-layer close to the first active layer, the second dielectric sub-layer being disposed in the pixel area and the capacitor area (Hwang, Fig. 8);
a dielectric constant of the first dielectric sub-layer is greater than a dielectric constant of the second dielectric sub-layer (Hwang, ¶ [0127]);
an orthographic projection of the first active layer on the substrate is within an orthographic projection of the second dielectric sub-layer on the substrate (Hwang, Fig. 8)
and the second dielectric sub-layer comprises silicon oxide (Hwang, Fig. 8, ¶ [0168] discloses element 161 may include a silicon oxide)
Hwang does not explicitly disclose:
the first dielectric sub-layer comprises aluminum oxide
Peng discloses:
the first dielectric sub-layer (Peng, dielectric layer; Fig. 2C, element 220) comprises aluminum oxide (Peng, ¶ [0030]).
Hwang discloses a first dielectric sub-layer but does not explicitly disclose this sub-layer to comprise aluminum oxide. Peng discloses a dielectric layer to comprise aluminum oxide for use in an array substrate. Both Hwang and Peng disclose array substrates and are therefore analogous art. It would be obvious to a person of ordinary skill in the art (POSITA) before the effective filing date to make the first dielectric sub-layer, as disclosed by Hwang, of aluminum oxide, as disclosed by Peng, for the known benefit of selecting specific dielectric constants of the layer (Peng, ¶ [0030]).
Re: Dependent Claim 14, Hwang and Peng disclose(s) all the limitations of claim 12 on which this claim depends. Hwang further discloses:
wherein the first gate layer (Hwang, a light emission control gate electrode; Fig. 8, element 155f) is disposed on the side of the first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively) away from the substrate (Hwang, substrate; Fig. 8, element 110);
the first plate (Hwang, the driving gate electrode; Fig. 8, element 155a) and the first gate layer are disposed in a same layer (Hwang, Fig. 8, elements 155a and 155f disposed in the same layer); and
the second plate (Hwang, storage electrode; Fig. 8, element 178) is disposed on a side of the first plate away from the substrate or on a side of the first plate close to the substrate.
Hwang is silent regarding:
The first plate and the first gate layer comprise a same material;
Hwang discloses that elements on the same layer can be formed of the same material to prevent having to form the element on a different layer using a different material (Hwang, ¶ [0124]), increasing the complexity of the manufacturing process. Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date to make the first plate and the first gate layer, which are already on the same layer, the same material to reduce the number of masks needed during manufacturing (Hwang, ¶ [0124]).
Re: Dependent Claim 15, Hwang and Peng disclose(s) all the limitations of claim 14 on which this claim depends. Hwang further discloses:
wherein the second plate (Hwang, storage electrode; Fig. 8, element 178) is disposed on the side of the first plate (Hwang, the driving gate electrode; Fig. 8, element 155a) away from the substrate (Hwang, substrate; Fig. 8, element 110); and
and the second plate is disposed between the first plate and the first source-drain layer (Hwang, third data connection member; Fig. 8, element 179), or the second plate and the first source-drain layer are disposed in a same layer (Hwang, Fig. 8, element 178 and element 179 are disposed in the same passivation layer, element 180).
Re: Dependent Claim 16, Hwang disclose(s) all the limitations of claim 14 on which this claim depends. Hwang further discloses:
wherein the second plate (Hwang, storage electrode; Fig. 8, element 178) is disposed on the side of the first plate (Hwang, the driving gate electrode; Fig. 8, element 155a);
the first thin film transistor (Hwang, light emission control transistor; Fig. 8, element T6, can be considered a first transistor) comprises a gate insulating layer (Hwang, first insulating layer; Fig. 8, element 140) disposed between the first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively) and the first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f), and disposed opposite to the first gate layer (Hwang, Fig. 8 shows elements 140 and 155f to be disposed opposite each other); and
and the first dielectric layer (Hwang, second insulating layer; Fig. 8, element 160, ¶ [0110]) and the gate insulating layer are disposed in a same layer (Hwang, Fig. 8, element 140 and element 160 can be considered to be in a same layer).
Hwang is silent regarding:
wherein the second plate is disposed on the side of the first plate close to the substrate;
Hwang discloses a second plate, but does not disclose this second plate to be disposed on the side of the first plate close to the substrate. In the absence of any indication that the claimed location is critical or produces unexpected results, a POSITA would have recognized that placing the second plate on the side of the first plate close to the substrate, such as in buffer layer (element 120), changes the distance between the plates, which is a known result-effective variable affecting the capacitance, yielding a predictable result.
Re: Dependent Claim 17, Hwang and Peng disclose(s) all the limitations of claim 16 on which this claim depends. Hwang further discloses:
wherein the array substrate (Hwang, Fig. 8) further comprises a light-shielding layer (Hwang, buffer layer; Fig. 8, element 120) disposed on the side of the first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively) close to the substrate (Hwang, substrate; Fig. 8, element 110); and
and the second plate (Hwang, storage electrode; Fig. 8, element 178) and the light-shielding layer are disposed in a same layer (Hwang, Fig. 8).
Re: Dependent Claim 18, Hwang and Peng disclose(s) all the limitations of claim 12 on which this claim depends. Hwang further discloses:
wherein the first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f) is disposed on the side of the first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively);
the first plate (Hwang, the driving gate electrode; Fig. 8, element 155a) and the first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f) are disposed in a same layer (Hwang, Fig. 8, elements 155a and 155f are disposed in layer 161); and
the second plate (Hwang, storage electrode; Fig. 8, element 178) is disposed on a side of the first plate away from the substrate (Hwang, substrate; Fig. 8, element 110);
Hwang is silent regarding: wherein the first gate layer is disposed on the side of the first active layer close to the substrate;
Hwang discloses a gate layer in a multilayer stack which includes a first active layer, but does not disclose this gate layer to be disposed on the side of the first active layer close to the substrate. The claimed modification merely relocates the gate layer to the side of first active layer closer to the substrate. In the absence of any indication that the claimed location is critical or produces unexpected results, a POSITA would have recognized that placing the gate layer on the side of the first active layer closer to the substrate as a routine and predicable modification based on known layer arrangements. Rearranging the relative order of known layers in a stack, where each layer performs a known function would have been an obvious matter of design choice because positional adjustments are routinely made to optimize fabrication or electrical characteristics, and would have yielded predictable results.
Hwang is also silent regarding:
The first plate and the first gate layer comprise a same material;
Hwang discloses that elements on the same layer can be formed of the same material to prevent having to form the element on a different layer using a different material (Hwang, ¶ [0124]), increasing the complexity of the manufacturing process. Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date to make the first plate and the first gate layer, which are already on the same layer, the same material to reduce the number of masks needed during manufacturing (Hwang, ¶ [0124]).
Claim(s) 10-11 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hwang (US 20190206969 A1) in view of Peng (US 20050023533 A1) and in further view of Kim (US 8716702 B2).
Re: Dependent Claim 10, Hwang and Peng disclose(s) all the limitations of claim 1 on which this claim depends. Hwang further discloses:
wherein the substrate (Hwang, substrate; Fig. 8, element 110) further has a non-display area (Hwang, Fig. 8, the region outside of the LD region can be considered a non-display area), and the array substrate further comprises a second thin film transistor (Hwang, switching transistor; Fig. 8, element T2, can be considered the second thin film transistor) disposed in the non-display area on the substrate;
there is a gap between an orthographic projection of the second thin film transistor on the substrate and an orthographic projection of the first thin film transistor (Hwang, light emission control transistor; Fig. 8, element T6, can be considered a first transistor) on the substrate;
the second thin film transistor comprises a second active layer (Hwang, second active layer includes: a switching source electrode, a switching channel, and the switching drain electrode; Fig. 8, element 136b, 131b, and 137b, respectively), and the first active layer (Hwang, first active layer includes: a light emission control source electrode, the light emission control channel, and the light emission control drain electrode; Fig. 8, element 136f, 131f, and 137f, respectively) is disposed on a side of the second active layer close to the substrate;
a first gate insulating sub-layer (Hwang, first dielectric constant layer; Fig. 8, element 161) and a second gate layer (Hwang, switching gate electrode; Fig. 8, element 155b) are disposed in sequence on a side of the second active layer away from the substrate;
a second gate insulating sub-layer (Hwang, second dielectric constant layer; Fig. 8, element 162), a third gate insulating sub-layer (Hwang, third dielectric constant layer; Fig. 8, element 163) and the first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f) are disposed in sequence on the side of the first active layer away from the substrate;
a fourth gate insulating sub-layer (Hwang, buffer layer; Fig. 8, ¶ [0117]) is disposed on the side of the second active layer close to the substrate (Hwang, Fig. 8); and
the first gate insulating sub-layer is formed of a same material as the third gate insulating sub-layer (Hwang, ¶ [0128]),
Hwang is silent regarding:
the second gate insulating sub-layer is formed of a same material as the fourth gate insulating sub-layer
Kim discloses:
a fourth gate insulating sub-layer (Kim, a buffer layer; Fig. 4, element 11, Col. 2, lines 18-24).
Hwang discloses that the second gate insulating sub-layer may include a zirconium oxide or a titanium oxide. Hwang discloses that the fourth gate insulating sub-layer (buffer layer) is used to block impurities from the substrate (Hwang, ¶ [0117]), but does not disclose the material. Kim discloses a fourth gate insulating sub-layer (buffer layer) with many suitable materials, including titanium dioxide and zirconium dioxide (Kim, Col. 2, lines 18-24) to flatten the substrate (Kim, Col. 4, lines 59-60). Both Hwang and Kim disclose organic light emitting display devices and their structure and are therefore analogous art. It would have been obvious to a POSITA before the effective filing date to make the buffer layer of Hwang with materials including titanium dioxide or zirconium dioxide, arriving at the claimed invention, for preventing impure elements from penetrating into the substrate (Kim, Col. 4, lines 59-62).
Re: Dependent Claim 11, Hwang, Peng, and Kim disclose(s) all the limitations of claim 10 on which this claim depends. Hwang further discloses:
wherein the second dielectric sub-layer (Hwang, first dielectric constant layer; Fig. 8, element 161) is further disposed in the non-display area (Hwang, Fig. 8, the region outside of the LD region can be considered a non-display area), and an orthographic projection of the second active layer (Hwang, second active layer includes: a switching source electrode, a switching channel, and the switching drain electrode; Fig. 8, element 136b, 131b, and 137b, respectively) on the substrate (Hwang, substrate; Fig. 8, element 110) is within the orthographic projection of the second dielectric sub-layer on the substrate.
Claim(s) 8-9, 19-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Hwang (US 20190206969 A1) in view of Peng (US 20050023533 A1) and in further view of Dong (US 12342620 B2).
Re: Dependent Claim 8, Hwang and Peng disclose(s) all the limitations of claim 1 on which this claim depends. Hwang further discloses:
wherein the first thin film transistor (Hwang, light emission control transistor; Fig. 8, element T6, can be considered a first transistor); and the first gate layer (Hwang, a light emission control gate electrode; Fig. 8, element 155f)
Hwang is silent regarding:
wherein the first thin film transistor is a dual-gate thin film transistor,
Hwang teaches transistors to be configured to be dual gate structure transistors (Hwang, ¶ [0092]) but does not disclose the first thin film transistor to be a dual gate transistor. It would have been obvious to a POSITA before the effective filing date to configure the first thin film transistor to be a dual gate structured transistor to better block the leakage current (Hwang, ¶ [0092]).
Hwang is also silent regarding:
comprises a first gate sub-layer disposed on the side of the first active layer away from the substrate, and a second gate sub-layer disposed on the side of the first active layer close to the substrate.
Dong discloses:
and the first gate layer (Dong, second gate layer; Fig. 2, element 350), comprises a first gate sub-layer (Dong, second gate of the driving transistor; Fig. 2, element 351) disposed on the side of the first active layer (Dong, active layer of the driving transistor; Fig. 2, element 331) away from the substrate (Dong, substrate; Fig. 2, element 110) and a second gate sub-layer (Dong, first gate of the driving transistor; Fig. 2, element 311) disposed on the side of the first active layer close to the substrate.
Hwang discloses a first gate layer but does not disclose this gate layer to have sub-layers and for these sub-layers to have a specific configuration. Dong discloses a first gate sub-layer disposed on the side of the first active layer away from the substrate and a second gate sub-layer disposed on the side of the first active layer close to the substrate for to avoid a patterning operation on another layer (Dong, Col. 7, lines 49-52). Both Hwang and Dong disclose transistor structures and arrangements for use in display devices and are therefore analogous art. It would have been obvious to a POSITA before the effective filing date to use the gate and plate layers and placements taught by Dong to the structure of Hwang to reduce the operations performed on the substrate, reducing overall manufacturing processing and costs (Dong, Col. 7, lines 53-57).
Re: Dependent Claim 9, Hwang, Peng, and Dong disclose(s) all the limitations of claim 8 on which this claim depends. Dong further discloses:
wherein the first plate (Dong, second electrode plate of the storage capacitor; Fig. 2, element 351(352)) and the first gate sub-layer (Dong, second gate of the driving transistor; Fig. 2, element 351) are disposed in a same layer (Dong, Col. 7, lines 17-18 & Col. 16, lines 38-40) and comprise a same material (Col. 9&10, lines 59- 6, and Col. 11, lines 16-18), and the second plate (Dong, first electrode plate of the storage capacitor; Fig. 2, element 312) is disposed on a side of the first plate away from the substrate or on a side of the first plate close to the substrate (Dong, Fig. 2); or
the first plate and the second gate sub-layer are disposed in a same layer and comprise a same material, and the second plate is disposed on the side of the first plate away from the substrate or on the side of the first plate close to the substrate (Dong discloses the first plate and the first gate sub-layer are disposed in the same layer and the second plate is disposed on a side of the first plate away from the substrate or on a side of the first plate close to the substrate).
Re: Dependent Claim 19, Hwang and Peng disclose(s) all the limitations of claim 12 on which this claim depends. Hwang further discloses:
wherein the first thin film transistor (Hwang, light emission control transistor; Fig. 8, element T6, can be considered a first transistor); and the first gate layer (Hwang, a light emission control gate electrode; Fig.8, element 155f);
Hwang is silent regarding:
wherein the first thin film transistor is a dual-gate thin film transistor,
Hwang teaches transistors to be configured to be dual gate structure transistors (Hwang, ¶ [0092]) but does not disclose the first thin film transistor to be a dual gate transistor. It would have been obvious to a POSITA before the effective filing date to configure the first thin film transistor to be a dual gate structured transistor to better block the leakage current (Hwang, ¶ [0092]).
Hwang is also silent regarding:
comprises a first gate sub-layer disposed on the side of the first active layer away from the substrate and a second gate sub-layer disposed on the side of the first active layer close to the substrate.
Dong discloses:
and the first gate layer (Dong, second gate layer; Fig. 2, element 350), comprises a first gate sub-layer (Dong, second gate of the driving transistor; Fig. 2, element 351) disposed on the side of the first active layer (Dong, active layer of the driving transistor; Fig. 2, element 331) away from the substrate (Dong, substrate; Fig. 2, element 110) and a second gate sub-layer (Dong, first gate of the driving transistor; Fig. 2, element 311) disposed on the side of the first active layer close to the substrate.
Hwang discloses a first gate layer but does not disclose this gate layer to have sub-layers and for these sub-layers to have a specific configuration. Dong discloses a first gate sub-layer disposed on the side of the first active layer away from the substrate and a second gate sub-layer disposed on the side of the first active layer close to the substrate for to avoid a patterning operation on another layer (Dong, Col. 7, lines 49-52). Both Hwang and Dong disclose transistor structures and arrangements for use in display devices and are therefore analogous art. It would have been obvious to a POSITA before the effective filing date to use the gate and plate layers and placements taught by Dong to the structure of Hwang to reduce the operations performed on the substrate, reducing overall manufacturing processing and costs (Dong, Col. 7, lines 53-57).
Re: Dependent Claim 20, Hwang, Peng and Dong disclose(s) all the limitations of claim 19 on which this claim depends. Dong further discloses:
wherein the first plate (Dong, second electrode plate of the storage capacitor; Fig. 2, element 351(352)) and the first gate sub-layer (Dong, second gate of the driving transistor; Fig. 2, element 351) are disposed in a same layer (Dong, Col. 7, lines 17-18 & Col. 16, lines 38-40) and comprise a same material (Col. 9&10, lines 59- 6, and Col. 11, lines 16-18), and the second plate (Dong, first electrode plate of the storage capacitor; Fig. 2, element 312) is disposed on a side of the first plate away from the substrate or on a side of the first plate close to the substrate (Dong, Fig. 2); or
the first plate and the second gate sub-layer are disposed in a same layer and comprise a same material, and the second plate is disposed on the side of the first plate away from the substrate or on the side of the first plate close to the substrate (Dong discloses the first plate and the first gate sub-layer are disposed in the same layer and the second plate is disposed on a side of the first plate away from the substrate or on a side of the first plate close to the substrate).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/NIMARTA KAUR CHOWDHARY/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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