Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1, the limitation “the second through electrode is greater than the first through electrode in planar view” does not define what property (cross sectional area, length, thickness, thermal conductivity, or resistivity for example) of the second through electrode that is greater than the first electrode in planar view. For examination purposes, the examiner has interpreted the limitation “the second through electrode is greater than the first through electrode in planar view” to be “the cross-sectional area of the second through electrode is greater than the cross-sectional area of the first through electrode in planar view.”Claims 2-6 are rejected based solely upon their dependency to claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liebmann et al. (US Patent Pub 20220181263 A1) in view of Okamoto et al. (WO 2020066797 A1, see attached machine translation).
Regarding Claim 1, Liebmann teaches a semiconductor integrated circuit device comprising:
a first semiconductor chip, wherein the first semiconductor chip includes (Fig. 1, structures inside and below 123 comprise the first semiconductor chip):
a substrate (Fig. 1, 120);
a first buried power rail formed in a buried interconnect layer in the substrate and supplying first power (Fig. 1, first buried power rail 122. Interconnect layer is entire area of substrate 110. Paragraph 0032-033 teaches 122 is connected to power delivery structure and applies power delivery);
and a first power line formed in a layer above the first buried power rail and supplying second power (Fig. 1, first power line 123. Paragraph 0033 teaches 123 can supply a second power to 122)
the first buried power rail receives supply of the first power from a back face of the first semiconductor chip via a first through electrode (Fig. 1 and paragraph 0033 122 receives supply of first power from a back face of the first semiconductor chip via first through electrode 124),
and the first power line receives supply of the second power from the back face of the first semiconductor chip via a second through electrode (Fig 1, 123 receives supply of second power from the back face of the first semiconductor chip second through electrode 141).
Liebmann fails to teach the cross-sectional area of the second through electrode is greater than the cross-sectional area of the first through electrode in planar view.
However, Okamoto teaches an integrated circuit device wherein the cross-sectional area of the second through electrode is greater than the cross-sectional area of the first through electrode in planar view (Okamato, Figs. 2 and 3 teach the cross-sectional area of the second through electrode 51 (comprised of three vias, therefore the cross-sectional area of all three vias are included in 51) is greater than the cross-sectional area of the first through electrode 21 (comprised of a single via)).
It would have been obvious to one of ordinary skill in the art at the time of invention to incorporate the teachings of Okamoto into the method of Liebmann by forming the integrated circuit device wherein the cross-sectional area of the second through electrode is greater than the cross-sectional area of the first through electrode in planar view. The ordinary artisan would have been motivated to modify Liebmann in the manner set forth above for at least the purpose of using multiple low-resistance wirings connected by a plurality of first and second through electrodes to reduce the overall resistance of the power supply line (Okamoto, paragraphs 0010 and 0011, please see attached machine translation).
Regarding Claim 2, Liebmann teaches the semiconductor integrated circuit device of claim 1, further comprising
a second semiconductor chip stacked on the first semiconductor chip (Fig. 1, structures inside and above 113 comprise the second semiconductor chip)
a principal face of the second semiconductor chip being opposed to a principal face of the first semiconductor chip (Fig. 1, Principal face of first semiconductor chip and second semiconductor chip are facing each other),
wherein the second semiconductor chip receives supply of the second power from the first semiconductor chip through the first power line (Liebmann, Fig. 1, paragraph 0036 teaches second semiconductor chip is electrically connected to first semiconductor chip through structures 140. Further, paragraph 0036 teaches 140 and 141 can penetrate through 123, providing the second semiconductor chip with second power).
Regarding Claim 3, Liebmann teaches the semiconductor integrated circuit device of claim 1, wherein the first semiconductor chip further includes a second power line formed in a layer above the first power line and electrically connected to the first power line (Liebmann, Fig. 1, first semiconductor chip further includes second power line 133 formed in a layer above and electrically connected to 123).
Regarding Claim 4, Liebmann teaches the semiconductor integrated circuit device of claim 1, wherein the first power and the second power are the same in voltage, and in the first semiconductor chip, the first buried power rail and the first power line are electrically connected to each other (Liebmann, Paragraph 0030 teaches the first and second power can be the same voltage. Fig. 1 teaches the first buried power rail 122 and first power line 123 are electrically connected to each other via 124).
Regarding Claim 5, Liebmann teaches the semiconductor integrated circuit device of claim 1, wherein the first semiconductor chip further includes a second buried power rail formed in a buried interconnect layer in the substrate, the second buried power rail receiving no supply of the first power from the back face of the first semiconductor chip and being electrically connected to the first buried power rail (Liebmann, Fig. 1, second buried power rail 140. Second buried power rail extends within substrate 120. 140 does not penetrate device layer 121 and therefore does not receive power from the back face).
Regarding Claim 6, Liebmann in view of Okamoto teaches the semiconductor integrated circuit device of claim 1, wherein the cross-sectional area of the second through electrode is greater than the cross-sectional area of the first through electrode (Okamato, Figs. 2 and 3 teach the cross-sectional area of the second through electrode 51 (comprised of three vias, therefore the cross-sectional area of all three vias are included in 51) is greater than the cross-sectional area of the first through electrode 21 (comprised of a single via)).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-6 have been considered but are moot in view of the new grounds of rejection as applied above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/V.R.G./Examiner, Art Unit 2899
/JOHN M PARKER/Primary Examiner, Art Unit 2899
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