Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liebmann et al. (US Patent Pub 20220181263 A1).
Regarding Claim 1, Liebmann teaches a semiconductor integrated circuit device comprising
a first semiconductor chip, wherein the first semiconductor chip includes (Fig. 1, structures inside and below 123 comprise the first semiconductor chip):
a substrate (Fig. 1, 120);
a first buried power rail formed in a buried interconnect layer in the substrate and supplying first power (Fig. 1, first buried power rail 122. Interconnect layer is entire area of substrate 110. Paragraph 0032-033 teaches 122 is connected to power delivery structure and applies power delivery);
and a first power line formed in a layer above the first buried power rail and supplying second power (Fig. 1, first power line 123. Paragraph 0033 teaches 123 can supply a second power to 122)
the first buried power rail receives supply of the first power from a back face of the first semiconductor chip via a first through electrode (Fig. 1 and paragraph 0033 122 receives supply of first power from a back face of the first semiconductor chip via first through electrode 124),
the first power line receives supply of the second power from the back face of the first semiconductor chip via a second through electrode (Fig 1, 123 receives supply of second power from the back face of the first semiconductor chip second through electrode 141.
and the cross-sectional area of the second through electrode is greater than the cross- sectional area of the first through electrode (Fig. 1, 141 has a greater cross-sectional area than 124).
Regarding Claim 2, Liebmann teaches the semiconductor integrated circuit device of claim 1, further comprising
a second semiconductor chip stacked on the first semiconductor chip (Fig. 1, structures inside and above 113 comprise the second semiconductor chip)
a principal face of the second semiconductor chip being opposed to a principal face of the first semiconductor chip (Fig. 1, Principal face of first semiconductor chip and second semiconductor chip are facing each other),
wherein the second semiconductor chip receives supply of the second power from the first semiconductor chip through the first power line (Fig. 1, paragraph 0036 teaches second semiconductor chip is electrically connected to first semiconductor chip through structures 140. Further, paragraph 0036 teaches 140 and 141 can penetrate through 123, providing the second semiconductor chip with second power).
Regarding Claim 3, Liebmann teaches the semiconductor integrated circuit device of claim 1, wherein the first semiconductor chip further includes a second power line formed in a layer above the first power line and electrically connected to the first power line (Fig. 1, first semiconductor chip further includes second power line 133 formed in a layer above and electrically connected to 123).
Regarding Claim 4, Liebmann teaches the semiconductor integrated circuit device of claim 1, wherein the first power and the second power are the same in voltage, and in the first semiconductor chip, the first buried power rail and the first power line are electrically connected to each other (Paragraph 0030 teaches the first and second power can be the same voltage. Fig. 1 teaches the first buried power rail 122 and first power line 123 are electrically connected to each other via 124).
Regarding Claim 5, Liebmann teaches the semiconductor integrated circuit device of claim 1, wherein the first semiconductor chip further includes a second buried power rail formed in a buried interconnect layer in the substrate, the second buried power rail receiving no supply of the first power from the back face of the first semiconductor chip and being electrically connected to the first buried power rail (Fig. 1, second buried power rail 140. Second buried power rail extends within substrate 120. 140 does not penetrate device layer 121 and therefore does not receive power from the back face).
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicants are directed to consider additional pertinent prior art included on the Notice of Reference Cited (PTO-892) attached herewith.
Conclusion
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/V.R.G./Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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