DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I Species II-2 corresponding to claims 1-10 and Fig (19) in the reply filed on 05/20/2026 is acknowledged.
Claims 11-18 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/20/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/28/2023 was filed after the mailing date of the application on 12/28/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Tsukuda et al, US 20230090409 A1 (Tsukuda) in view of Lee et al, US 20230275150 A1 (Lee).
Regarding claim 1; Tsukuda teaches a semiconductor device (Tsukuda: Annotated Fig (2) shared in this OA: SD) comprising:
a semiconductor substrate (SUB); and
a ferroelectric memory cell (Ferroelectric Memory Cell) formed on the semiconductor substrate (SUB), wherein the ferroelectric memory cell (Ferroelectric Memory Cell) comprises:
a first gate dielectric film (IF1+FEF) formed on the semiconductor substrate (SUB);
a first gate electrode (MGE) formed on the first gate dielectric film (IF1+FEF);
a second gate dielectric film (IF3) formed on the semiconductor substrate (SUB);
a second gate electrode (CGE) formed on the second gate dielectric film (IF3);
a source region (SR) formed in the semiconductor substrate (SUB); and
a drain region (DR) formed in the semiconductor substrate (SUB),
wherein the first gate dielectric film (IF1+FEF) includes a first ferroelectric film (FEF), and
wherein the second gate dielectric film (IF3) includes a second ferroelectric film
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Tsukuda does not teach a second ferroelectric film.
However, Lee teaches a second ferroelectric film (Lee: Fig (9): 3640).
Tsukuda and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Tsukuda by using a second ferroelectric film as disclosed in Lee to improve the speed of switching in the memory cell leading to a better performing device.
Regarding claim 2; Tsukuda in view of Lee teaches all the limitations of the semiconductor device according to claim 1.
Further, Tsukuda teaches wherein the semiconductor substrate(Tsukuda: annotated Fig (2) shared in this OA: SUB) has an upper surface, wherein the first gate dielectric film (IF1+FEF) includes a first dielectric film (IF1) disposed between the semiconductor substrate (SUB) and the first ferroelectric film (FEF), and wherein the second gate dielectric film (IF3) includes a second dielectric film (IF3) disposed between the semiconductor substrate (SUB) and the second ferroelectric film.
Tsukuda does not teach the second ferroelectric film.
Lee teaches the second ferroelectric film (Lee: Fig (9): 3640).
Tsukuda and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Tsukuda by using a second ferroelectric film as disclosed in Lee to improve the speed of switching in the memory cell leading to a better performing device.
Regarding claim 3; Tsukuda in view of Lee teaches all the limitations of the semiconductor device according to claim 2.
Further, Tsukuda teaches wherein a thickness of the first dielectric film (Tsukuda: Annotated Fig (2) shared in this OA: IF1+FEF) is greater than a thickness of the second dielectric film (IF3) in a direction (Z direction) perpendicular to the upper surface of the semiconductor substrate (SUB).
Regarding claim 4; Tsukuda in view of Lee teaches all the limitations of the semiconductor device according to claim 1.
Tsukuda does not teach wherein the semiconductor substrate has an upper surface, and wherein a thickness of the first ferroelectric film is equal to a thickness of the second ferroelectric film in a direction perpendicular to the upper surface of the semiconductor substrate.
However, Lee teaches wherein the semiconductor substrate (Lee: Fig (9): 3701) has an upper surface, and wherein a thickness of the first ferroelectric film (3540) is equal to a thickness of the second ferroelectric film (3640) in a direction perpendicular to the upper surface of the semiconductor substrate(3701).
Tsukuda and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Tsukuda by making the thickness of the second ferroelectric film equal to that of the second ferroelectric film as disclosed in Lee to improve the speed of switching in the device leading to a better performing device.
Regarding claim 5; Tsukuda in view of Lee teach all the limitations of the semiconductor device according to claim 2
Further, Tsukuda teaches wherein the first dielectric film (Tsukuda: Annotated Fig (2) shared in this OA: IF1+FEF) is formed of a silicon oxide film ([0079]), and wherein the second dielectric film (IF3) is formed of a silicon oxide film ([0090]).
Regarding claim 6; Tsukuda in view of Lee teaches all the limitations of the semiconductor device according to claim 1.
wherein the first ferroelectric film (Tsukuda: Annotated Fig (2) shared in this OA: FEF) includes hafnium and oxygen ([0085]: “The material of the ferroelectric film FEF contains, for example, hafnium (Hf) and oxygen (O).”), and wherein the second ferroelectric film includes hafnium and oxygen.
Tsukuda does not teach wherein the second ferroelectric film includes hafnium and oxygen.
Lee teaches wherein the second ferroelectric film (Lee: Fig (9): 3640) includes hafnium and oxygen ([0025]: “In some embodiments, each of the first ferroelectric layer and the second ferroelectric layer may include at least one of hafnium oxide, zirconium oxide, and hafnium-zirconium oxide”).
Tsukuda and Lee are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Tsukuda by constructing the second ferrorelectric film from hafnium and oxygen as disclosed in Lee to improve its ability to maintain polarization which improves its response time leading to a better performing device.
Regarding claim 7; Tsukuda in view of Lee teaches all the limitations of the semiconductor device according to claim 1.
Tsukuda teaches comprising: an impurity region (Tsukuda: Annotated Fig (2) shared in this OA: WR, [0073]) formed in the semiconductor substrate (SUB), wherein the impurity region (WR) is disposed between the source region (SR) and the drain region (DR).
Regarding claim 8; Tsukuda in view of Lee teaches all the limitations of the semiconductor device according to claim 7
Further, Tsukuda teaches wherein the first gate dielectric film (Tsukuda: Annotated Fig (2) shared in this OA: IF1+FEF) is formed on a portion (R1) of the semiconductor substrate (SUB) located between the drain region (DR) and the impurity region (WR), and wherein the second gate dielectric film (IF3) is formed on a portion of the semiconductor substrate (R2) located between the source region (SR) and the impurity region (WR).
Regarding claim 10; Tsukuda in view of Lee teaches all the limitations of the semiconductor device according to claim 1
Further, Tsukuda teaches comprising: an interlayer dielectric film (Tsukuda: Annotated Fig (2) shared in this OA: IL) formed on the semiconductor substrate (SUB) so as to cover the ferroelectric memory cell (Ferroelectric Memory Cell); a first contact plug (PLG) formed in the interlayer dielectric film (IL) and connected to the drain region (DR); and a second contact plug (PLG) formed in the interlayer dielectric film (IL) and connected to the source region (SR).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Tsukuda et al, US 20230090409 A1 (Tsukuda) in view of Lee et al, US 20230275150 A1 (Lee) in view of Yamaguchi, US 20190355584 A1 (Yamaguchi).
Regarding claim 9; Tsukuda in view of Lee teaches all the limitations of the semiconductor device according to claim 1.
Tsukuda in view of Lee does not teach wherein the ferroelectric memory cell comprises: a first metal film disposed between the first ferroelectric film and the first gate electrode; and a second metal film disposed between the second ferroelectric film and the second gate electrode.
However, Yamaguchi teaches wherein the ferroelectric memory cell comprises: a first metal film (Yamaguchi: Fig (22): MF1) disposed between the first ferroelectric film (FEL) and the first gate electrode (G1); and a second metal film (MF1) disposed between the second ferroelectric film (FEL) and the second gate electrode (G1).
Tsukuda in view of Lee and Yamaguchi are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person of ordinary skill in the art, to modify Tsukuda in view of Lee by using the metal film between the ferroelectric films and the gate electrodes as disclosed in Yamaguchi to improve the connectivity between the gate electrode and the ferroelectric film leading to a better performing device.
Conclusion
Prior art made of record but not relied upon is considered pertinent to applicant’s disclosure:
Ogura et al, US 20240164112 A1 (Ogura); discloses two gate electrodes between source and drain regions.
Ha et al, US 20230380176 A1 (Ha); teaches ferroelectric memory devices containing ferroelectric films on dielectric films.
Im et al, US 20230247840 A1 (Im); discloses two ferroelectric films on two dielectric layers.
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/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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