DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the application
Acknowledgment has been made to the amendment received on 07/01/2026. Claims 1-21 are pending in this application. Claims 14-20 withdraw claims. Claims 1-13 and 21 are being examined in this office action.
Claim Rejections - 35 USC § 112
Claims 2-4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Re claim 2 line 3 recites “a size of the second portion in the first direction is larger than a size of the first portion”, claim 3 lines 1-2 recite “the size of the first portion in the first direction is a first size and a size of the first portion “and claim 4 line 1 recite “the first portion and the second portion”. These claims are not clear as to which soldering structure the recited “first portion” and “second portion” belong, whether they are portions of the first soldering structure or the second soldering structure one ordinary skill in the relevant art would not know what structures/steps are covered by the limitations. For these reasons, the claims 2-4 are indefinite.
For best understanding and examination purpose, the claim will be best considered based on drawings, disclosure, and /or any applicable prior arts.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13 and 21 are rejected under 35 U.S.C 103 as being unpatentable over Li et al (CN 114188349A) in view of Choi et al (US20230247832A1).
Re claim 1 Li teaches, a semiconductor structure (400, fig 4) comprising:
a stack structure (412, fig 4) [page10, para 3] comprising alternating conductive layers (439, fig 4) [page 6, para 1] and insulating layers (240, fig 4) [page 6, para 1];
a semiconductor layer (452, fig 4) [page 11, para 2] on the stack structure (412) extending along a first direction (horizontal), wherein the conductive layers (439, fig 4) [page 6, para 1] and insulating layers (440, fig 4) [page , para 1] of the stack structure are alternating along a second direction (vertical) intersecting with the first direction (vertical);
a channel structure (417, fig 4) [page 11, para 2] extending through the stack structure (412, fig 4) [page 11 para 2] and into the semiconductor layer (452, fig 4);
a contact structure (415, fig 4) [page 11, para 2] extending along the second direction (vertical).
a first soldering structure (416/419, fig 4) [page 11, para 4] and a second soldering structure (418/421, fig 4) [page 11, para 4], wherein the first soldering structure (416/419, fig 4) [page 11, para 4] is connected with the contact structure (415, fig 4) and second soldering structure (418/421, fig 4) is connected with the semiconductor layer (452, fig 4).
Li fig 4 does not teach each of the first soldering structure and second soldering structure and second soldering structure comprises a first portion and second portion, wherein the first portion of the first soldering structure penetrates through the semiconductor layer.
Li fig 1e teaches each of the first soldering structure (116,fig 1e) [page 5, para 7] and second soldering structure (118, fig 1e) [page 5, para 7] comprises a first portion (bottom of 116 and bottom of 118) and second portion (top of 116, and top of 118, fig 1e), wherein the first portion (bottom of 116) of the first soldering structure (116) penetrates through the semiconductor layer (152, fig 1e).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by fig 1e into the structure of fig 4 to include each of the first soldering structure and second soldering structure and second soldering structure comprises a first portion and second portion, wherein the first portion of the first soldering structure penetrates through the semiconductor layer as claimed.
The ordinary artisan would have been motivated to modify Li in the above manner for the purpose of improving process technology, circuit design [page 1 para 3].
Li does not teach a largest dimension of the first portion of the second soldering structure in the first direction is smaller than a largest dimension of the first portion of the first soldering structure in the first direction.
Choi teaches a largest dimension of the first portion (bottom of 139, fig 4) [0091] of the second soldering structure (139, fig 4)[0091] in the first direction (lateral) is smaller than a largest dimension of the first portion (bottom of 137, fig 4) [0092] of the first soldering structure (137, fig 4) in the first direction (lateral).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Choi into the structure of Li to include a largest dimension of the first portion of the second soldering structure in the first direction is smaller than a largest dimension of the first portion of the first soldering structure in the first direction as claimed.
The ordinary artisan would have been motivated to modify Li based on the teaching of Choi in the above manner for the purpose of improving functionality of the device.
Further, a change in size is generally recognized as being within the level of ordinary skill in the art. In r rose, 105 USPQ 237 (CCPA 1955) and rearranging part of an invention involves only routine skill in art . In re Jaikse, 86 USPQ 70.
Re claim 2 Li in view of Choi teach the semiconductor structure wherein a size of the second portion (top of 116, fig 1e) [Li, page 6, para 2] in the first direction (horizontal) is larger than a size of the first portion (bottom of 116, fig 1e) in the first direction (horizontal) [Li, page 6, para 2].
Re claim 3 Li in view of Choi teach the semiconductor structure of claim 2, wherein the size of the first portion (416 for first soldering and 418 for second soldering, fig 4) in the first direction (horizontal) is a first size (horizontal size of 416 and 418) and a size of the first portion in the second direction (vertical) is a second size (vertical size of 416 and 418) and a ratio of the second size (vertical size) to the first size (horizontal) is smaller than 1/5 (at least smaller than 1/5). [Li fig 4, page 11, para 2].
Re claim 4 Li in view of Choi teaches the semiconductor structure of claim 2, wherein the first and second portions (top and bottom portions of 116/118, fig 1e), [Li page 10, para 1] are formed integrally.
Re claim 5 Li in view of Choi teaches, the semiconductor structure of claim 1, wherein a portion of the channel structure (top of 417, fig 4) [Li, page 11 para 7] extending into the semiconductor layer (452, fig 4) has a size in the stacking direction (vertical),
Li does not teach the size being smaller than 200 nm.
Li different embodiment fig 2 teaches, the thickness of the semiconductor layer 252 with the thickness 30-300nm, [Page 8 para 3], the channel structure (217, fig 2f) [page 8, page 2] extending into the semiconductor layer, therefore the size being smaller than 200 nm.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Li to include the size being smaller than 200 nm as claimed.
The ordinary artisan would have been motivated to modify Li in the above manner for the purpose of improving reliability.
Since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ233.
Re claim 6 Li in view of Choi teaches the semiconductor structure of claim 1, wherein a top surface of the semiconductor layer (152, fig 1e) right above the channel structure (117, fig 1e) is flush with a top surface (152 in 118 area is flush above the stack structure) of the semiconductor layer (152) right above the stack structure (see fig 1e).
Re claim 7 Li in view of Choi teaches, the semiconductor structure of claim 1, wherein a top surface of the semiconductor layer (152, fig 1e) right above the channel structure (117 1e) is higher than a top surface of the semiconductor layer right above the stack structure. (top surface is 152 is higher than a top surface of 152 above the stack structure due to 118 forming inside the 152 layer, see fig 2) [page 5, para 1].
Re claim 8 Li in view of choi teaches the semiconductor structure of claim 1, wherein materials of the first soldering structure (416/419) and materials of the second soldering structure (418/421) both comprise aluminum. (contact structures including 419 and 421 comprise aluminum) [page 11 para 5].
Re claim 9 Li in view of Choi teaches the semiconductor structure of claim 1, further comprising: an isolating structure (453, fig4) [Li, Page 11 para 2] located at least between the first soldering structure 416, fig 4) and the semiconductor layer (452, fig 4).
Re claim 10 Li in view of Choi teach the semiconductor structure of claim 1,
the stack structure (ST1/ST2, fig 4) [Choi, 0056] further comprises: sacrificial layers (113, fig 4) [Choi, 0069] stacked with the insulating layers (111, fig 4) alternately along the second direction (vertical), and the sacrificial layers (113, fig 4) [Choi, 0069] and the conductive layers (131, fig 4) [Choi, 0054] are arranged side by side (see fig 4) in a direction (horizontal) perpendicular to the second direction (vertical), wherein the contact structure (115, fig 4) penetrates through the sacrificial layers (113, fig 4) and the insulating layers (111, fig 4) and the channel structure (CH, fig 4) [Choi, 0083] penetrates through the conductive layers (131, fig 4) and the insulating layers (111, fig 4) [Choi, 0054],.
Re claim 11 Li teaches the semiconductor structure of claim 1, wherein the channel structure comprises a functional layer (channel plug) [Li, page 10 para 5], located in the stack structure (412, fig 4) and a channel layer (semiconductor channel, fig 4) located in the stack structure (412, fig 4) and extending into the semiconductor layer (452, fig 4) [Li, page 10, para 5].
Re claim 21 I in view of Choi teaches the semiconductor structure of claim 1, wherein a smallest dimension of the first portion (top of 139, fig 4) [Choi,0069] of the second soldering structure (139, fig 4) in the first direction (horizontal) is smaller than a smallest dimension of the first portion (top of 137, fig 4) [Choi, 0054] of the first soldering structure (137, fig 4) [Choi 0054] in the first direction (horizontal).
Re claim 12. Li teaches, a semiconductor device (fig 4), comprising:
a first semiconductor structure (407, fig 4) [Page 9, Para 4]; and
a second semiconductor structure (403, fig4 [Page 9, para 4] comprising: a stack structure (412) [Page 10, para 4]; comprising alternating conductive layers (439, fig 4) [page 6, para 1] and insulating layers (240, fig 4) [page 6, para 1];
a semiconductor layer (452 fig 4) [page 11, para 2] on the stack structure (412) extending along a first direction (horizontal), wherein the conductive layers (439, fig 4) [page 6, para 1] and insulating layers (440, fig 4) [page , para 1] of the stack structure are alternating along a second direction (vertical) intersecting with the first direction (vertical);
a channel structure (417 fig 4) [page 11, para 2] extending through the stack structure and into the semiconductor layer (452, fig 4);
a contact structure (415, fig 4) [Page 11 para 1] extending along the second direction
(vertical) of the stack structure (see fig 4); and
a first soldering structure (416/419, fig 4) and a second soldering structure (418/421, fig 4) [page 11 para 1] wherein the first soldering structure (116, fig 4) is connected with the contact structure (415, fig 4) and the second soldering structure (418/421, fig 4) is connected with the semiconductor layer (452, fig 4),
wherein the first semiconductor structure (407, fig 1e) is located on one of the two opposite sides (left side and right side, fig 4) of the second semiconductor structure (403, fig 4) away from the semiconductor layer (452, fig 2) in the second direction (vertical) and is connected with the second semiconductor structure (403, fig 1e) through hybrid bonding (bonding, fig 4) [page 11, para 2].
Li fig 4 does not teach each of the first soldering structure and the second soldering structure comprises a first portion and a second portion, wherein the first portion of the first soldering structure penetrates through the semiconductor layer wherein the first soldering structure penetrates through the semiconductor layer.
Li fig 1e teaches each of the first soldering structure (116,fig 1e) [page 5, para 7] and second soldering structure (118, fig 1e) [page 5, para 7] comprises a first portion (bottom of 116 and bottom of 118) and second portion (top of 116, and top of 118, fig 1e), wherein the first portion (bottom of 116) of the first soldering structure (116) penetrates through the semiconductor layer (152, fig 1e).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by fig 1e into the structure of fig 4 to include each of the first soldering structure and second soldering structure and second soldering structure comprises a first portion and second portion, wherein the first portion of the first soldering structure penetrates through the semiconductor layer as claimed.
The ordinary artisan would have been motivated to modify Li in the above manner for the purpose of improving process technology, circuit design [page 1 para 3].
Li does not teach a largest dimension of the first portion of the second soldering structure in the first direction is smaller than a largest dimension of the first portion of the first soldering structure in the first direction.
Choi teaches a largest dimension of the first portion (bottom of 139, fig 4) [0091] of the second soldering structure (139, fig 4)[0091] in the first direction (lateral) is smaller than a largest dimension of the first portion (bottom of 137, fig 4) [0092] of the first soldering structure (137, fig 4) in the first direction (lateral).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Choi into the structure of Li to include a largest dimension of the first portion of the second soldering structure in the first direction is smaller than a largest dimension of the first portion of the first soldering structure in the first direction as claimed.
The ordinary artisan would have been motivated to modify Li based on the teaching of Choi in the above manner for the purpose of achieving high integrated structure.
Further, a change in shape is generally recognized as being within the level of ordinary skill in the art. In r Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) and arranging part of an invention involves only routine skill in art. In re Jaikse, 86 USPQ 70.
Re claim 13 Li in view of Choi teaches the semiconductor device of claim 12, wherein the first semiconductor structure (Li, 407, fig 4) [page 11, para 7] comprises:
a peripheral circuitry (peripheral circuit-not shown in the fig) [Li page 11, para 7] connected with the contact structure (415, fig 4) [Li, page 11, para 7] in the second semiconductor structure (403, fig 4) Li, [page 11, para 7].
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al (CN 114188349A) in view of Kim et al (US11791327 B2).
Re claim 1 Li teaches, a semiconductor structure (400, fig 4) comprising:
a stack structure (412, fig 4) [page10, para 3] comprising alternating conductive layers (439, fig 4) [page 6, para 1] and insulating layers (240, fig 4) [page 6, para 1];
a semiconductor layer (452, fig 4) [page 11, para 2] on the stack structure (412) extending along a first direction (horizontal), wherein the conductive layers (439, fig 4) [page 6, para 1] and insulating layers (440, fig 4) [page , para 1] of the stack structure are alternating along a second direction (vertical) intersecting with the first direction (vertical);
a channel structure (417, fig 4) [page 11, para 2] extending through the stack structure (412, fig 4) [page 11 para 2] and into the semiconductor layer (452, fig 4);
a contact structure (415, fig 4) [page 11, para 2] extending along the second direction (vertical).
a first soldering structure (416/419, fig 4) [page 11, para 4] and a second soldering structure (418/421, fig 4) [page 11, para 4], wherein the first soldering structure (416/419, fig 4) [page 11, para 4] is connected with the contact structure (415, fig 4) and second soldering structure (418/421, fig 4) is connected with the semiconductor layer (452, fig 4).
Li fig 4 does not teach each of the first soldering structure and second soldering structure and second soldering structure comprises a first portion and second portion, wherein the first portion of the first soldering structure penetrates through the semiconductor layer.
Li fig 1e teaches each of the first soldering structure (116,fig 1e) [page 5, para 7] and second soldering structure (118, fig 1e) [page 5, para 7] comprises a first portion (bottom of 116 and bottom of 118) and second portion (top of 116, and top of 118, fig 1e), wherein the first portion (bottom of 116) of the first soldering structure (116) penetrates through the semiconductor layer (152, fig 1e).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by fig 1e into the structure of fig 4 to include each of the first soldering structure and second soldering structure and second soldering structure comprises a first portion and second portion, wherein the first portion of the first soldering structure penetrates through the semiconductor layer as claimed.
The ordinary artisan would have been motivated to modify Li in the above manner for the purpose of improving process technology, circuit design [page 1 para 3].
Li does not teach a largest dimension of the first portion of the second soldering structure in the first direction is smaller than a largest dimension of the first portion of the first soldering structure in the first direction.
Kim teaches teach a largest dimension of the first portion (top of 1792 in 200, fig 25) [page 14, line 36] of the second soldering structure (1792/1780, in 200, fig 25) [page 35, line 26] in the first direction (horizontal) is smaller than a largest dimension (top of 1792 in 100, fig 25) [page 14, line 32] of the first portion of the first soldering structure (1792/1780 in 100, fig 25) in the first direction (horizontal).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Kim into the structure of Li to include teach a largest dimension of the first portion of the second soldering structure in the first direction is smaller than a largest dimension of the first portion of the first soldering structure in the first direction as claimed.
The ordinary artisan would have been motivated to modify Li based on the teaching of Kim in the above manner for the purpose of increasing the data transfer speed between the memory-containing die and the logic die.[0252].
Response to Arguments
Applicant’s arguments with respect to claims 1-13, 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zhang et al (US20220302150A1) teaches a 3D memory device including a stack structure including interleaved conductive layers and dielectric layers, a channel structure extending through the stack structure.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRATIKSHA J LOHAKARE whose telephone number is (571)270-1920. The examiner can normally be reached Monday - Friday 7.30 am-4.30 pm.
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/PRATIKSHA JAYANT LOHAKARE/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 9/10/26
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