DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Notes : when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as ( 25 ; Fig 2 ; [00 17 ] or C 18, L 18-37)= (element 25 ; Figure No. 17 ; Paragraph No. [0050]) or Column No 18, Line Nos. 18-17. For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” or “Column No, Line Nos" shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document. Claims 1 ,10 , 2- 5 and 11 - 14 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by LEE; Kuan-Feng (US 20200075703 A 1 ) hereinafter Lee . Regarding Claim s 1, 1 0 . Lee teaches , for claim 10, a display panel (Fig 9 ; [00 35 ] , comprising an array substrate, and the; (For both 1claims 10 and claim 1 ) a n /the array substrate ([00 06 ]), comprising ( see the entire document, Figs 9 and 1-2 , along with subject matter referenced in other figures ; ( Fig 9 is a super structure of Fig 2 ) , specifically, as cited below , : Lee Figure 1 Lee Figure 9 superstructure of Figure 2 an underlay substrate ( 25 ; 9; [0038]; first cited in Fig 2; [00 17 ] , Structure of Fig is within structure of Fig 9, but detailed labelling is given ) and a plurality of sub-pixels ( pixels ; Fig 1; [ 00 16 ]) arranged in an array on the underlay substrate ( 25 ); wherein each of the sub-pixels ( each of the pixels ; [0016] ) at least comprises a first transistor ( 17 ), a second transistor ( 19 ), and a storage capacitor ( 21 detailed [0024] as A storage capacitor 21 is built of the gate electrode 19g, the drain electrode 19d, and the gate insulation layer 29′, the gate insulation layer 29′ is disposed between the gate electrode 19g and the drain electrode 19d ); wherein a drain electrode ( 17d ; Fig s 1-2 ; [00 18 ]) of the first transistor ( 17 ) is connected ([0018]: a bridging line 33 connected to the drain region 17 d and the gate electrode 19 g through two of the through vias ) to a gate electrode ( 19g ) of the second transistor ( 19 ), and the drain electrode ( 17d ) of the first transistor ( 17 ) is connected ( detailed in [0024] as ) to a first electrode plate ( 19g [0024] since 21 is built of the gate electrode 19g, the drain electrode 19d, and the gate insulation layer 29 ) of the storage capacitor ( 21 ); wherein a drain electrode ( 19d ; Fig 2; [00 24 ]) of the second transistor ( 19 ) is connected to a second electrode plate ( 19d since [0024] 21 is built of the gate electrode 19g, the drain electrode 19d, and the gate insulation layer 29 ) of the storage capacitor ( 21 ), the second electrode plate ( 19d ) and the first electrode plate ( 19g ) are disposed opposite to each other, and the second electrode plate ( 18d ) is located on a side of the first electrode plate ( 19g ) away from the underlay substrate ( 25 ) . Regarding Claim 2 , 11 . Lee as applied to the array substrate according to claim 1 and/or display panel according to claim 10 , further teaches, (the substrate) further comprising a first scan line (1 3 ; Fig 1; [0016]) extending along a first direction (horizontal) and a data line ( 11 ) and a first power line ( 15 ) extending along a second direction (vertical) , a source electrode ( 17s ; Fig 2/9) of the first transistor ( 17 ) is connected to the data line ( 1 1 ) , a gate electrode ( 17g ) of the first transistor ( 17 ) is connected to the first scan line ( 1 3 ) , and a source electrode ( 1 9s ) of the second transistor ( 1 9) is connected to the first power line ( 1 5 ) . Regarding Claim 3, 1 2. Lee as applied to the array substrate according to claim 2 and/or display panel according to claim 1 1 , further teaches, (the substrate) further comprising: a first metal layer ( 17g,19g ; Fig 9/2) disposed on a side of the underlay substrate ( 25 ) , wherein the first metal layer comprises the first electrode plate ( 19d ) and the first power line ( 1 5 ) ; a buffer layer ( 27 ) covering the first metal layer away from a side of the underlay substrate ( 2 5 ) ; a semiconductor layer ( 17a ; Fig 2; [0017]) disposed on a side of the buffer layer ( 27 ) away from the first metal layer, wherein the semiconductor layer comprises a first active portion ( 1 7 c ) of the first transistor, a second active portion ( 19c ) of the second transistor, and the second electrode plate ( 19g ) ; a gate electrode insulation layer ( 2 9 ) covering the semiconductor layer ( 17a ) and the buffer layer ( 27 ) ; and a second metal layer ( 11 , 19d ) disposed on a side of the gate electrode insulation layer ( 27 ) away from the semiconductor layer, wherein the second metal layer comprises a gate electrode of the first transistor, a gate electrode of the second transistor, and the first scan line; wherein the first electrode plate ( 19d ) is connected between the gate electrode of the second transistor ( 19 ) and the drain electrode ( 17d ) of the first transistor ( 17 ) . Regarding Claim 4 , 1 3 . Lee as applied to the array substrate according to claim 3 and/or display panel according to claim 1 2 , further teaches, (the substrate) wherein the first metal layer ( 17g, 19g ; Fig 9/2) further comprises a data line ( 11 ) , the second metal layer ( 11 , 19d ) further comprises the source electrode ( 17s ) and the drain electrode ( 17d ) of first transistor ( 17 ) , the source electrode ( 1 9 s ) and the drain electrode ( 1 9d ) of the second transistor ( 1 9 ) , the source electrode of the first transistor is connected to the data line ( 1 1 ) and a side of the first active portion ( 17 c ) , the drain electrode ( 17 d ) of the first transistor ( 17 ) is connected to another side of the first active portion and the first electrode plate (17g) ; the source electrode ( 1 9 s ) of the second transistor (19) is connected to the first power line (15) and an end of the second active portion ( 1 9c ) , the drain electrode ( 1 9d ) of the second transistor ( 1 9 ) is connected to another end of the second active portion ( 1 9c ) and the second electrode plate ( 19g ) . Regarding Claim 5 , 1 4 . Lee as applied to the array substrate according to claim 4 and/or display panel according to claim 1 3 , further teaches, wherein the second metal layer ( 11 , 19d ; fig 9/2) further comprises a first adaptor line (33) extending along the first direction (horizontal) , and the first adaptor line is connected to the first power line (15) and the source electrode ( 19 s ) of the second transistor ( 19 ) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 6- 9 and 1 5-20 are rejected under 35 U.S.C. 103 as being unpatentable over LEE; Kuan-Feng (US 20200075703 A1) hereinafter Lee ; in view of Beak; Jung-Sun et al. ( US 20180166015) hereinafter Beak . Regarding Claim 6. Lee as applied to the array substrate according to claim 3, does not expressly disclose , wherein the array substrate further comprises a detective signal line extending along the second direction; and the sub-pixel further comprises a third transistor, a source electrode of the third transistor is connected to the detective signal line, and a drain electrode of the third transistor is connected to the drain electrode of the second transistor and the second electrode plate. However, in the analogous art, Beak teaches display device having switching and driving transistors TS and TD and the storage capacitor Cst, ([0083]), wherein a structure in which the pixel-driving circuit further includes a sensing transistor. The sensing transistor serves to sense the threshold voltage of the driving transistor TD, and the data voltage is compensated in proportion to the sensed threshold voltage. Herein, because a reference line, which is connected to a source electrode of the sensing transistor, overlaps the data line DL in the vertical direction, with at least one buffer layer 170 , including the organic buffer layer 174 , interposed therebetween, it is possible to accomplish a high-resolution design. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate of Beak ’s teaching into Lee’s array substrate , thereafter, the combination of ( Lee , and Beak ) comprises: a detective signal line (threshold voltage of the driving transistor TD, and the data voltage is compensated in proportion to the sensed threshold voltage) extending along the second direction); and the sub-pixel further comprises a third transistor ( sensing transistor ), a source electrode of the third transistor is connected to the detective signal line, and a drain electrode of the third transistor is connected to the drain electrode of the second transistor and the second electrode plate”, since this inclusion at least will accomplish a high-resolution design ( Beak ’ [0083]) . Regarding Claim 7. The combination of ( Lee , and Beak ) as applied to the array substrate according to claim 6, further teaches, wherein the array substrate further comprises a second scan line ([0018]: not shown) extending along the first direction; and the first metal layer (17g,19g ; Fig 9/2) further comprises the detective signal line, the second metal layer further comprises the second scan line and the source electrode and the drain electrode of the third transistor, the semiconductor layer further comprises third active portion, the source electrode of the third transistor is connected to the detective signal line and an end if the third active portion, the drain electrode of the third transistor is connected to another end of the third active portion and the second electrode plate (obvious from claim 6 r e jection) Regarding Claim 8. The combination of ( Lee , and Beak ) as applied to the array substrate according to claim 6, further teaches, wherein the second metal layer ( 11 , 19d ; Fig 9 /2 ) further comprises a second adaptor line ( obvious from Beak [0083] ) extending along the first direction and connected to the detective signal line (threshold voltage of the driving transistor TD line) and the source electrode of the third transistor. Regarding Claim 9. The combination of ( Lee , and Beak ) as applied to the array substrate according to claim 6, further teaches, wherein in the first direction (horizontal) , adjacent three of the sub-pixels commonly share the first power line (15) and the detective signal line (threshold voltage of the driving transistor TD, and the data voltage is compensated in proportion to the sensed threshold voltage) . Regarding Claim 15 . Lee teaches an array substrate ([0006]), comprising ( see the entire document, Figs 9 and 1-2, along with subject matter referenced in other figures; (Fig 9 is a super structure of Fig 2 ): Lee Figure 1 Lee Figure 2 an underlay substrate ( 25 ; 9; [0038]; first cited in Fig 2; [0017], Structure of Fig is within structure of Fig 9, but detailed labelling is given ) and a plurality of sub-pixels wherein each of the sub-pixels ( each of the pixels ; [0016]) at least comprises a first transistor ( 17 ), a second transistor ( 19 ), and a storage capacitor ( 21 detailed [0024] as A storage capacitor 21 is built of the gate electrode 19g, the drain electrode 19d, and the gate insulation layer 29′, the gate insulation layer 29′ is disposed between the gate electrode 19g and the drain electrode 19d ); wherein a drain electrode (17d; Figs 1-2 ,9 ; [0018]) of the first transistor (17) is connected ([0018]: a bridging line 33 connected to the drain region 17 d and the gate electrode 19 g through two of the through vias ) to a gate electrode (19g) of the second transistor (19), and the drain electrode (17d) of the first transistor ( 17 ) is connected ( detailed in [0024] as ) to a first electrode plate ( 19g [0024] since 21 is built of the gate electrode 19g, the drain electrode 19d, and the gate insulation layer 29 ) of the storage capacitor ( 21 ); wherein a drain electrode ( 19d ; Fig 2 /9 ; [0024]) of the second transistor (19) is connected to a second electrode plate ( 19d since [0024] 21 is built of the gate electrode 19g, the drain electrode 19d, and the gate insulation layer 29 ) of the storage capacitor ( 21 ), the second electrode plate ( 19d ) and the first electrode plate (19g) are disposed opposite to each other, and the second electrode plate ( 18d ) is located on a side of the first electrode plate (19g) away from the underlay substrate ( 25 ). wherein the array substrate further comprises (Fig 9) a first scan line (1 3 ; Fig 1; [0016]) extending along a first direction (horizontal) and a data line ( 11 ) and a first power line ( 15 ) extending along a second direction ( vertical ) , a source electrode ( 17s ; Fig 2 /9 ) of the first transistor ( 17 ) is connected to the data line ( 11 ) , a gate electrode ( 17g ) of the first transistor ( 17 ) is connected to the first scan line ( 13 ) , and a source electrode ( 19s ) of the second transistor ( 19 ) is connected to the first power line ( 15 ) ; a first metal layer ( 17g,19g ; Fig 9 /2 ) disposed on a side of the underlay substrate ( 25 ) , wherein the first metal layer comprises the first electrode plate ( 19d ) and the first power line ( 15 ) ; a buffer layer ( 27 ) covering the first metal layer away from a side of the underlay substrate ( 25 ) ; a semiconductor layer ( 17a ; Fig 2; [0017]) disposed on a side of the buffer layer ( 27 ) away from the first metal layer (17g/19g) , wherein the semiconductor layer ( 17A ) comprises a first active portion ( 17c ) of the first transistor ( 17 ) , a second active portion ( 19c ) of the second transistor ( 19 ) , and the second electrode plate (19g) ; a gate electrode insulation layer (29) covering the semiconductor layer (17a) and the buffer layer (27) ; and a second metal layer (11 , 19d, disposed on a side of the gate electrode insulation layer (29) away from the semiconductor layer (17a) , wherein the second metal layer comprises a gate electrode of the first transistor, a gate electrode of the second transistor, and the first scan line; wherein the first electrode plate (19d) is connected between the gate electrode of the second transistor (19) and the drain electrode (17d) of the first transistor (17) ; But, Lee does not expressly disclose wherein the array substrate further comprises “ a detective signal line (49; Fig 9) extending along the second direction; and the sub-pixel further comprises a third transistor, a source electrode of the third transistor is connected to the detective signal line, and a drain electrode of the third transistor is connected to the drain electrode of the second transistor and the second electrode plate ” . However, in the analogous art, Beak teach es display device having switching and driving transistors TS and TD and the storage capacitor Cst, ([0083]), wherein a structure in which the pixel-driving circuit further includes a sensing transistor. The sensing transistor serves to sense the threshold voltage of the driving transistor TD, and the data voltage is compensated in proportion to the sensed threshold voltage. Herein, because a reference line, which is connected to a source electrode of the sensing transistor, overlaps the data line DL in the vertical direction, with at least one buffer layer 170 , including the organic buffer layer 174 , interposed therebetween, it is possible to accomplish a high-resolution design. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate of Beak ’s teaching into Lee’s array substrate , thereafter, the combination of ( Lee , and Beak ) comprises: a detective signal line ( threshold voltage of the driving transistor TD, and the data voltage is compensated in proportion to the sensed threshold voltage ) extending along the second direction ) ; and the sub-pixel further comprises a third transistor ( sensing transistor ) , a source electrode of the third transistor is connected to the detective signal line, and a drain electrode of the third transistor is connected to the drain electrode of the second transistor and the second electrode plate” , since this inclusion at least will accomplish a high-resolution design ( Be ak ’ [0083]) Regarding Claim 16. The combination of ( Lee , and Beak ) as applied to the array substrate according to claim 15, further teaches, wherein the first metal layer ( 17g,19g ; Fig 9/2) further comprises a data line ( 11 ), the second metal layer ( 11 , 19d ) further comprises the source electrode ( 17s ) and the drain electrode ( 17d ) of first transistor ( 17 ), the source electrode ( 19s ) and the drain electrode ( 19d ) of the second transistor ( 19 ), the source electrode of the first transistor is connected to the data line ( 11 ) and a side of the first active portion ( 17c ), the drain electrode ( 17d ) of the first transistor ( 17 ) is connected to another side of the first active portion and the first electrode plate(17g); the source electrode ( 19s ) of the second transistor (19) is connected to the first power line (15) and an end of the second active portion ( 19c ), the drain electrode ( 19d ) of the second transistor ( 19 ) is connected to another end of the second active portion ( 19c ) and the second electrode plate ( 19g ). Regarding Claim 1 7 . The combination of ( Lee , and Beak ) as applied to the array substrate according to claim 1 6 , further teaches, wherein the second metal layer ( 11. 19d ; fig 9/2) further comprises a first adaptor line (33) extending along the first direction, and the first adaptor line is connected to the first power line (15) and the source electrode ( 19s ) of the second transistor ( 19 ). Regarding Claim 1 8 . The combination of ( Lee , and Beak ) as applied to the array substrate according to claim 1 5 , further teaches wherein wherein the array substrate further comprises a second scan line ([0018]: not shown) extending along the first direction; and the first metal layer (17g,19g ; Fig 9/2) further comprises the detective signal line, the second metal layer further comprises the second scan line and the source electrode and the drain electrode of the third transistor, the semiconductor layer further comprises third active portion, the source electrode of the third transistor is connected to the detective signal line and an end if the third active portion, the drain electrode of the third transistor is connected to another end of the third active portion and the second electrode plate (obvious from claim 15 r e jection) . Regarding Claim 1 9 . The combination of ( Lee , and Beak ) as applied to the array substrate according to claim 1 8 , further teaches , wherein the second metal layer ( 11 , 19d; Fig 0/2 ) further comprises a second adaptor line ( obvious from Beak [0083]) extending along the first direction and (x) connected to the detective signal line (threshold voltage of the driving transistor TD line) and the source electrode of the third transistor. Regarding Claim 20 . The combination of ( Lee , and Beak ) as applied to the array substrate according to claim 1 5 , further teaches , wherein in the first direction (horizontal) , adjacent three of the sub-pixels commonly share the first power line (15) and the detective signal line (threshold voltage of the driving transistor TD, and the data voltage is compensated in proportion to the sensed threshold voltage). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT MOAZZAM HOSSAIN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-7960 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F: 8:30AM - 6:00 PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Julio J. Maldonado can be reached on FILLIN "SPE Phone?" \* MERGEFORMAT 571-272-1864 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOAZZAM HOSSAIN/ Primary Examiner, Art Unit 2898 February 24, 2026