Prosecution Insights
Last updated: May 29, 2026
Application No. 18/399,435

SUBSTRATE HAVING ASYMMETRIC METALLIZATION STRUCTURES DISPOSED ON OPPOSITE SIDES OF A CENTRAL CORE

Non-Final OA §102§103§112
Filed
Dec 28, 2023
Examiner
STARK, JARRETT J
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Qualcomm Incorporated
OA Round
1 (Non-Final)
70%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 70% — above average
70%
Career Allowance Rate
896 granted / 1274 resolved
+2.3% vs TC avg
Moderate +11% lift
Without
With
+11.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
60 currently pending
Career history
1332
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
84.7%
+44.7% vs TC avg
§102
8.6%
-31.4% vs TC avg
§112
1.4%
-38.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1274 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 12 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Improper Claim Scope (Hybrid/Apparatus vs. Component): Claim 12 depends from Claim 6, which defines a specific substrate structure (a core, two sets of metallization layers, and an offset layer). Claim 12 improperly attempts to redefine this specific, structural component as an entire, high-level end-product ("at least one of: a music player, a video player, [etc.]"). The substrate is merely a part of a device, not the device itself. Thus, the claim is indefinite as to whether it claims the substrate structure of Claim 6 or the final electronic device. Breadth and Functional Vagueness: The phrase "comprises at least one of" followed by a long, disparate list of items (e.g., a "fixed location terminal" and a "wearable device" and "a laptop computer") is considered overly broad and functionally vague. It covers nearly every imaginable electronic product without defining which features of the Claim 6 substrate are necessary for, or adapted to, those specific products. Lack of Functional Relationship (Technical Improvement): The claim fails to explain how the specific, claimed substrate structure (offset layer, unequal metallization layers) contributes to any of the listed devices. By merely stating the substrate is part of a device, the claim is "wholly functional" and fails to define the technical improvement within that device, making it impossible to determine the true scope of the invention. Redundancy and Lack of Definiteness: The list of devices is overly broad, mixing types of devices (e.g., "communication device" which could be a smartphone, alongside "mobile phone" and "smartphone" specifically) in a way that makes it difficult to determine the exact scope of the invention. Suggested Correction:To correct these issues, the claim should be amended to clearly define the application of the substrate, rather than redefining the substrate as the end product. Example correction: "The electronic device of claim 6, wherein the substrate is configured for use in at least one of..." or "The electronic device of claim 6, wherein the device is a [specific device]." Prior Art of Record The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-2, 4-7, 9-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chavali et al. (US 10624213 B1). PNG media_image1.png 332 520 media_image1.png Greyscale PNG media_image2.png 314 526 media_image2.png Greyscale CLAIM 1. Chavali teaches a substrate comprising: a core 104/202 having a first surface and a second surface opposite the first surface (Figs. 1 & 2); a first set of metallization layers 120 disposed over the first surface (Figs. 1 & 2); an offset layer structure 116 disposed over the second surface (Figs. 1 & 2 – While the offset layer structure is explicitly labeled as element 116 in Figure 1, an analogous structure appears in Figure 2 without numerical labeling.); and a second set of metallization layers 120 disposed over the second surface wherein the second set of metallization layers includes a larger number of metallization layers than the first set of metallization layers (Figure 2 – Chavali demonstrates a greater number of metallization layers over the analogous “offset layer structure” observable on the second surface of the core 202.). CLAIM 2. Chavali teaches an substrate of claim 1, wherein: the offset layer structure is disposed between metallization layers of the second set of metallization layers (Figs 1 & 2). CLAIM 4. Chavali teaches an substrate of claim 1, further comprising: a first set of one or more connection pads 218 disposed at a first outer surface of the substrate over the first set of metallization layers (Figs 1 & 2). ; and a second set of one or more connection pads 218 disposed at a second outer surface of the substrate over the second set of metallization layers (Figs 1 & 2), wherein the second set of one or more connection pads are spaced from the second surface of the core at a greater distance than the first set of one or more connection pads are spaced from the first surface of the core (Figs 2 – spaced further with the inclusion of offset laminated layer 116 and higher number of metallization layers.). CLAIM 5. Chavali teaches an substrate of claim 1, further comprising: an electronic component 110/210 embedded in the core and electrically coupled to one or more metallization layers of the first set of metallization layers. (Figs 1 & 2). CLAIM 6. (Original) An electronic device, comprising: a substrate comprising: a core104/204 having a first surface and a second surface opposite the first surface (Figs 1 & 2); a first set of metallization layers 118/218 disposed over the first surface (Figs 1 & 2); an offset layer 116 structure disposed over the second surface Figs. 1 & 2 – While the offset layer structure is explicitly labeled as element 116 in Figure 1, an analogous structure appears in Figure 2 without numerical labeling.); and a second set of metallization layers 118/218 disposed over the second surface, wherein the second set of metallization layers includes a larger number of metallization layers than the first set of metallization layers (Figure 2 – Chavali demonstrates a greater number of metallization layers over the analogous “offset layer structure” observable on the second surface of the core 202.). CLAIM 7. Chavali teaches an electronic device of claim 6, wherein: the offset layer structure is disposed between metallization layers of the second set of metallization layers (Figs 1 & 2). CLAIM 9. Chavali teaches an electronic device of claim 6, further comprising: a first set of one or more connection pads 118/218 disposed at a first outer surface of the substrate over the first set of metallization layers (Figs 1 & 2); and a second set of one or more connection pads 118/218 disposed at a second outer surface of the substrate over the second set of metallization layers (Figs 1 & 2), wherein the second set of one or more connection pads are spaced from the second surface of the core at a greater distance than the first set of one or more connection pads are spaced from the first surface of the core (Figs 2 – spaced further with the inclusion of offset laminated layer 116 and higher number of metallization layers.). CLAIM 10. Chavali teaches an electronic device of claim 6, further comprising: an electronic component 110/210 embedded in the core and electrically coupled to one or more metallization layers of the first set of metallization layers (Figs 1 & 2). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 3 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chavali et al. (US 10624213 B1) in view of Hayashi et al. (US 20140327137 A1). CLAIM 3. Chavali teaches an substrate of claim 1, however may be silent upon wherein: the offset layer structure 116 comprises one or more pre-preg (PPG) layers, each PPG layer comprising a fabric that has been impregnated with a resin. While Chavali teaches the offset layer 116 is a laminated layer, Chavali does not specifically teach the layer as a fabric resin impregnated l type of laminated layer. Hayashi teaches an analogous core substrate comprising a dielectric layer with metallization layers on opposing sides. Hayashi further explicitly teaches that dielectric layers—structurally analogous to the "offset structure layer" claimed herein—are known to be formed of a fabric mesh impregnated with resin (e.g., pre-preg). Providing a mesh within a dielectric layer was a well-known, routine method of adding structural strength in insulating layers as needed. Therefore, it would have been obvious to one having ordinary skill in the art (PHOSITA) at the time the invention was made to form the "offset structure layer" of Chavali with the fabric-reinforced resin taught by Hayashi. Such a substitution constitutes the application of a known technique (using fabric mesh for strength) to a known material (dielectric resin) to achieve a predictable result (increased structural strength of the offset layer). It is well-established that selecting a known material on the basis of its suitability for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416. CLAIM 8. Chavali teaches an electronic device of claim 6, however may be silent upon wherein: the offset layer structure 116 comprises one or more pre-preg (PPG) layers, each PPG layer comprising a fabric that has been impregnated with a resin. While Chavali teaches the offset layer 116 is a laminated layer, Chavali does not specifically teach the layer as a fabric resin impregnated l type of laminated layer. Hayashi teaches an analogous core substrate comprising a dielectric layer with metallization layers on opposing sides. Hayashi further explicitly teaches that dielectric layers—structurally analogous to the "offset structure layer" claimed herein—are known to be formed of a fabric mesh impregnated with resin (e.g., pre-preg). Providing a mesh within a dielectric layer was a well-known, routine method of adding structural strength in insulating layers as needed. Therefore, it would have been obvious to one having ordinary skill in the art (PHOSITA) at the time the invention was made to form the "offset structure layer" of Chavali with the fabric-reinforced resin taught by Hayashi. Such a substitution constitutes the application of a known technique (using fabric mesh for strength) to a known material (dielectric resin) to achieve a predictable result (increased structural strength of the offset layer). It is well-established that selecting a known material on the basis of its suitability for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416. Claim(s) 11 & 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chavali et al. (US 10624213 B1) in view of Hsieh et al. (US 10910321 B2). CLAIM 11. Chavali teaches an electronic device of claim 10, however is silent upon wherein: the electronic component comprises at least one deep trench capacitor. Hsieh et al. teaches core substrates with metalization layers on opposing sides were known at the time of the invention to be capable in comprising “deep trench capacitors” It would have been obvious to a POSITA to incorporate the deep trench capacitors taught by Hsieh et al. into the core substrate of Chavali. Because Hsieh demonstrates that such trench capacitors are directly compatible with metallization layers on opposing sides of a core, applying this technique to Chavali is simply a matter of engineering choice to improve electrical performance. Substituting Hsieh’s known structure into Chavali’s, in light of these teachings, produces predictable, expected results in terms of capacitance and density, rendering the claim unpatentable under 35 U.S.C. § 103 (KSR, 550 U.S. 398). CLAIM 12. Chavali in view of Hsiech teaches electronic device of claim 6, wherein the electronic device comprises at least one of: a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, or a device in an automotive vehicle ( Hsiech – Col. 1 lines 10-25 – interposer core substrates are routinely known to be used in electronic devices (computers, tablets, mobile/smart phones/devices, etc.. Note: The subject matter of this claim is unclear. It is not understood how the electronic device (e.g. core substrate) comprises a high-level end-product. For purposes of compact prosecution the claim is interpreted to mean that the electronic device is to be used in one of the listed devices. ). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JARRETT J. STARK Primary Examiner Art Unit 2822 4/29/2026 /JARRETT J STARK/Primary Examiner, Art Unit 2898
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Prosecution Timeline

Dec 28, 2023
Application Filed
May 11, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
70%
Grant Probability
82%
With Interview (+11.2%)
2y 8m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1274 resolved cases by this examiner. Grant probability derived from career allowance rate.

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