Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments directed to the newly amended claim filed 8/7/2026 have been fully considered but they are not persuasive.
The argument that Hayashi teaches away and that the cited art fails to explicitly recite "pre-preg" is unpersuasive.
No Teaching Away: Hayashi’s disclosure of symmetric bonding to prevent warpage represents a preferred design choice for a specific embodiment, not a critique or total prohibition of asymmetric configurations. A reference does not teach away unless it expressly discredits or leads away from the claimed combination.
Compatibility with Asymmetric Structures: Chavali explicitly contemplates asymmetric build-up structures and addresses processing techniques to handle them (Chavali, Col. 1, lines 50-55; Col. 2, lines 21-25). Utilizing known reinforced dielectric materials within Chavali’s recognized asymmetric structure is a logical combination of teachings.
Routine Material Choice and Equivalency: Standard resin compositions, glass-impregnated resin sheets, and pre-pregs (PPG) are art-recognized equivalents for build-up insulating layers in electronic substrates. Selecting or substituting a specific resin-based material or pre-preg layer from known dielectric options represents a routine material substitution yielding predictable structural reinforcement.
Broadest Reasonable Interpretation: Claim terms are given their broadest reasonable interpretation consistent with the specification. Unless explicitly limited by a strict definition in the specification, a generic resin matrix or resin-impregnated sheet encompasses standard pre-preg insulating layers used in substrate lamination.
Accordingly, combining Chavali’s asymmetric architecture with known resin/pre-preg insulating layers renders the claimed subject matter obvious under 35 U.S.C. § 103, and the rejection is maintained.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-7, 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chavali et al. (US 10624213 B1) in view of Hayashi et al. (US 20140327137 A1).
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CLAIM 1. Chavali teaches a substrate comprising:
a core 104/202 having a first surface and a second surface opposite the first surface (Figs. 1 & 2);
a first set of metallization layers 120 disposed over the first surface (Figs. 1 & 2);
an offset layer structure 116 disposed over the second surface (Figs. 1 & 2 – While the offset layer structure is explicitly labeled as element 116 in Figure 1, an analogous structure appears in Figure 2 without numerical labeling.); and
a second set of metallization layers 120 disposed over the second surface wherein the second set of metallization layers includes a larger number of metallization layers than the first set of metallization layers (Figure 2 – Chavali demonstrates a greater number of metallization layers over the analogous “offset layer structure” observable on the second surface of the core 202.).
Chavali teaches an substrate of claim 1, however may be silent upon wherein: the offset layer structure 116 comprises one or more pre-preg (PPG) layers, each PPG layer comprising a fabric that has been impregnated with a resin.
While Chavali teaches the offset layer 116 is a laminated layer, Chavali does not specifically teach the layer as a fabric resin impregnated l type of laminated layer. Hayashi teaches an analogous core substrate comprising a dielectric layer with metallization layers on opposing sides. Hayashi further explicitly teaches ([¶92] & Fig. 1) that dielectric layers, structurally analogous to the "offset structure layer" claimed herein, are known to be formed of a fabric mesh impregnated with resin (e.g., pre-preg). Providing a mesh within a dielectric layer was a well-known, routine method of adding structural strength in insulating layers as needed.
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Therefore, it would have been obvious to one having ordinary skill in the art (PHOSITA) at the time the invention was made to form the "offset structure layer" of Chavali with the fabric-reinforced resin taught by Hayashi. Such a substitution constitutes the application of a known technique (using fabric mesh for strength) to a known material (dielectric resin) to achieve a predictable result (increased structural strength of the offset layer). It is well-established that selecting a known material on the basis of its suitability for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
CLAIM 2. Chavali teaches an substrate of claim 1, wherein: the offset layer structure is disposed between metallization layers of the second set of metallization layers (Figs 1 & 2).
CLAIM 4. Chavali teaches an substrate of claim 1, further comprising: a first set of one or more connection pads 218 disposed at a first outer surface of the substrate over the first set of metallization layers (Figs 1 & 2). ; and
a second set of one or more connection pads 218 disposed at a second outer surface of the substrate over the second set of metallization layers (Figs 1 & 2),
wherein the second set of one or more connection pads are spaced from the second surface of the core at a greater distance than the first set of one or more connection pads are spaced from the first surface of the core (Figs 2 – spaced further with the inclusion of offset laminated layer 116 and higher number of metallization layers.).
CLAIM 5. Chavali teaches an substrate of claim 1, further comprising: an electronic component 110/210 embedded in the core and electrically coupled to one or more metallization layers of the first set of metallization layers. (Figs 1 & 2).
CLAIM 6. (Original) An electronic device, comprising: a substrate comprising: a core104/204 having a first surface and a second surface opposite the first surface (Figs 1 & 2);
a first set of metallization layers 118/218 disposed over the first surface (Figs 1 & 2);
an offset layer 116 structure disposed over the second surface Figs. 1 & 2 – While the offset layer structure is explicitly labeled as element 116 in Figure 1, an analogous structure appears in Figure 2 without numerical labeling.); and
a second set of metallization layers 118/218 disposed over the second surface, wherein the second set of metallization layers includes a larger number of metallization layers than the first set of metallization layers (Figure 2 – Chavali demonstrates a greater number of metallization layers over the analogous “offset layer structure” observable on the second surface of the core 202.).
Chavali teaches an electronic device of claim 6, however may be silent upon wherein: the offset layer structure 116 comprises one or more pre-preg (PPG) layers, each PPG layer comprising a fabric that has been impregnated with a resin.
While Chavali teaches the offset layer 116 is a laminated layer, Chavali does not specifically teach the layer as a fabric resin impregnated l type of laminated layer. Hayashi teaches an analogous core substrate comprising a dielectric layer with metallization layers on opposing sides. Hayashi further explicitly teaches that dielectric layers—structurally analogous to the "offset structure layer" claimed herein—are known to be formed of a fabric mesh impregnated with resin (e.g., pre-preg). Providing a mesh within a dielectric layer was a well-known, routine method of adding structural strength in insulating layers as needed.
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Therefore, it would have been obvious to one having ordinary skill in the art (PHOSITA) at the time the invention was made to form the "offset structure layer" of Chavali with the fabric-reinforced resin taught by Hayashi. Such a substitution constitutes the application of a known technique (using fabric mesh for strength) to a known material (dielectric resin) to achieve a predictable result (increased structural strength of the offset layer). It is well-established that selecting a known material on the basis of its suitability for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
CLAIM 7. Chavali teaches an electronic device of claim 6, wherein: the offset layer structure is disposed between metallization layers of the second set of metallization layers (Figs 1 & 2).
CLAIM 9. Chavali teaches an electronic device of claim 6, further comprising: a first set of one or more connection pads 118/218 disposed at a first outer surface of the substrate over the first set of metallization layers (Figs 1 & 2); and
a second set of one or more connection pads 118/218 disposed at a second outer surface of the substrate over the second set of metallization layers (Figs 1 & 2), wherein the second set of one or more connection pads are spaced from the second surface of the core at a greater distance than the first set of one or more connection pads are spaced from the first surface of the core (Figs 2 – spaced further with the inclusion of offset laminated layer 116 and higher number of metallization layers.).
CLAIM 10. Chavali teaches an electronic device of claim 6, further comprising: an electronic component 110/210 embedded in the core and electrically coupled to one or more metallization layers of the first set of metallization layers (Figs 1 & 2).
Claim(s) 11 & 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chavali et al. (US 10624213 B1) in view of Hsieh et al. (US 10910321 B2).
CLAIM 11. Chavali teaches an electronic device of claim 10, however is silent upon wherein: the electronic component comprises at least one deep trench capacitor.
Hsieh et al. teaches core substrates with metalization layers on opposing sides were known at the time of the invention to be capable in comprising “deep trench capacitors” It would have been obvious to a POSITA to incorporate the deep trench capacitors taught by Hsieh et al. into the core substrate of Chavali. Because Hsieh demonstrates that such trench capacitors are directly compatible with metallization layers on opposing sides of a core, applying this technique to Chavali is simply a matter of engineering choice to improve electrical performance. Substituting Hsieh’s known structure into Chavali’s, in light of these teachings, produces predictable, expected results in terms of capacitance and density, rendering the claim unpatentable under 35 U.S.C. § 103 (KSR, 550 U.S. 398).
CLAIM 12. Chavali in view of Hsiech teaches electronic device of claim 6, the substrate is configured for use in at least one of: a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, or a device in an automotive vehicle ( Hsiech – Col. 1 lines 10-25 – interposer core substrates are routinely known to be used in electronic devices (computers, tablets, mobile/smart phones/devices, etc.. Note: The subject matter of this claim is unclear. It is not understood how the electronic device (e.g. core substrate) comprises a high-level end-product. For purposes of compact prosecution the claim is interpreted to mean that the electronic device is to be used in one of the listed devices. The claim does not provide and further structural distinction over the cited prior art. ).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
8/25/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
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