CTNF 18/399,473 CTNF 79650 DETAILED ACTION Claims 1-16 have been examined. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority Applicant’s claim for the benefit of a prior-filed application (17/355,942) under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Information Disclosure Statement Per MPEP 609.02(I) and (II)(A)(2), the examiner of a continuing application will consider information which has been considered by the Office in the parent application. Therefore, information considered in parent application 17/355,942 has been considered during examination of the instant application. However, if applicant wants said considered information to be printed on any patent resulting from the instant application, applicant must ensure that said information appears on either an IDS or an 892 in the instant application. Specification The title of the invention is not sufficiently descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner recommends inserting --SCALAR/VECTOR-- after “FUSED”. The abstract of the disclosure is objected to because of the following minor informalities: The examiner recommends replacing commas with semicolons after “number” in line 5, after “instruction” in line 5, after “identifiers” in line 6, after “products” in the 3 rd to last line, and after “instruction” in the 2 nd to last line, to improve readability. In line 4, delete “a” before “packed” for improved grammar. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b). 06-31 AIA The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. 07-29 AIA The disclosure is objected to because of the following informalities: Applicant has not fully incorporated corrections made to the parent specification. As such, at least some of the objections set forth in the parent application are applicable herein . Appropriate correction is required. Drawings All FIGs are objected to for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(l), which requires the drawings be in black, and that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. The drawings are pixelated, likely because applicant did not use black (RGB = 000), despite the drawings appearing black to the naked eye. This cannot be confirmed with certainty since the examiner does not have access to applicant’s submitted pdf file. However, it is the examiner’s experience that pixelation usually occurs when black is not being used. In such a case, the dithering used to convert applicant's grayscale image to black and white will add white pixels to try to estimate applicant's "gray" color, and the final drawings may not print properly or may print with reduced quality. Therefore, applicant must be sure to use only black and white. The drawings are objected to because of the following minor informalities: In FIG.1, the middle of the bottom edge of box 110 is incomplete/inconsistent. In FIG.5B, the middle of the bottom edge of box 524 is incomplete/inconsistent. In FIG.9B, to the right of field 950 is a horizontal line that divides boxes 960 and 962A. It appears this line should be deleted. In FIG.10A, under the encoding of the format 1000, it appears that many of the braces/markings have been cut off In FIG.12A, change the single line under 1208, 1210, and 1212, to individual underlines. Check all other drawings for a similar issue. In FIG.12B, boxes 1234, 1250, 1252, and 1264 are incomplete (include a break in the bottom edge). Please check all other drawings for a similar issue. In FIGs.13A-13B, is the arrow supposed to point to inside of 1310 or to the bottom edge? Is the arrow supposed to start inside box 1328 or at the bottom edge. Please check all arrows. FIG.15 appears to be missing portions (e.g. the top edge of box 1520 along with the word “CONTROLLER” (only ‘C’ is shown)). See the parent drawings. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Objections Claim 1 is objected to because of the following informalities: In line 11, insert --the-- before “first real value”. In line 12, insert --the-- before “second real value”. Claim 5 is objected to because of the following informalities: At the end, remove the hyphen after “32”. Claim 6 is objected to because of the following informalities: In line 2, insert a hyphen after both instances of “special”. Claim 9 is objected to because of the following informalities: In line 14, insert --the-- before “first real value”. In line 15, insert --the-- before “second real value”. Claim 13 is objected to because of the following informalities: At the end, remove the hyphen after “32”. 07-29-01 AIA Claim 14 is objected to because of the following informalities: In line 2, insert a hyphen after “special” . Appropriate correction is required. 07-30-03-h AIA Claim Interpretation 07-30-03 AIA The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. 07-30-05 The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. Such claim limitations are: In claim 1, “ a scalar unit to perform the scalar complex multiply operation, the scalar unit to multiply the first and second real values to generate a first real product, to multiply the first and second imaginary values to generate a second real product, to multiply the first imaginary value and first real value to generate a first imaginary product, and to multiply the second imaginary value and second real value to generate a second imaginary product, the scalar unit to generate a real scalar result value using the first and second real products and to generate an imaginary scalar result value using the first and second imaginary products ”. Though not explicitly stated, the examiner understands the scalar unit to include either the structure 300 or 400, each including four multiplier circuits, two adder circuits, and a sign inverter circuit (paragraphs 48 and 54). While FIGs.3-4 are shown in the context of vector operations, it is the examiner’s understanding that the only difference between the scalar and vector versions is that the scalar version will use the hardware 300/400 once while the vector version will use it multiple times. In claim 1, “ a vector unit to perform the vector complex multiply operation, the vector unit to cross-multiply the real value and the imaginary value of each packed vector complex number of the first plurality of packed vector complex numbers with the real value and the imaginary value of a corresponding packed vector complex number of the second plurality of packed vector complex numbers to generate first and second real products and first and second imaginary products, the vector unit to generate a corresponding packed vector complex result comprising a corresponding real result value using the first and second real products and a corresponding imaginary result value using the first and second imaginary products ”. From paragraphs 48, 50, 54, and 56, the vector unit includes at least one instance of structure 300 or 400 in FIGs.3-4. That is, there may be a single instance to determine the results shown in FIGs.3-4, or multiple instances to generate multiple results in parallel. The examiner notes that “ special-purpose logic…to perform scalar complex multiply operations and vector complex multiple operations ” is determined to not invoke 112(f) because it comprises and, thus, is modified by, sufficient structure (register set(s) and structure(s) 300/400) to perform the claimed scalar/vector complex multiply operations. As such, prong (c) of the three-prong test in MPEP 2181(I) is not met. In claim 7 (and similarly claim 15), “ a scheduler unit to schedule a vector complex multiply instruction… ”. Per paragraphs 163 and 166, the scheduler unit is interpreted to encompass a dispatch/issue stage of a processor pipeline, or a reservation station (and equivalents). While a central instruction window is also disclosed in paragraph 166, the structure of this is not clear and thus, the claim is not interpreted to include “central instruction window” unless it would be deemed an equivalent of the dispatch/issue stage and/or reservation station. In claim 8 (and similarly claim 16), “ a numeric conversion unit to perform numeric conversion of values… ”. FIG.13B only shows generic black box numeric conversion units 1322A-B, which are not structurally-detailed in the disclosure. This amounts to an insufficient disclosure of structure for purposes of 112(f) interpretation. As such, broadest reasonable interpretation is taken and 112(a)/(b) rejections are set forth below. In claim 9, “scalar unit”, “vector unit”, “scalar data processing resources”, and “vector data processing resources” are treated/interpreted the same as “scalar unit”, “vector unit”, “special-purpose logic”, and “special-purpose logic”, respectively, in claim 1. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. In claims 1 and 9, applicant claims to cross-multiply the real value and the imaginary value of each packed vector complex number of the first plurality of packed vector complex numbers with the real value and the imaginary value of a corresponding packed vector complex number of the second plurality of packed vector complex numbers to generate first and second real products and first and second imaginary products. Cross-multiplication has a known meaning of multiplying the numerator of each equivalent fraction with the denominator of the other (e.g. multiplying diagonally) (e.g. see Wikipedia, “Cross-multiplication” (not cited herewith)). Based on applicant’s lack of disclosure of equivalent fractions, and based on paragraph 76, applicant intends cross-multiplication to mean something other than what is known, i.e., four multiplications to generate the four claimed products. As such, per the flowchart at the end of MPEP 2111.01, the examiner is to interpret cross-multiplication as applicant has used it. Claim Rejections - 35 USC § 112 07-30-01 AIA The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. 07-31-01 Claims 8 and 16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Referring to claims 8 and 16, as described above in the “Claim Interpretation” section, the disclosure does not provide adequate structure for the numeric conversion unit to perform the corresponding claimed function(s). The specification does not demonstrate that applicant has made an invention that achieves the claimed function(s) because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention. 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claims recite the following limitations for which there is a lack of antecedent basis: In claim 1, line 8, “the scalar complex multiply operation” because there are multiple such operations in lines 3-4. In claim 1, line 21, “the vector complex multiply operation” because there are multiple such operations in line 4. In claim 7, “the vector complex multiply operation” for similar reasoning. In claim 9, line 9, “the scalar complex multiply operation” because there are multiple such operations in lines 4-5. In claim 9, on page 4, line 1, “the vector complex multiply operation” because there are multiple such operations on page 3, 6 th -7 th to last line. In claim 7, “the vector complex multiply operation” for similar reasoning given above. In claim 15, “the vector complex multiply operation” for similar reasoning given above. 07-34-23 Regarding claims 8 and 16, the numeric conversion unit + function limitations invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, as described above in the “Claim Interpretation” section, the written description fails to disclose the corresponding structure(s), material(s), or act(s) for performing the entire claimed function(s) and to clearly link the structure(s), material(s), or act(s) to the function(s). Therefore, the claim(s) are indefinite and are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. Applicant may: (a) Amend the claim(s) so that the claim limitation(s) will no longer be interpreted as a limitation(s) under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph; (b) Amend the written description of the specification such that it expressly recites what structure(s), material(s), or act(s) perform the entire claimed function(s), without introducing any new matter (35 U.S.C. 132(a)); or (c) Amend the written description of the specification such that it clearly links the structure(s), material(s), or act(s) disclosed therein to the function(s) recited in the claim(s), without introducing any new matter (35 U.S.C. 132(a)). If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure(s), material(s), or act(s) and clearly links them to the function(s) so that one of ordinary skill in the art would recognize what structure(s), material(s), or act(s) perform the claimed function(s), applicant should clarify the record by either: (a) Amending the written description of the specification such that it expressly recites the corresponding structure(s), material(s), or act(s) for performing the claimed function(s) and clearly links or associates the structure(s), material(s), or act(s) to the claimed function(s), without introducing any new matter (35 U.S.C. 132(a)); or (b) Stating on the record what the corresponding structure(s), material(s), or act(s), which are implicitly or inherently set forth in the written description of the specification, perform the claimed function(s). For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181. All dependent claims are rejected due to their dependence on an indefinite claim. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-36 AIA Claim s 1-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-3, 1, 1, 1, 1, 1, 1-3, 1, 1, 1, 1, and 1, respectively , of U.S. Patent No. 11,023,231 (as cited by applicant) in view of at least one of the prior art references cited below as part of the prior art rejections (including Official Notice). Of note: Claim 1 is partly anticipated by claim 1 of ‘231 (regarding the math). While claim 1 of ‘231 has not taught the scalar unit and vector unit (and corresponding register sets), as interpreted under 112(f), the structures of Taunton’s FIG.7 would have been an obvious implementation in claim 1 of ‘231 for parallelism, flexibility (since NEGATE and ACC MODE signals can be provided to implement different calculations), and speed realized by register (fast memory) usage. Multiple cores are also known and would have been obvious to implement in claim 1 of ‘231 for increased parallelism. Claim 1 of ‘231 does not teach the single-precision floating-point values of claim 4. However, such values are known in the art and would be obvious to implement in claim 1 of ‘231 to realize floating-point capability according to a known IEEE standard. Claim 1 of ‘231 does not teach the 32-bit values and larger result of claim 5. However, such value sizes are known, especially where multiplication is known to double the size of the inputs for the result. As a result, it would have been obvious to implement these sizes in claim 1 of ‘231. Note that change in size is also a routine expedient, not a patentable distinction (MPEP 2144.04). Claim 1 of ‘231 does not teach multiple special-cores on a die of claim 6. However, a multi-core single die processor is known and would have been an obvious implementation in claim 1 of ‘231 to realize fast communication between components closely packaged onto the same chip. Claim 1 of ‘231 does not teach the scheduler and memory controller+memory of claim 7. However, such components (issue/dispatch stage of pipeline and/or reservation station, per 112(f), and a memory controller to connect to memory) are known to efficiently schedule instructions for execution and also to allow a core to communicate with external memory for increased storage. Claim 1 of ‘231 does not teach the numeric conversion of claim 8. However, such is known in the art and would be obvious to implement in claim 1 of ‘231 to allow for conversion between different data formats, thereby increasing flexibility. Claim 9 is partly anticipated by claim 1 of ‘231 (regarding the math and decoder). The remaining limitations are obvious for similar reasoning set forth in the rejection of claim 1. Claim 12-13 are not patentably distinct from claim 1 of ‘231 for similar reasoning that claims 4-5 are not patentably distinct from claim 1 of ‘231. Claim 1 of ‘231 does not teach the general-purpose core with the instruction circuitry and the special core with the vector circuitry of claim 14. However, Sanghavi has taught such a configuration where a general-purpose core decoded instructions for a special-purpose core that performs complex multiplication. Such an arrangement would be obvious to implement in claim 1 of ‘231 so as to dedicate the special-purpose core to performing specialized tasks (complex multiplication), while the general-purpose core can focus on basic system control and other tasks that it may efficiently perform. Claim 15-16 are not patentably distinct from claim 1 of ‘231 for similar reasoning that claims 7-8 are not patentably distinct from claim 1 of ‘231 . Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-16 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Regarding step 1 of the subject matter eligibility test (hereafter “the test”) in MPEP 2106(III), all claims are directed to a machine. Regarding step 2A (prong 1) of the test, claim 1 recites: “ to perform scalar complex multiply operations and vector complex multiply operations ”, “ to multiply the first and second real values to generate a first real product, to multiply the first and second imaginary values to generate a second real product, to multiply the first imaginary value and first real value to generate a first imaginary product, and to multiply the second imaginary value and second real value to generate a second imaginary product ”, “ to generate a real scalar result value using the first and second real products and to generate an imaginary scalar result value using the first and second imaginary products ”, “ to cross-multiply the real value and the imaginary value of each packed vector complex number of the first plurality of packed vector complex numbers with the real value and the imaginary value of a corresponding packed vector complex number of the second plurality of packed vector complex numbers to generate first and second real products and first and second imaginary products ”, and “ to generate a corresponding packed vector complex result comprising a corresponding real result value using the first and second real products and a corresponding imaginary result value using the first and second imaginary products ”. The aforementioned steps fall into the abstract idea grouping of mathematical concepts, such as mathematical calculation, which can be performed in the human mind with or without pen and paper (see MPEP 2106.04(a)). The examiner notes that performing the scalar multiplication involves multiplying a single pair of complex numbers while the vector multiplication involves multiplying multiple pairs of complex numbers. Regarding step 2A (prong 2) of the test, claim 1 recites the following additional elements: “ A processor comprising: one or more cores to process instructions of a first instruction set architecture ”, “ special-purpose logic coupled to the one or more cores to perform ” the scalar and vector multiply operations, “ a scalar register set to store ” complex numbers that are multiplied, “ a scalar unit ” to perform multiplication and generation of a result. Per 112(f) interpretation, this scalar unit includes hardware 300/400. “ a vector register set to store ” complex numbers that are multiplied, “ a vector unit ” to perform multiplication and generation of a result. Per 112(f) interpretation, this scalar unit includes at least one instance of hardware 300/400, and “ a memory interconnect coupled to the scalar unit and the vector unit ”. These elements amount to generic computing components as a tool to implement the complex number multiplication, insignificant extra-solution activity (storing data), and/or a generic linking of the math to a particular technological environment or fields of use (applicant is linking complex number math to a scalar environment and vector environment). The courts have determined that none of these integrates an abstract idea into a practical application (see MPEP 2106.04(d)(I), last three bullets). Regarding step 2B of the test, the courts have also determined that using a generic computer as a tool to perform an abstract idea, and linking the abstract idea to a particular environment or field of use, do not amount to significantly more (see MPEP 2106.05(I)(A), 2 nd enumerated list, elements (i) and (iv). Further, the storage, into registers, of the data to be multiplied also does not amount to significantly more because the courts have deemed it to be well-understood/routine/conventional activity (again, see MPEP 2106.05(I)(A), along with 2106.05(d)(II), first enumerated list, element (i)). As such, claim 1 is not patent-eligible under 35 U.S.C. 101. Referring to claim 2, applicant only further recites math, including finding the difference between two products and summing the result with an accumulated value, and summing two other products with an accumulated value. Thus, there is no additional element that integrates into a practical application or amounts to significantly more. Thus, claim 2 is not patent-eligible. Claim 3 is not patent-eligible for similar reasoning as claim 2. Referring to claim 4, applicant only further recites the type of data being multiplied as single-precision floating-point data. Thus, this is directed to the abstract idea and there is no additional element integrates into a practical application or amounts to significantly more. This type of data could also alternatively be seen as a link to a particular environment or field of use (floating-point field/environment), which again does not integrate or amount to significantly more. Thus, claim 4 is not patent-eligible. Claim 5 is not patent-eligible for similar reasoning as claim 4, where the size of the data is encompassed by the abstract idea. Or, the size of the data can define a particular environment/field of use. Claim 6 sets forth generic computing components (e.g. multi-core processor) that do not integrate the math into a practical application or amount to significantly more. Thus, claim 6 is not patent-eligible. Claim 7 sets forth generic computing components (issue/dispatch stage of pipeline and/or reservation station, per 112(f) interpretation) that do not integrate the math into a practical application or amount to significantly more. Thus, claim 7 is not patent-eligible. The examiner alternatively notes that scheduling an instruction is extra-solution activity that is known to be well-known, routine, and conventional in the art (Official Notice of such is taken). As such, claim 7 is not patent-eligible for this reason as well. Claim 8 recites the abstract idea of converting values. This is deemed a mental process. Additionally, a generic “numeric conversion unit” to perform the conversion amounts to use of a generic computer to carry out the abstract idea. Thus, claim 8 is not patent-eligible. Claim 9 is generally not patent-eligible for similar reasoning as claim 1, with heterogenous processor, decoder to decode instructions, scalar data processing resources, and vector data processing resources, all being generic computing components that do not integrate the math into a practical application or amount to significantly more. Claims 10-13 are not patent-eligible for similar reasoning as claims 2-5, respectively. Claim 14 merely recites additional generic computing elements to perform the math. They do not integrate into a practical application or amount to significantly more. Alternatively, applicant is linking to a processor/coprocessor environment (general-purpose core/special-purpose core). This does not integrate or amount to significantly more. Claims 15-16 are not patent-eligible for similar reasoning as claims 7-8, respectively. Claim Rejections - 35 USC § 103 07-21-aia AIA Claim s 1-13 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Taunton et al. (US 2005/0193185) in view of the examiner’s taking of Official Notice and Moyer (US 2005/0055534) . Referring to claim 1, Taunton has taught a processor (e.g. paragraph 32) comprising: special-purpose logic to perform vector complex multiply operations (e.g. FIG.7) , the special-purpose logic comprising: a vector register set including a first source vector register (FIG.7, top left) to store a first plurality of packed vector complex numbers (H0-H1 make up a first complex number and H2-H3 make up a second complex number) and a second source vector register (FIG.7, top right) to store a second plurality of packed vector complex numbers (H0-H1 make up a first complex number and H2-H3 make up a second complex number) , each packed vector complex number of the first and second plurality including a real value (H0 and H2 in each register of FIG.7) and an imaginary value (H1 and H3 in each register of FIG.7) , and a vector unit (FIG.7, all hardware shown, which includes four left multipliers and four right multipliers, a respective sign inverter controlled by the negate signal to implement normal vs conjugate/inverse (paragraph 72), and two left adders and two right adders (controlled by accumulate (ACC) mode signal). Note that this hardware corresponds to how the vector unit is interpreted under 112(f) interpretation) to perform the vector complex multiply operation (in FIG.7, the CMACH operation is a complex multiply accumulate halfword operation) , the vector unit to cross-multiply the real value and the imaginary value of each packed vector complex number of the first plurality of packed vector complex numbers with the real value and the imaginary value of a corresponding packed vector complex number of the second plurality of packed vector complex numbers (see the cross-multiplication in FIG.7) to generate first and second real products (e.g. for the four left multipliers, a first real product is H2xH2 (3 rd multiplier from left) and a second real product is H3xH3 (4 th multiplier from left)) and first and second imaginary products (e.g. for the four left multipliers, a first imaginary product is H3xH2 (leftmost multiplier) and a second imaginary product is H2xH3 (2 nd multiplier from left) , the vector unit to generate a corresponding packed vector complex result comprising a corresponding real result value using the first and second real products and a corresponding imaginary result value using the first and second imaginary products (the four products for the for multipliers are used by subsequent circuitry to generate corresponding results) , and a memory interconnect coupled to the vector unit (in order to obtain complex number data from registers in FIG.7, there must be an interconnect leading to/from registers) . Taunton has not taught the special-purpose logic coupled to one or more cores that process instructions of a first instruction set architecture . However, Official Notice is taken that multi-core processors were well known in the art before applicant’s invention. By adding more cores to process ISA instructions, more parallelism is realized, which would translate to increased execution speed since more work can be done simultaneously. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Taunton such that the special-purpose logic is coupled to one or more cores that process instructions of a first instruction set architecture . In other words, the special-purpose logic of Taunton may appear in one core, which is then coupled to another core, which may or may not include its own instance of the special-purpose logic. Alternatively , Official Notice is taken that coupling a core to a SIMD coprocessor/accelerator was well known in the art before applicant’s invention. Such a configuration allows a core without SIMD functionality to offload SIMD work (such as that performed by Taunton) to a coprocessor specialized in efficiently processing SIMD workloads, thereby realizing SIMD functionality in the overall system. As a result, it would have been alternatively obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Taunton such that the special-purpose logic is part of a SIMD coprocessor that is coupled to a non-SIMD core that processes its own ISA instructions. Taunton has also not taught the special-purpose logic comprising: a scalar register set to store a first scalar complex number comprising a first real value and a first imaginary value and a second scalar complex number comprising a second real value and a second imaginary value, and a scalar unit to perform the scalar complex multiply operation, the scalar unit to multiply the first and second real values to generate a first real product, to multiply the first and second imaginary values to generate a second real product, to multiply the first imaginary value and first real value to generate a first imaginary product, and to multiply the second imaginary value and second real value to generate a second imaginary product, the scalar unit to generate a real scalar result value using the first and second real products and to generate an imaginary scalar result value using the first and second imaginary products . However, Moyer has taught instructions that indicate the number of elements in the registers they operate on (e.g. see paragraph 25 and the code in paragraph 77, where an add.h instruction is used to indicate that each 64-bit register includes four 16-bit halfwords. If the add used “.b” instead, each 64-bit register would include eight 8-bit bytes. If the add used “.w”, then each 64-bit register would include two 32-bit words. Being able to specify the number and size of elements increases flexibility. One of ordinary skill in the art would have recognized that instead of each register having two complex numbers comprising four 16-bit halfwords (i.e., CMACH), instructions such as CMACB and CMACW could also be implemented to operate on values of different sizes. With CMACW, each register would have two 32-bit elements, which means that each register would store one complex number. Thus, fewer multipliers/inverters/adders would be needed and such would make up a scalar unit that is merely considering multiply-accumulate for a pair of complex numbers stored in scalar registers (which are now each only holding a single complex number (i.e., a scalar)). As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Taunton to include the ability to dynamically indicate the number/size of elements in registers and utilize only the hardware needed to carry out the respective operations. When only two scalar complex numbers are being processed, the registers holding these numbers are scalar registers and the multipliers/inverters/adders used to carry out the multiply-accumulate would make up a scalar unit. The examiner notes that the scalar unit may be a subset of the vector unit (for instance, the scalar unit could be the left half of FIG.7). Taunton, as modified, has further taught a memory interconnect coupled to the scalar unit (again, for data to get into and out of the registers, there must be a memory interconnect) . Referring to claim 2, Taunton, as modified, has taught the processor of claim 1, wherein the corresponding real result value comprises a sum of a corresponding packed accumulated real value and a difference between the first real product and the second real product, and the corresponding imaginary result value comprises a sum of a corresponding packed accumulated imaginary value, the first imaginary product, and the second imaginary product (as is known, the formula for normal complex multiplication is (a+bi)(c+di) = (ac − bd) + (ad + bc)i. The 3 rd and 4 th multipliers from the left along with the corresponding adders controlled by NEGATE and ACC MODE to implement normal mode will (1) subtract the second real product (bd) from the first real product (ac) and then add that to a packed accumulated value (in 2 nd accumulator from left) and (2) add the imaginary products (ad and bc) to an accumulated imaginary value (in the leftmost accumulator)) . Referring to claim 3, Taunton, as modified, has taught the processor of claim 1, wherein the corresponding real result value comprises a sum of a corresponding packed accumulated real value, the first real product, and the second real product, and the corresponding imaginary result value comprises a sum of a corresponding packed accumulated imaginary value and a difference between the first imaginary product and the second imaginary product (as is known, the a conjugate of a complex number comprises the complex number with its imaginary sign flipped. This results in performing (a+bi)(c-di) = (ac-bd) + (ac-bd)i. The 3 rd and 4 th multipliers from the left along with the corresponding adders controlled by NEGATE and ACC MODE will perform the conjugate multiplication (paragraph 72) add the resulting sums to respective accumulated real and imaginary values in the two leftmost accumulators) . Referring to claim 4, Taunton, as modified, has taught the processor of claim 1, wherein each of the first plurality of packed vector complex numbers, the second plurality of packed vector complex numbers, and the corresponding packed vector complex result are floating point values (see paragraph 84). Taunton has not explicitly taught that they are single-precision floating-point values. However, the examiner first notes that the register size could be any size. While 64-bit registers are taught, Official Notice is taken that 128-bit registers, 256-bit registers, and other size registers were well known in the art before applicant’s invention. Changing the size of the register to a larger size allows for more elements and/or larger elements as well as increased parallelism to speed up processing. For examiner, instead of a 64-bit register holding four 16-bit values for two complex numbers, a 128-bit register could be implemented to hold four 32-bit values for two complex numbers, thereby allowing for a larger range of complex numbers to be represented. Additionally, Official Notice is taken that IEEE single-precision 32-bit floating-point representation was well known in the art before applicant’s invention. Such is a standard format and, thus, one would be motivated to use it to comply with standards. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Taunton to store multiple complex numbers in a packed register in 32-bit floating-point format . Referring to claim 5, Taunton, as modified, has taught the processor of claim 1, but has not taught wherein complex numbers of the first plurality of packed vector complex numbers and the second plurality of packed vector complex numbers comprise 32-bit numbers and the corresponding packed vector complex result is larger than 32-bits . However, for reasons set forth in the rejection of claim 4, it is obvious for each complex number (real portion, imaginary portion) to be a 32-bit value. The complex result includes both a real and imaginary part and thus includes at least 64 bits . Referring to claim 6, Taunton, as modified, has taught the processor of claim 1, wherein the special-purpose logic comprises one or more special-purpose cores (each core may be considered a special-purpose core). While Taunton, as modified, has not taught wherein the one or more special purpose cores and the one or more cores are on a single die , Official Notice is taken that a single die including multiple cores was well known in the art before applicant’s invention. Since all elements are integrated onto a single chip, communication therebetween is faster and the collective would include a smaller footprint than if discrete components were coupled together. Additionally, integration of components into a single package is deemed to be a routine expedient, not a patentable distinction, particularly absent some demonstration of criticality of the integration by applicant (see MPEP 2144.04, including section (V)(B). Here, integration onto a single chip would only provide expected results. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Taunton such that the cores are on a single die. Referring to claim 7, Taunton, as modified, has taught the processor of claim 1, further comprising: an integrated memory controller to couple the processor to a system memory (see paragraph 87. A memory would store a program that is obtained and executed by a processor. The memory must include a memory controller to allow the processor and memory to communicate) ; and a scheduler unit to schedule a vector complex multiply instruction to cause the vector unit to perform the vector complex multiply operation (from the last line of the abstract, and paragraph 6, the processor is pipeline and there is an issue stage to issue instructions for execution, as is known. Note that this is consistent with 112(f) interpretation) . Referring to claim 8, Taunton, as modified, has taught the processor of claim 7, further comprising a numeric conversion unit to perform numeric conversion of values in the vector register set (see paragraphs 50-56) . Claim 9 is mostly rejected for reasons similar to those set forth in the rejection of claim 1. Taunton has further taught instruction processing circuitry including a decoder to decode instructions (all instructions must be decoded to determine the type of operation to be performed and control logic to perform that operation). Claims 10-13 and 15-16 are rejected for similar reasoning as claims 2-5 and 7-8, respectively . 07-21-aia AIA Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Taunton in view of the examiner’s taking of Official Notice, Moyer, and Sanghavi et al. (US 7,376,812) . Referring to claim 14, Taunton, as modified, has taught the heterogeneous processor of claim 9, wherein the vector data processing resources are within one or more special purpose cores of the heterogeneous processor (the logic of FIG.7 is in one special-purpose core). Taunton, as modified, has not taught the instruction processing circuitry is within one or more general purpose cores of the heterogeneous processor . However, Sanghavi has taught a general-purpose core 202 that fetches and decodes instructions and sends coprocessor instructions to a coupled special-purpose core 204, which performs complex number multiplication (see column 5, lines 45-61, column 17, lines 31-39 (where MAC unit 304 is part of core 204), and claim 1). This teaching represents a known processor/coprocessor configuration where a processor focuses on general-purpose tasks and fetching/decoding instructions, and offloading coprocessor instructions to core 204. This allows core 204 to be dedicated to performing its specialized task(s) while the main core to generally control the system and perform simpler tasks including filtering out instructions for itself and core 204. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Taunton such that the instruction processing circuitry is within one or more general purpose cores of the heterogeneous processor. Conclusion 07-96 The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Jouppi (US 5,261,113) has taught a coprocessor with a combined scalar and vector register file. Hinds (GB 2338094) has taught a floating-point coprocessor with both scalar and vector registers. An instruction indicates the type of operand (scalar/vector) to be used. Sugumar (US 5,913,069) has taught a multiprocessor system where each processor has a scalar unit and a vector unit and physical vector registers. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /David J. Huisman/Primary Examiner, Art Unit 2183 Application/Control Number: 18/399,473 Page 2 Art Unit: 2183 Application/Control Number: 18/399,473 Page 3 Art Unit: 2183 Application/Control Number: 18/399,473 Page 4 Art Unit: 2183 Application/Control Number: 18/399,473 Page 5 Art Unit: 2183 Application/Control Number: 18/399,473 Page 6 Art Unit: 2183 Application/Control Number: 18/399,473 Page 7 Art Unit: 2183 Application/Control Number: 18/399,473 Page 8 Art Unit: 2183 Application/Control Number: 18/399,473 Page 9 Art Unit: 2183 Application/Control Number: 18/399,473 Page 10 Art Unit: 2183 Application/Control Number: 18/399,473 Page 11 Art Unit: 2183 Application/Control Number: 18/399,473 Page 13 Art Unit: 2183 Application/Control Number: 18/399,473 Page 14 Art Unit: 2183 Application/Control Number: 18/399,473 Page 15 Art Unit: 2183 Application/Control Number: 18/399,473 Page 16 Art Unit: 2183 Application/Control Number: 18/399,473 Page 17 Art Unit: 2183 Application/Control Number: 18/399,473 Page 18 Art Unit: 2183 Application/Control Number: 18/399,473 Page 19 Art Unit: 2183 Application/Control Number: 18/399,473 Page 20 Art Unit: 2183 Application/Control Number: 18/399,473 Page 21 Art Unit: 2183 Application/Control Number: 18/399,473 Page 22 Art Unit: 2183 Application/Control Number: 18/399,473 Page 23 Art Unit: 2183 Application/Control Number: 18/399,473 Page 24 Art Unit: 2183 Application/Control Number: 18/399,473 Page 25 Art Unit: 2183 Application/Control Number: 18/399,473 Page 26 Art Unit: 2183 Application/Control Number: 18/399,473 Page 27 Art Unit: 2183 Application/Control Number: 18/399,473 Page 28 Art Unit: 2183 Application/Control Number: 18/399,473 Page 29 Art Unit: 2183 Application/Control Number: 18/399,473 Page 30 Art Unit: 2183 Application/Control Number: 18/399,473 Page 31 Art Unit: 2183 Application/Control Number: 18/399,473 Page 32 Art Unit: 2183
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