Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 5/9/2026 is acknowledged.
Applicant’s election with traverse of Species I in the reply filed on 5/9/2026 is also acknowledged.
Claim 20 is withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected claim, there being no allowable generic or linking claim. In addition, claims 3, 14-16 (demultiplexing circuitry not shown in the current embodiment) and 18 (second microcrystalline silicon not shown in the current embodiment) are also withdrawn as they are directed to non-elected embodiments.
Applicant timely traversed the restriction (election) requirement in the reply filed on 5/9/2026.
The examiner finds the traversal of the species as unacceptable.
Species I: Fig. 1 shows the second ohmic contact layer (142) is partially overlapping with yg2 of T2.
Species II: Fig. 2 shows the second ohmic contact layer (142) does not overlap yg2 of T2. Polysilicon y21 is only in the channel region of T2 (para 49).
Species III: Fig. 3 shows Ys2 or Yd2 of a single layer of polysilicon.
The species are not obvious variants but specific embodiments requiring separate field of search causing search burden. Search burden is a broad term and includes different classification groups, different field of search as detailed in MPEP 808.02. Moreover, the applicant has classified these species as different embodiments. As such, the restriction is still deemed proper.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1. Claim(s) 1,2,17 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by US 20210408074 A1 (Xu) in view of CN 105655410 A (Di).
Regarding claim 1, Xu shows (Fig. 1-2) a driving substrate (100, para 46)
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comprising a pixel region (AA, para 46) and a frame region (BB, para 46), the frame region being located on at least one side of the pixel region, the driving substrate comprising:
a base (101, para 46);
first thin film transistors (104’, para 53) disposed on the base and located in the pixel region, wherein each of the first thin film transistors comprises a first active layer; and
second thin film transistors (104, para 53) disposed on the base and located in the frame region, wherein each of the second thin film transistors comprises a second active layer, the second active layer comprises a second channel comprising polysilicon (para 53), and electron mobility of the second thin film transistor is greater than electron mobility of the first thin film transistor (due to crystallization on the peripheral region, para 53).
Xu does not show the first active layer comprises a first amorphous silicon layer and a first microcrystalline silicon layer disposed on a side of the first amorphous silicon layer which is away from the base.
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Di shows (Fig. 2) the first active layer comprises a first amorphous silicon layer (42) and a first microcrystalline silicon layer (41) disposed on a side of the first amorphous silicon layer which is away from the base.
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Di, with active layer having first amorphous silicon layer and a first microcrystalline silicon layer, to the invention of Xu.
The motivation to do so is that the combination produces the predictable result of reducing back channel leakage current and guarantee the ratio of on-state current to off-state current without reducing the front channel active layer is a microcrystalline silicon thin film, device mobility increases, it can increase the on-state current (Pg-8-9).
Regarding claim 2, Xu in view of Di shows wherein the first active layer (Di, 42) comprises a first source contact portion (42 below 5 left and 6), a first drain contact portion (42 below 7 and 5 right), and a first channel (remaining portion of 42 between source and drain), the first source contact portion is connected to one side of the first channel, the first drain contact portion is connected to an other side of the first channel, wherein the first source contact portion, the first drain contact portion, and the first channel each comprise the first amorphous silicon layer and the first microcrystalline silicon layer stacked;
the second active layer comprises a second source contact portion (Xu, 104 portion below 105) and a second drain contact portion (Xu, 104 portion below 106), the second source contact portion is connected to one side of the second channel (remaining portion of 104 between source and drain), the second drain contact portion is connected to an other side of the second channel, and at least a portion of the second source contact portion and at least a portion of the second drain contact portion are each made of the polysilicon.
Regarding claim 17, Xu shows (Fig. 1-2) a display panel comprising a driving substrate (100, para 46) comprising a pixel region (AA, para 46) and a frame region (BB, para 46), the frame region being located on at least one side of the pixel region, the driving substrate comprising: a base (101, para 46);
first thin film transistors (104’, para 53) disposed on the base and located in the pixel region, wherein each of the first thin film transistors comprises a first active layer, and
second thin film transistors (104, para 53) disposed on the base and located in the frame region, wherein each of the second thin film transistors comprises a second active layer, the second active layer comprises a second channel, the second active layer comprises polysilicon (para 53) at least in the second channel, and electron mobility of the second thin film transistor is greater than electron mobility of the first thin film transistor (due to crystallization on the peripheral region, para 53).
Xu does not show the first active layer comprises a first amorphous silicon layer and a first microcrystalline silicon layer disposed on a side of the first amorphous silicon layer which is away from the base.
Di shows (Fig. 2) the first active layer comprises a first amorphous silicon layer (42) and a first microcrystalline silicon layer (41) disposed on a side of the first amorphous silicon layer which is away from the base.
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Di, with active layer having first amorphous silicon layer and a first microcrystalline silicon layer, to the invention of Xu.
The motivation to do so is that the combination produces the predictable result of reducing back channel leakage current and guarantee the ratio of on-state current to off-state current without reducing the front channel active layer is a microcrystalline silicon thin film, device mobility increases, it can increase the on-state current (Pg-8-9).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claim(s) 4,5,6,9,19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Di.
Regarding claim 4, Xu in view of Di shows wherein the polysilicon is formed.
As per the claim limitation “wherein the polysilicon is formed by crystallizing a fourth amorphous silicon layer and a fourth microcrystalline silicon layer, which are stacked, as a monolithic crystal, the fourth amorphous silicon layer is provided in a same layer as the first amorphous silicon layer, and the fourth microcrystalline silicon layer is provided in a same layer as the first microcrystalline silicon layer”, which is drawn to process steps of a product-by-process claim, such method step(s) are not considered to render an old apparatus patentable where the prior art teaches a product that appears to be the same as, or an obvious variant of, the product set forth in a product-by-process claim although produced by a different process. In the regard, both the claimed product and the prior art product would be the same or substantially the same. That is even though product-by-process claims are limited and defined by the process, the determination of patentability of the claims is based on the product itself. The patentability of a product does not depend on its method of production. See MPEP 2113.
Regarding claim 5, Xu in view of Di shows wherein the polysilicon is formed.
As per the claim limitation “wherein the polysilicon is formed by crystallizing a fourth amorphous silicon layer and a fourth microcrystalline silicon layer, which are stacked, as a monolithic crystal, the fourth amorphous silicon layer is provided in a same layer as the first amorphous silicon layer, and the fourth microcrystalline silicon layer is provided in a same layer as the first microcrystalline silicon layer”, which is drawn to process steps of a product-by-process claim, such method step(s) are not considered to render an old apparatus patentable where the prior art teaches a product that appears to be the same as, or an obvious variant of, the product set forth in a product-by-process claim although produced by a different process. In the regard, both the claimed product and the prior art product would be the same or substantially the same. That is even though product-by-process claims are limited and defined by the process, the determination of patentability of the claims is based on the product itself. The patentability of a product does not depend on its method of production. See MPEP 2113.
Regarding claim 6, Xu in view of Di shows wherein the polysilicon is formed.
As per the claim limitation “wherein the polysilicon is formed by crystallizing a fourth amorphous silicon layer and a fourth microcrystalline silicon layer, which are stacked, as a monolithic crystal, the fourth amorphous silicon layer is provided in a same layer as the first amorphous silicon layer, and the fourth microcrystalline silicon layer is provided in a same layer as the first microcrystalline silicon layer”, which is drawn to process steps of a product-by-process claim, such method step(s) are not considered to render an old apparatus patentable where the prior art teaches a product that appears to be the same as, or an obvious variant of, the product set forth in a product-by-process claim although produced by a different process. In the regard, both the claimed product and the prior art product would be the same or substantially the same. That is even though product-by-process claims are limited and defined by the process, the determination of patentability of the claims is based on the product itself. The patentability of a product does not depend on its method of production. See MPEP 2113.
Regarding claim 9, Xu in view of Di shows wherein a thickness of the first microcrystalline silicon layer is between 10% and 30% of a thickness of the first active layer (Pg 4 of Di, first microcrystalline silicon layer thickness 10 nm to 20nm and a-silicon 40nm to 60 nm or first active layer thickness of 50nm to 80nm where the ratio is 20% (10nm/50nm)).
Regarding claim 19, the prior art/s as noted in the above rejection of claim 4, discloses the entire claimed invention.
2. Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Di, as applied to claim 1 above, further in view of US 20180166326 A1 (Kumar).
Regarding claim 7, Xu in view of Di shows the polysilicon.
Xu in view of Di is silent regarding wherein the polysilicon has a grain width greater than 2 microns.
Kumar shows wherein the polysilicon has a grain width greater than 2 microns (para 32 with 71).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Kumar, with grain width, to the invention of Xu in view of Di.
The motivation to do so is that the combination produces the predictable result of higher device channel mobility (para 71).
Regarding claim 8, Xu in view of Di shows the polysilicon.
Xu in view of Di is silent regarding wherein the polysilicon has a grain width greater than 6 microns.
Kumar shows wherein the polysilicon has a grain width greater than 6 microns (para 32 with 71).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Kumar, with grain width, to the invention of Xu in view of Di.
The motivation to do so is that the combination produces the predictable result of higher device channel mobility (para 71).
3. Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Di, as applied to claim 2 above, further in view of US 20180374956 A1 (Lee).
Regarding claim 10, Xu in view of Di shows wherein the driving substrate further comprises a gate insulating layer, the first thin film transistor comprises a first gate, the second thin film transistor comprises a second gate, the first gate and the second gate are both disposed on the base, the gate insulating layer covers the first gate and the second gate, the first active layer is disposed on a side of the gate insulating layer which is away from the base, and the second active layer is disposed on a side of the gate insulating layer which is away from the base;
in an orthographic projection pattern of the driving substrate, the first active layer and the first gate are overlapped, and the second active layer and the second gate are overlapped;
the gate insulating layer.
Xu in view of Di does not show the gate insulating layer
comprises a silicon oxide layer and a silicon nitride layer, the silicon nitride layer is disposed on a side of the silicon oxide layer which is away from the base.
Lee shows (Fig. 7B) the gate insulating layer (150)
comprises a silicon oxide layer (151, para 126) and a silicon nitride layer (152, para 126), the silicon nitride layer is disposed on a side of the silicon oxide layer which is away from the base (101).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Lee, with bi-layered gate dielectric, to the invention of Xu in view of Di.
The motivation to do so is that the combination produces the predictable result of moisture prevention and leakage control ability.
4. Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Di and Lee, as applied to claim 10 above, further in view of US 20150206976 A1 (Song).
Regarding claim 11, Xu in view of Di and Lee shows the silicon nitride layer is greater and the silicon oxide layer.
Xu in view of Di and Lee does not show wherein a thickness of the silicon nitride layer is greater than a thickness of the silicon oxide layer.
Song shows wherein a thickness of the silicon nitride layer is greater than a thickness of the silicon oxide layer (claim 11).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Song, with greater thickness of silicon nitride, to the invention of Xu in view of Di and Lee.
The motivation to do so is that the combination produces better moisture prevention.
5. Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Di and Lee, as applied to claim 10 above, further in view of US 20120085998 A1 (Kwon).
Regarding claim 12, Xu in view of Di and Lee shows the silicon nitride layer is greater and the silicon oxide layer.
Xu in view of Di and Lee does not show wherein a thickness of the silicon oxide layer is less than or equal to 250 nm, and a thickness of the silicon nitride layer is between 200 nm and 400 nm.
Kwon shows wherein a thickness of the silicon oxide layer (10) is less than or equal to 250 nm, and a thickness of the silicon nitride layer (20) is between 200 nm and 400 nm (para 64).
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Kwon, with greater thickness of silicon nitride, to the invention of Xu in view of Di and Lee.
The motivation to do so is that the combination produces better moisture prevention.
6. Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Di and Lee, as applied to claim 10 above, further in view of US 20220415654 A1 (Kang).
Regarding claim 13, Xu in view of Di and Lee shows the first thin film transistor further comprises a first source and a first drain, and the second thin film transistor further comprises a second source and a second drain.
Xu in view of Di and Lee does not show a first ohmic contact layer, a second ohmic contact layer;
a portion of the first ohmic contact layer is provided on the first source contact portion, an other portion of the first ohmic contact layer is provided on the first drain contact portion, the first source is connected to the first source contact portion through the portion of the first ohmic contact layer, and the first drain is connected to the first drain contact portion through the other portion of the first ohmic contact layer;
a portion of the second ohmic contact layer is provided on the second source contact portion, an other portion of the second ohmic contact layer is provided on the second drain contact portion, the second source is connected to the second source contact portion through the portion of the second ohmic contact layer, and the second drain is connected to the second drain contact portion through the other portion of the second ohmic contact layer.
Kang shows (Fig. 1) an ohmic contact layer (135, para 52) between source (140) and source contact portion (130 below 135 left) or drain (150) and the drain contact portion (130 below 135 right).
Xu in view of Di and Lee in combination with Kang teaches the whole limitation.
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Kang, with ohmic contact layer, to the invention of Xu in view of Di and Lee.
The motivation to do so is that the selection of an art recognized ohmic contact of Kang is suitable for the intended use of Xu in view of Di and Lee (MPEP §2144.07).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WASIUL HAIDER whose telephone number is (571)272-1554. The examiner can normally be reached M-F 9 a.m. - 6 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WASIUL HAIDER/Primary Examiner, Art Unit 2812
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