Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21-23 and 26-27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0237540 A1 Gao et al (herein “Gao”).
Regarding Claim 21, Gao discloses:
A manufacturing method of a semiconductor device (see generally Fig. 1 and descriptive paragraphs [0008]-[0017]), the method comprising:
forming an amorphous silicon layer (#3, Fig. 1, [0008]: “the thin film layer(s) 3 is/are arranged on the device substrate 1 or/and the supporting substrate 2, and is/are one of a silicon dioxide layer, a silicon oxynitride layer, a silicon nitride layer, a polysilicon layer and an amorphous silicon layer.” emphasis added) on a crystalline silicon layer (#1, Fig. 1, [0008], [0030]); and
forming a dielectric layer (#4, Fig. 1, [0008]) on the amorphous silicon layer (#3),
wherein the dielectric layer (#4) includes silicon oxynitride (Fig. 1, [0008]).
Regarding Claim 22, Gao discloses:
The method of claim 21, wherein the amorphous silicon layer (#3) is generated through a first plasma treatment process ([0031], [0053], [0085], [0108]) of reacting a portion of the crystalline silicon layer (#1) with a first plasma (multilayer SOI structure formed by using PECVD process [0053], i.e. forming multiple layers to meet specific device needs, see also [0054]).
Regarding Claim 23, Gao discloses:
The method of claim 22, wherein the first plasma is generated from a source gas including argon ([0033]: “wherein according to different materials of the thin film layers 3, gases used in deposition are oxygen, hydrogen, nitrogen, silane, nitrous oxide, hydrogen and argon with flow rates of 0-20 slm, 0-10 slm, 0-1 slm, 0-25 sccm, 0-20 sccm, 0-50 sccm and 0-60 sccm respectively” emphasis added).
Regarding Claim 26, Gao discloses: The semiconductor device of claim 21,
wherein a thickness of the amorphous silicon layer (#3) is between about 1 nm and about 200 nm ([0015]).
Regarding Claim 27, Gao discloses: The semiconductor device of claim 21,
wherein a thickness of the dielectric layer (#4) is between about 1 nm and about 200 nm ([0015]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0237540 A1 Gao et al (herein “Gao”) in view of Study of the mechanical and structural properties of silicon oxynitride films for optical applications Criado et al (herein “Criado”).
Regarding Claim 1, Gao discloses:
A semiconductor device (see generally Fig. 1 and descriptive paragraphs [0008]-[0017]) comprising:
a crystalline silicon layer (#1, Fig. 1, [0008], [0030]);
an amorphous silicon layer (#3, Fig. 1, [0008]: “the thin film layer(s) 3 is/are arranged on the device substrate 1 or/and the supporting substrate 2, and is/are one of a silicon dioxide layer, a silicon oxynitride layer, a silicon nitride layer, a polysilicon layer and an amorphous silicon layer.” emphasis added) on the crystalline silicon layer (#1) and extending along a first surface of the crystalline silicon layer (#1); and
a dielectric layer (#4, Fig. 1, [0008]) on the amorphous silicon layer (#3) and extending along a surface of the amorphous silicon layer (#3),
wherein the dielectric layer (#4) includes silicon oxynitride (Fig. 1, [0008])
Gao does not explicitly disclose:
wherein the dielectric has compressive stress.
However, in analogous art, Criado teaches:
wherein the silicon oxynitride dielectric has compressive stress (abstract discloses “studies on the residual stress and structure of silicon oxynitride films deposited by PECVD with nitrogen atomic percent varying from 24 to 55.”).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider utilizing the PECVD deposition of a silicon oxynitride layer, like disclosed by Criado, to form the claimed dielectric layer. Doing so would be swapping the atomic layer deposition (ALD) method of forming the layer disclosed by Gao (see [0035]) for the PECVD method wherein the layer would subsequently have the claimed property of having compressive stress, see Criado abstract and results. Doing so would be a simple substitution of one known method known in the art of forming a dielectric layer for another to achieve a predictable result.
Regarding Claim 2, Gao in view of Criado discloses: The semiconductor device of claim 1,
Gao further discloses:
wherein the amorphous silicon layer (#3) is in direct contact with the first surface (top surface) of the crystalline silicon layer (#1),
wherein the dielectric layer (#4) is in direct contact with the surface (top surface) of the amorphous silicon layer (#3), and
wherein the dielectric layer (#4) separates from the crystalline silicon layer (#1) with the amorphous silicon layer (#3) disposed between the dielectric layer (#4) and the crystalline silicon layer (#1).
Regarding Claim 3, Gao in view of Criado discloses: The semiconductor device of claim 1,
Gao further discloses:
wherein a thickness of the amorphous silicon layer (#3) is between about 1 nm and about 200 nm ([0015]).
Regarding Claim 4, Gao in view of Criado discloses: The semiconductor device of claim 1,
Gao further discloses:
wherein a thickness of the dielectric layer (#4) is between about 1 nm and about 200 nm ([0015]).
Regarding Claim 5, Gao in view of Criado discloses: The semiconductor device of claim 1,
Gao further discloses:
wherein the dielectric layer (#4) comprises at least one of:
a binary compound including a silicon element and a nitrogen element ([0035]),
a ternary compound including a silicon element, a nitrogen element, and a hydrogen element ([0035]), and
a quaternary compound including a silicon element, a nitrogen element, an oxygen element, and a hydrogen element ([0035]).
Regarding Claim 6, Gao in view of Criado discloses: The semiconductor device of claim 1,
Gao further discloses:
wherein the dielectric layer (#4) does not comprise carbon ([0035]).
Claims 7-10 and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0237540 A1 Gao et al (herein “Gao”) in view of Study of the mechanical and structural properties of silicon oxynitride films for optical applications Criado et al and further in view of US 2023/0062468 A1 Chiu et al (herein “Chiu”).
Regarding Claim 7, Gao in view of Criado discloses: The semiconductor device of claim 1,
Gao in view of Criado does not explicitly disclose:
further comprising an interconnect structure contacting a second surface of the crystalline silicon layer and including a wiring pattern, the second surface of the crystalline silicon layer being opposite to the first surface of the crystalline silicon layer.
However, in analogous art, Chiu teaches:
See generally Fig. 1A-1G, specifically Fig. 1G showing cross sectional view of second semiconductor structure #200 within molding layer #300 implemented into larger package structure including substrate #10 and first semiconductor element #100. See Fig. 1D for element numbers specifically drawn to second semiconductor structure #200. Chiu [0032] discloses the second semiconductor element #200 may have active elements and passive elements, i.e. semiconductor layers and dielectric layers. See also annotated Fig. 1F below.
further comprising an interconnect structure (see annotated Fig. 1F below) contacting a second surface (bottom surface) of the second semiconductor element (#200) and including a wiring pattern (see annotated Fig. 1F below), the second surface (bottom surface) of the second semiconductor element (#200)being opposite to the first surface (top surface) of the second semiconductor element (#200).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider implementing the semiconductor layer stack disclosed by Gao in view of Criado into a semiconductor device like the one disclosed by Chiu. Gao states in the abstract the objective of the layer stack is to solve problems of serious spontaneous heating of an existing SOI device, severe warpage of an existing SOI structure caused by high-temperature annealing, a poor radio frequency characteristic and the like, and paragraph [0006] states the layer structure may be used in a semiconductor product. Gao is silent on the constructional details of the larger semiconductor product the layer structure may be implemented into. In analogous art, Chiu teaches constructional details of a semiconductor device, specifically second semiconductor element #200 comprising stacked semiconductor (memory chips) in Chiu Fig. 1F, implemented into a larger package structure with an identical goal of preventing/relieving warpage of the semiconductor structure by using molding layer #300, see [0038], Doing so would be a substitution of individual semiconductor elements #204 (stacked memory chips) shown in Chiu Fig. 1D for the semiconductor layer structure disclosed by Gao in view of Criado, both of which comprise active elements (semiconductor layers) and passive elements (dielectric layers). Therefore, a person of ordinary skill would be motivated to seek the teachings of Chiu to use the semiconductor layer structure disclosed by Gao in view of Criado.
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Chiu Fig. 1F – Annotated by Examiner
Regarding Claim 8, Gao in view of Criado and further in view of Chiu discloses: The semiconductor device of claim 7,
Chiu further teaches:
further comprising a through electrode (see annotated Fig. 1F above) passing through the crystalline silicon layer (Gao #1), the amorphous silicon layer (Gao #3), and the dielectric layer (Gao #4), and electrically connected to the wiring pattern (see annotated Fig. 1F above).
Regarding Claim 9, Gao discloses:
A semiconductor device (see generally Fig. 1 and descriptive paragraphs [0008]-[0017]) comprising:
a crystalline silicon layer (#1, Fig. 1, [0008], [0030]);
an amorphous silicon layer (#3, Fig. 1, [0008]: “the thin film layer(s) 3 is/are arranged on the device substrate 1 or/and the supporting substrate 2, and is/are one of a silicon dioxide layer, a silicon oxynitride layer, a silicon nitride layer, a polysilicon layer and an amorphous silicon layer.” emphasis added) on the crystalline silicon layer (#1) and extending along a first surface of the crystalline silicon layer (#1); and
a dielectric layer (#4, Fig. 1, [0008]) on the amorphous silicon layer (#3) and extending along a surface of the amorphous silicon layer (#3),
wherein the dielectric layer (#4) includes silicon oxynitride (Fig. 1, [0008])
Gao does not explicitly disclose:
wherein the dielectric has compressive stress.
However, in analogous art, Criado teaches:
wherein the silicon oxynitride dielectric has compressive stress (abstract discloses “studies on the residual stress and structure of silicon oxynitride films deposited by PECVD with nitrogen atomic percent varying from 24 to 55.”).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider utilizing the PECVD deposition of a silicon oxynitride layer, like disclosed by Criado, to form the claimed dielectric layer. Doing so would be swapping the atomic layer deposition (ALD) method of forming the layer disclosed by Gao (see [0035]) for the PECVD method wherein the layer would subsequently have the claimed property of having compressive stress, see Criado abstract and results. Doing so would be a simple substitution of one known method known in the art of forming a dielectric layer for another to achieve a predictable result.
Gao in view of Criado does not explicitly disclose:
A semiconductor package comprising a plurality of semiconductor devices stacked in a vertical direction.
However, in analogous art, Chiu teaches:
See generally Fig. 1A-1G, specifically Fig. 1G showing cross sectional view of second semiconductor structure #200 within molding layer #300 implemented into larger package structure including substrate #10 and first semiconductor element #100. See Fig. 1D for element numbers specifically drawn to second semiconductor structure #200. See also annotated Fig. 1F above.
A semiconductor package comprising a plurality of semiconductor devices (#204, Fig. 1D, see also annotated Fig. 1F above) stacked in a vertical direction.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider implementing the semiconductor layer stack disclosed by Gao in view of Criado into a semiconductor device like the one disclosed by Chiu. Gao states in the abstract the objective of the layer stack is to solve problems of serious spontaneous heating of an existing SOI device, severe warpage of an existing SOI structure caused by high-temperature annealing, a poor radio frequency characteristic and the like, and paragraph [0006] states the layer structure may be used in a semiconductor product. Gao is silent on the constructional details of the larger semiconductor product the layer structure may be implemented into. In analogous art, Chiu teaches constructional details of a semiconductor device, specifically second semiconductor element #200 comprising stacked semiconductor (memory chips) in Chiu Fig. 1F, implemented into a larger package structure with an identical goal of preventing/relieving warpage of the semiconductor structure by using molding layer #300, see [0038], Doing so would be a substitution of individual semiconductor layers #204 (stacked memory chips) shown in Chiu Fig. 1D for the semiconductor layer structure disclosed by Gao in view of Criado. Therefore, a person of ordinary skill would be motivated to seek the teachings of Chiu to use the semiconductor layer structure disclosed by Gao in view of Criado.
Regarding Claim 10, Gao in view of Criado and further in view of Chiu discloses:
The semiconductor package of claim 9, wherein each semiconductor device (#204) of the plurality of semiconductor devices (#204) further comprises:
an interconnect structure (see annotated Fig. 1F above) contacting a second surface (bottom surface) of the crystalline silicon layer (Gao #1) and including a wiring pattern (see annotated Fig. 1F above); and
a through electrode (see annotated Fig. 1F above) passing through the crystalline silicon layer (Gao #1), the amorphous silicon layer (Gao #3), and the dielectric layer (Gao #4), and electrically connected to the wiring pattern (see annotated Fig. 1F above).
Regarding Claim 12, Gao in view of Criado and further in view of Chiu discloses: The semiconductor package of claim 9,
Chiu further teaches:
The semiconductor package of claim 9, wherein each semiconductor device (#204) of the plurality of semiconductor devices is a memory chip ([0032]).
Regarding Claim 13, Gao in view of Criado and further in view of Chiu discloses: The semiconductor package of claim 9,
Gao further teaches:
wherein a thickness of the amorphous silicon layer (#3) is between about 1 nm and about 200 nm (Gao [0015]), and wherein a thickness of the dielectric layer (#4) is between about 1 nm and about 200 nm (Gao [0015]).
Regarding Claim 14, Gao in view of Criado and further in view of Chiu discloses: The semiconductor package of claim 9,
Gao further discloses:
wherein the dielectric layer (#4) comprises at least one of:
a binary compound including a silicon element and a nitrogen element ([0035]),
a ternary compound including a silicon element, a nitrogen element, and a hydrogen element ([0035]), and
a quaternary compound including a silicon element, a nitrogen element, an oxygen element, and a hydrogen element ([0035]).
Regarding Claim 15, Gao in view of Criado and further in view of Chiu discloses:
Gao further discloses:
wherein the dielectric layer (#4) does not comprise carbon ([0035]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0237540 A1 Gao et al (herein “Gao”) in view of Study of the mechanical and structural properties of silicon oxynitride films for optical applications Criado et al and further in view of US 2023/0062468 A1 Chiu et al and further in view of US 2017/0256528 A1 Lim (herein “Lim”).
Regarding Claim 11, Gao in view of Criado and further in view of Chiu discloses: The semiconductor package of claim 9.
Gao in view of Criado and further in view of Chiu does not explicitly disclose:
wherein, among the plurality of semiconductor devices, two neighboring semiconductor devices in the vertical direction are stacked offset in a lateral direction, and wherein the plurality of semiconductor devices are electrically connected through conductive wires.
However, in analogous art, Lim teaches:
See Fig. 8 and [0052]-[0056].
wherein, among the plurality of semiconductor devices (memory dies 1-8, Fig. 8), two neighboring semiconductor devices (memory dies 1-8, Fig. 8) in the vertical direction are stacked offset in a lateral direction (see Fig. 8), and
wherein the plurality of semiconductor devices are electrically connected through conductive wires (#176, using bonding pads #170).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Lim to the device disclosed by Gao in view of Criado and further in view of Chiu and form the stack of semiconductor structures such that adjacent semiconductor structures are laterally offset from one another and connected through wires. Doing so would be a simple substitution of one known connective structure (through vias) for another (connection wire and bonding pads) to achieve the predictable result of electrically connecting vertically adjacent semiconductor layers. Doing so in the manner disclosed by Lin (laterally offset) would also have the benefit of providing a horizontal space for bonding pads to be placed in order to electrically connect them to adjacent semiconductor devices, see Lin [0052]-[0056], which would be easier to manufacture as compared to bonding the wires to a vertical surface where the semiconductor structures are not laterally offset.
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0237540 A1 Gao et al (herein “Gao”) in view of Study of the mechanical and structural properties of silicon oxynitride films for optical applications Criado et al and further in view of US 9508674 B2 Pan et al (herein “Pan”).
Regarding Claim 16, Gao discloses:
A semiconductor device (see generally Fig. 1 and descriptive paragraphs [0008]-[0017]) comprising:
a crystalline silicon layer (#1, Fig. 1, [0008], [0030]);
an amorphous silicon layer (#3, Fig. 1, [0008]: “the thin film layer(s) 3 is/are arranged on the device substrate 1 or/and the supporting substrate 2, and is/are one of a silicon dioxide layer, a silicon oxynitride layer, a silicon nitride layer, a polysilicon layer and an amorphous silicon layer.” emphasis added) on the crystalline silicon layer (#1) and extending along a first surface of the crystalline silicon layer (#1); and
a dielectric layer (#4, Fig. 1, [0008]) on the amorphous silicon layer (#3) and extending along a surface of the amorphous silicon layer (#3),
wherein the dielectric layer (#4) includes silicon oxynitride (Fig. 1, [0008])
Gao does not explicitly disclose:
wherein the dielectric has compressive stress.
However, in analogous art, Criado teaches:
wherein the silicon oxynitride dielectric has compressive stress (abstract discloses “studies on the residual stress and structure of silicon oxynitride films deposited by PECVD with nitrogen atomic percent varying from 24 to 55.”).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider utilizing the PECVD deposition of a silicon oxynitride layer, like disclosed by Criado, to form the claimed dielectric layer. Doing so would be swapping the atomic layer deposition (ALD) method of forming the layer disclosed by Gao (see [0035]) for the PECVD method wherein the layer would subsequently have the claimed property of having compressive stress, see Criado abstract and results. Doing so would be a simple substitution of one known method known in the art of forming a dielectric layer for another to achieve a predictable result.
Gao in view of Criado does not explicitly disclose:
A semiconductor package comprising:
a first redistribution structure including a first redistribution pattern;
a semiconductor device on the first redistribution structure;
a molding layer disposed on the first redistribution structure and configured to cover the semiconductor device;
a second redistribution structure disposed on the molding layer and including a second redistribution pattern; and
a vertical connection conductor electrically connecting the first redistribution pattern to the second redistribution pattern, wherein the semiconductor device comprises:
an interconnect structure between the second surface of the semiconductor device and the first redistribution structure, wherein the interconnect structure includes a wiring pattern.
However, in analogous art, Pan teaches:
See Figs. 3A-3E showing formation of semiconductor device. See specifically Fig. 3E showing completed semiconductor device unless otherwise specified.
A semiconductor package (see Fig. 3E) comprising:
a first redistribution structure (#124) including a first redistribution pattern (#213*);
a semiconductor device (#121) on the first redistribution structure (#213*);
a molding layer (Fig. 3D, #123* and #128) disposed on the first redistribution structure (#213*) and configured to cover the semiconductor device (#121);
a second redistribution structure (#222*) disposed on the molding layer (#123* and #128) and including a second redistribution pattern (#222*); and
a vertical connection conductor (#207*) electrically connecting the first redistribution pattern (#124*) to the second redistribution pattern (#222*),
an interconnect structure (Fig. 3D, #127) between the second surface of the semiconductor device (#121) and the first redistribution structure (#124*), wherein the interconnect structure includes a wiring pattern (Fig. 3D, #127).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider implementing the semiconductor layer stack disclosed by Gao in view of Criado into a semiconductor device like the one disclosed by Pan. Gao states in the abstract the objective of the layer stack is to solve problems of serious spontaneous heating of an existing SOI device, severe warpage of an existing SOI structure caused by high-temperature annealing, a poor radio frequency characteristic and the like, and paragraph [0006] states the layer structure may be used in a semiconductor product. Gao is silent on the constructional details of the larger semiconductor product the layer structure may be implemented into. In analogous art, Pan teaches constructional details of a semiconductor device, specifically semiconductor element #121, implemented into a larger package structure with an identical goal of preventing/relieving warpage (Pan refers to this characteristic as “bowing”) of the semiconductor structure by using molding layers #123* and #128, and additionally dielectric layer #208* see (14) and (15), Doing so would be a substitution of individual semiconductor layer (device) #121 shown in Pan Fig. 3E for the semiconductor layer structure disclosed by Gao in view of Criado. Therefore, a person of ordinary skill would be motivated to seek the teachings of Pan to use the semiconductor layer structure disclosed by Gao in view of Criado.
Regarding Claim 17, Gao in view of Criado and further in view of Pan discloses: The semiconductor package of claim 16,
Gao further teaches:
wherein a thickness of the amorphous silicon layer (#3) is between about 1 nm and about 200 nm (Gao [0015]), and wherein a thickness of the dielectric layer (#4) is between about 1 nm and about 200 nm (Gao [0015]).
Regarding Claim 18, Gao in view of Criado and further in view of Pan discloses: The semiconductor package of claim 16,
Gao further teaches:
wherein the dielectric layer (#4) comprises at least one of:
a binary compound including a silicon element and a nitrogen element ([0035]),
a ternary compound including a silicon element, a nitrogen element, and a hydrogen element ([0035]), and
a quaternary compound including a silicon element, a nitrogen element, an oxygen element, and a hydrogen element ([0035]).
Regarding Claim 19, Gao in view of Criado and further in view of Pan discloses: The semiconductor package of claim 16,
Gao further teaches:
wherein the dielectric layer (#4) does not comprise carbon ([0035]).
Regarding Claim 20, Gao in view of Criado and further in view of Pan discloses: The semiconductor package of claim 16,
Gao further teaches:
wherein the amorphous silicon layer (#3) entirely covers the first surface of the crystalline silicon layer (#1),
wherein the dielectric layer (#4) entirely covers the amorphous silicon layer (#3), and
wherein the dielectric layer (#4) separates from the crystalline silicon layer (#1) with the amorphous silicon layer (#3) disposed between the dielectric layer (#4) and the crystalline silicon layer (#1).
Claims 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0237540 A1 Gao et al (herein “Gao”).
Regarding Claim 24, Gao discloses:
The method of claim 22, wherein the forming of the dielectric layer () comprises forming a second plasma from an oxygen source gas including an oxygen element and a nitrogen source gas including a nitrogen element, and wherein the dielectric layer is generated through a second plasma treatment process in which a portion of the amorphous silicon layer reacts with the second plasma.
Gao does not explicitly disclose the process of forming a second layer, in this case the dielectric layer, using explicitly a second source gas and using a second plasma reaction step, i.e. PECVD. However, paragraph [0054] states “The structure formed by the method of the present invention is diverse and can meet design requirements of different devices.” and paragraph [0108] states “a silicon oxynitride layer, a silicon nitride layer, a silicon dioxide layer, a polysilicon layer or an amorphous silicon layer which is formed on the silicon wafer by using a method such as LPCVD/PECVD is combined with a silicon wafer, a silicon dioxide wafer, a silicon oxynitride wafer, a silicon nitride wafer, a polycrystalline silicon wafer, or an amorphous silicon wafer to form a multilayer SOI structure” emphasis added. Additionally, paragraph [0033] states “wherein according to different materials of the thin film layers 3, gases used in deposition are oxygen, hydrogen, nitrogen, silane, nitrous oxide, hydrogen and argon with flow rates of 0-20 slm, 0-10 slm, 0-1 slm, 0-25 sccm, 0-20 sccm, 0-50 sccm and 0-60 sccm respectively”
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider forming a multilayer SOI structure, specifically including a step forming the dielectric layer using oxygen and nitrogen as precursor gases and reacting with plasma, by using a PECVD process as described to meet the specific needs of the device. Gao describes forming various layers through PECVD process, for example, the silicon oxynitride layer, by using a wafer, for example an amorphous silicon wafer. Doing so would be a duplication of steps to meet the specific needs of the claimed device. See MPEP 2144.
Regarding Claim 25, Gao discloses:
The method of claim 24, wherein the first plasma treatment process for forming the amorphous silicon layer (#3) and the second plasma treatment process for forming the dielectric layer are performed in a same chamber ([0031]: “…the device substrate 1 and/or the supporting substrate 2 to be grown with a thin film layer 3 are/is placed into a reaction chamber of a PECVD or LPCVD apparatus”).
Conclusion
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/ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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