DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-11 and 20 in the reply filed on 3/6/2026 is acknowledged.
Invention II, claims 12-19 are withdrawn.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 4/29/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 10-11, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al. (US 2015/0031180; hereinafter ‘Cho’).
Regarding claim 1, Cho teaches a semiconductor device (FIGS. 1A-1C, [0037]), comprising:
a semiconductor pillar array (the array of pillars 26, [0038]; hereinafter ‘26A’) comprising a plurality of semiconductor pillars (26) arranged in an array (26A) along a first direction (Y direction, FIG. 1C, [0039]; hereinafter ‘Y’) and a second direction (X direction, FIG. 1C; hereinafter ‘X’) and extending in a third direction (vertical direction Z, FIG. 1A; hereinafter ‘Z’), wherein the first direction (Y), the second direction (X) and the third direction (Z) intersect with each other (FIGS. 1A-1C);
a gate strip (29, [0038]) and a shielding strip (30, [0038]) disposed between adjacent ones of the semiconductor pillars (26) along the second direction (X; FIG. 1C), wherein the gate strip (29) and the shielding strip (30) extend along the first direction (Y; FIGS. 1A-1C) and are spaced apart in the second direction (X; FIG. 1C); and
a barrier strip (34, [0042]) extending along the first direction (Y; FIGS. 1A-1C), wherein the barrier strip (34) is connected with an end of the shielding strip (30) in the third direction (Z; FIG. 1A), and is located on a same side of the shielding strip (30) and the gate strip (29) in the third direction (Z; FIG. 1A, 34 is positioned on the same upper side of 30 and 29 in the Z direction).
Regarding claim 4, Cho teaches the semiconductor device of claim 1, comprising:
a plurality of gate strips (29, FIG. 1A, [0038]) arranged as being spaced apart between rows of the semiconductor pillars along the second direction (29 disposed between adjacent 26 in the X direction);
a plurality of shielding strips (30, [0038]) arranged as being spaced apart between the rows of the semiconductor pillars along the second direction (30 disposed between adjacent 6 in the X direction) and arranged as being staggered and spaced apart with the plurality of gate strips (30 arranged alternately with 29);
a plurality of barrier strips (34, [0042]) arranged as being spaced apart between the rows of the semiconductor pillars along the second direction (34 disposed between adjacent 26 in the X direction); and
a plurality of gate conductive connection structures (36, [0042]) arranged as being spaced apart between the rows of the semiconductor pillars along the second direction (36 disposed between adjacent 26 in the X direction).
Regarding claim 10, Cho teaches the semiconductor device of claim 1, further comprising:
a first oxide layer (28 includes a silicon oxide, FIG. 1A, [0040]) between the semiconductor pillar (26) and the gate strip (29) and between the semiconductor pillar (11) and the shielding strip (30); and
an isolation structure (31, [0042]) between the gate strip (29) and the shielding strip (30).
Regarding claim 11, Cho teaches the semiconductor device of claim 1, further comprising: a capacitor array (108, FIG. 2, [0046]) at an end of the semiconductor pillar array (108 disposed on top portions of 103 corresponding to 26 of FIG. 1A) in the third direction (Z),
wherein the capacitor array comprises a plurality of capacitor structures arranged in an array along the first direction and the second direction and extending in the third direction (108 formed on the pillars 103 in a one-to-one correspondence with 103, such that 108 is arranged in both the X and Y direction and extend vertically in the Z direction), and the capacitor structures comprise a first electrode layer (41, FIG. 5C, [0069]) connected with an end of the semiconductor pillar (26) in the third direction (Z), and a capacitor dielectric layer (a dielectric layer for 41, [0070]) and a second electrode layer (plate node, [0070]) within the first electrode layer (the dielectric layer and the plate nodes formed over and surrounding 41 to form 108).
Regarding claim 20, Cho teaches a memory system (FIG. 2, [0046]), comprising:
a semiconductor device (FIGS. 1A-1C, [0037]) comprising:
a semiconductor pillar array (the array of pillars 26, [0038]; hereinafter ‘26A’) comprising a plurality of semiconductor pillars (26) arranged in an array (26A) along a first direction (Y direction, FIG. 1C, [0039]; hereinafter ‘Y’) and a second direction (X direction, FIG. 1C; hereinafter ‘X’) and extending in a third direction (vertical direction Z, FIG. 1A; hereinafter ‘Z’), wherein the first direction (Y), the second direction (X) and the third direction (Z) intersect with each other (FIGS. 1A-1C);
a gate strip (29, [0038]) and a shielding strip (30, [0038]) disposed between adjacent ones of the semiconductor pillars (26) along the second direction (X; FIG. 1C), wherein the gate strip (29) and the shielding strip (30) extend along the first direction (Y; FIGS. 1A-1C) and are spaced apart in the second direction (X; FIG. 1C); and
a barrier strip (34, [0042]) extending along the first direction (Y; FIGS. 1A-1C), wherein the barrier strip (34) is connected with an end of the shielding strip (30) in the third direction (Z; FIG. 1A), and is located on the same side of the shielding strip (30) and the gate strip (29) in the third direction (Z; FIG. 1A); and
a controller (a memory controller, [0179]) coupled with the semiconductor device (a memory including the semiconductor device), wherein the controller is configured to control the semiconductor device to perform data write and read operations (the memory controller configured to control memories to read and write data).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Cho (US 2015/0031180) in view of Kim et al. (US 2018/0102314; hereinafter ‘Kim’).
Regarding claim 2, Cho teaches the semiconductor device of claim 1, further comprising:
a gate conductive connection structure (36, FIG. 1A, [0042]), wherein the gate conductive connection structure (36) extends along the first direction (Y), and is located between an end of the gate strip (29) in the third direction (Z) and the barrier strip (34), and is at least partially in juxtaposition to the barrier strip (34); and
a gate lead-out contact (40, FIG. 5B, [0068]) at an end of the semiconductor pillar array (26) in the third direction (Z).
Cho does not teach the semiconductor device wherein the gate lead-out contact is connected with the gate conductive connection structure.
Kim teaches a semiconductor device (FIG. 1A, [0018]) wherein the gate lead-out contact is connected with the gate conductive connection structure (LL is connected with GCT, [0030]).
As taught by Kim, one of ordinary skill in the art would utilize and modify the above teaching into Cho to obtain and achieve the semiconductor device wherein the gate lead-out contact is connected with the gate conductive connection structure as claimed, because it provides a separate vertical conductive path and together with the connection structure, forms a multi-stage connection for facilitating signal extraction and routing [0029, 0030].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kim in combination with Cho due to above reason.
Regarding claim 5, Cho teaches the semiconductor device of claim 4, further comprising: a plurality of gate lead-out contacts (40, FIG. 5B, [0068]), wherein one of the gate lead-out contacts corresponds to one of the gate conductive connection structures (40 is associated with a respective 36).
Cho does not teach the semiconductor device wherein the plurality of gate lead-out contacts are synchronously arranged as being spaced apart along the first direction and the second direction in a staircase distribution.
Kim teaches a semiconductor device (FIG. 1A, [0018]) wherein the plurality of gate lead-out contacts are synchronously arranged as being spaced apart along the first direction and the second direction in a staircase distribution (GCT disposed at end portions of conductive patterns arranged in a stepped structure, such that GCT are arranged in a staircase distribution, [0059]).
As taught by Kim, one of ordinary skill in the art would utilize and modify the above teaching into Cho to obtain and achieve the semiconductor device wherein the plurality of gate lead-out contacts are synchronously arranged as being spaced apart along the first direction and the second direction in a staircase distribution as claimed, because the arrangement provides separate across points along the stepped structure and facilitates signal extraction and routing [0030, 0059].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kim in combination with Cho due to above reason.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Cho (US 2015/0031180) in view of Kim (US 2018/0102314), and further in view of Dunn et al. (US 2011/0018059; hereinafter ‘Dunn’).
Regarding claim 3, Cho in view of Kim teaches the semiconductor device of claim 2, but does not teach the semiconductor device further comprising: a shielding lead-out contact at the end of the semiconductor pillar array in the third direction, wherein the shielding lead-out contact is connected with the shielding strip.
Dunn teaches a semiconductor device (100, FIG. 3, [0033]) further comprising: a shielding lead-out contact (interconnect layer 328 contacting the shield electrode 320, thereby forming a shielding lead-out contact; hereinafter ‘328S’), at the end of the semiconductor pillar array (disposed in a shield contact region 106 adjacent to and outside an active region 102, the active region 102 corresponding to the semiconductor pillar array) in the third direction (a direction corresponding to a depth direction of the trenches 210), wherein the shielding lead-out contact (328S) is connected with the shielding strip (320).
As taught by Dunn, one of ordinary skill in the art would utilize and modify the above teaching into Cho in view of Kim to obtain and achieve the semiconductor device further comprising: a shielding lead-out contact at the end of the semiconductor pillar array in the third direction, wherein the shielding lead-out contact is connected with the shielding strip as claimed, because providing direct contact to the shield electrode via an interconnect layer reduces shield resistance and shortens the contact distance [0002, 0004].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Dunn in combination with Cho in view of Kim due to above reason.
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Cho (US 2015/0031180) in view of Dunn (US 2011/0018059) and Tanzawa (US 2020/0357813).
Regarding claim 6, Cho teaches the semiconductor device of claim 4, but does not teach the semiconductor device further comprising: a plurality of shielding lead-out contacts, wherein one of the shielding lead-out contacts corresponds to one of the shielding strips, and the plurality of shielding lead-out contacts are synchronously arranged as being spaced apart along the first direction and the second direction in a staircase distribution.
Tanzawa teaches a semiconductor device (100, FIG. 6A, [0052]) further comprising: a plurality of lead-out contacts (130), wherein one of the lead-out contacts corresponds to one of the strips (each of 130 corresponds to a respective conductive pattern 128), and the plurality of lead-out contacts are synchronously arranged as being spaced apart along the first direction and the second direction in a staircase distribution (130 disposed at end portions of conductive patterns arranged in a stepped structure, such that 130 are arranged in a staircase distribution).
As taught by Tanzawa, one of ordinary skill in the art would utilize and modify the above teaching into Cho to obtain and achieve the semiconductor device further comprising: a plurality of lead-out contacts, wherein one of the lead-out contacts corresponds to one of the strips, and the plurality of lead-out contacts are synchronously arranged as being spaced apart along the first direction and the second direction in a staircase distribution as claimed, because contacts formed on steps of a staircase structure are positioned at different location corresponding to the steps, thereby inherently providing offset contact positions that facilitate routing of connections and maintain spacing between adjacent interconnects [0052, 0057].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Tanzawa in combination with Cho due to above reason.
Cho in view of Tanzawa does not teach that the lead-out contacts are configured as shielding lead-out contacts corresponding to respective shielding strips.
Dunn teaches a semiconductor device (100, FIG. 3, [0033]) comprising: a shielding lead-out contact (interconnect layer 328 contacting the shield electrode 320, thereby forming a shielding lead-out contact; hereinafter ‘328S’), wherein the shielding lead-out contacts corresponds to a shielding strip (320).
As taught by Dunn, one of ordinary skill in the art would utilize and modify the above teaching into Cho in view of Tanzawa to obtain and achieve the semiconductor device including a plurality of shielding lead-out contacts corresponding to respective shielding strips as claimed, because shielding lead-out contact configuration provides electrical connection to shielding electrodes, reduces resistance, and improves device performance [0002, 0004].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Dunn in combination with Cho in view of Tanzawa due to above reason.
Regarding claim 7, Cho teaches the semiconductor device of claim 4, further comprising a plurality of gate lead-out contacts (40, FIG. 5B, [0068]), wherein one of the gate lead-out contacts corresponds to one of the gate conductive connection structures (40 is associated with a respective 36).
Cho does not teach a plurality of shielding lead-out contacts, wherein one of the shielding lead-out contacts corresponds to one of the shielding strips, nor does it teach that the plurality of gate lead-out contacts and the plurality of shielding lead-out contacts are synchronously arranged as being staggered and spaced apart along the first direction and the second direction in a staircase distribution.
Tanzawa teaches a semiconductor device (100, FIG. 6A, [0052]) further comprising a plurality of lead-out contacts (130), wherein one of the lead-out contacts corresponds to one of the strips (each of 130 corresponds to a respective conductive pattern 128), and the plurality of lead-out contacts are synchronously arranged as being staggered (130 formed on different step locations of one or more additional staircase structures 126a and/or 126b, such that the contacts are positioned at different locations and offset from one another along the first and second directions) and spaced apart along the first direction and the second direction (130 disposed at end portions of conductive patterns arranged in a stepped structure).
As taught by Tanzawa, one of ordinary skill in the art would utilize and modify the above teaching into Cho to obtain and achieve the semiconductor device further comprising a plurality of lead-out contact, wherein one of the lead-out contacts corresponds to one of the strips, and the plurality of lead-out contacts are synchronously arranged as being staggered and spaced apart along the first direction and the second direction in a staircase distribution as claimed, because contacts formed at different step locations of staircase structures are positioned at different spatial locations, thereby facilitating routing and maintaining spacing between adjacent interconnects [0052, 0057].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Tanzawa in combination with Cho due to above reason.
Cho in view of Tanzawa does not teach that the lead-out contacts are configured as shielding lead-out contacts corresponding to respective shielding strips, nor does it teach that both the gate lead-out contact and the shielding lead-out contact are provided together.
Dunn teaches a semiconductor device (100, FIG. 3, [0033]) comprising: a shielding lead-out contact (interconnect layer 328 contacting the shield electrode 320, thereby forming a shielding lead-out contact; hereinafter ‘328S’), wherein the shielding lead-out contacts corresponds to a shielding strip (320), and both a gate lead-out contact (interconnect layer 328 contacting the gate electrode 324, thereby forming a gate lead-out contact, [0034]) and the shielding lead-out contact (328S) are arranged together (shown in FIG. 3).
As taught by Dunn, one of ordinary skill in the art would utilize and modify the above teaching into Cho in view of Tanzawa to obtain and achieve the semiconductor device including a plurality of shielding lead-out contacts corresponding to respective shielding strips, and both the gate lead-out contact and the shielding lead-out contact are provided together as claimed, because shielding lead-out contact configuration provides electrical connection to shielding electrodes, reduces resistance, and improves device performance [0002, 0004], and electrical contacts are required to provide electrical connection to conductive electrodes, including both shielding electrodes and gate electrodes.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Dunn in combination with Cho in view of Tanzawa due to above reason.
Regarding claim 8, Cho teaches the semiconductor device of claim 4, further comprising a plurality of gate lead-out contacts (40, FIG. 5B, [0068]), wherein one of the gate lead-out contacts corresponds to one of the gate conductive connection structures (40 is associated with a respective 36).
Cho does not teach a plurality of shielding lead-out contacts, wherein one of the shielding lead-out contacts corresponds to one of the shielding strips, nor does it teach that the plurality of gate lead-out contacts and the plurality of shielding lead-out contacts are arranged as being staggered and spaced apart along the second direction.
Tanzawa teaches a semiconductor device (100, FIG. 6A, [0052]) further comprising a plurality of lead-out contacts (130), wherein one of the lead-out contacts corresponds to one of the strips (each of 130 corresponds to a respective conductive pattern 128), and the plurality of lead-out contacts are arranged as being staggered and spaced apart along the second direction (130 disposed at end portions of conductive patterns arranged in a stepped structure, [0052]).
As taught by Tanzawa, one of ordinary skill in the art would utilize and modify the above teaching into Cho to obtain and achieve the semiconductor device further comprising a plurality of lead-out contacts, wherein one of the lead-out contacts corresponds to one of the strips, and the plurality of lead-out contacts are arranged as being staggered and spaced apart along the second direction as claimed, because contacts formed on steps of a staircase structure are positioned at different location corresponding to the steps, thereby inherently providing offset contact positions that facilitate routing of connections and maintain spacing between adjacent interconnects [0052, 0057].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Tanzawa in combination with Cho due to above reason.
Cho in view of Tanzawa does not teach that the lead-out contacts are configured as shielding lead-out contacts corresponding to respective shielding strips, nor does it teach that both the gate lead-out contact and the shielding lead-out contact are provided together.
Dunn teaches a semiconductor device (100, FIG. 3, [0033]) comprising: a shielding lead-out contact (interconnect layer 328 contacting the shield electrode 320, thereby forming a shielding lead-out contact; hereinafter ‘328S’), wherein the shielding lead-out contacts corresponds to a shielding strip (320), and both a gate lead-out contact (interconnect layer 328 contacting the gate electrode 324, thereby forming a gate lead-out contact, [0034]) and the shielding lead-out contact (328S) are arranged together (shown in FIG. 3).
As taught by Dunn, one of ordinary skill in the art would utilize and modify the above teaching into Cho in view of Tanzawa to obtain and achieve the semiconductor device including a plurality of shielding lead-out contacts corresponding to respective shielding strips, and both the gate lead-out contact and the shielding lead-out contact are provided together as claimed, because shielding lead-out contact configuration provides electrical connection to shielding electrodes, reduces resistance, and improves device performance [0002, 0004], and electrical contacts are required to provide electrical connection to conductive electrodes, including both shielding electrodes and gate electrodes.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Dunn in combination with Cho in view of Tanzawa due to above reason.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Cho (US 2015/0031180) in view of Breitwisch et al. (US 2011/0275209; hereinafter ‘Breitwisch’).
Regarding claim 9, Cho teaches the semiconductor device of claim 1, but does not teach the semiconductor device wherein a cross-sectional dimension of the semiconductor pillars in the second direction is equal to a spacing dimension between two adjacent ones of the semiconductor pillars.
Breitwisch teaches a semiconductor device (FIG. 2, [0030]) wherein a cross-sectional dimension of the semiconductor pillars in the second direction is equal to a spacing dimension between two adjacent ones of the semiconductor pillars (1F corresponds to a cross-sectional dimension of semiconductor pillars via the pillar mask, and is equal to a spacing dimension between two adjacent pillar mask layers corresponding to adjacent semiconductor pillars).
As taught by Breitwisch, one of ordinary skill in the art would utilize and modify the above teaching into Cho to obtain and the semiconductor device wherein a cross-sectional dimension of the semiconductor pillars in the second direction is equal to a spacing dimension between two adjacent ones of the semiconductor pillars as claimed, because it provides improved pattern uniformity, simplify lithographic processing, and result in consistent device characteristics.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Breitwisch in combination with Cho due to above reason.
Conclusion
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 4/30/26
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