Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 12 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Gao (CN 107068618 A, from IDS) in view of Hattori (JP 2022167030 A), and Ma (CN-110649055-A).
Regarding independent claim 12, Gao discloses an apparatus (Fig. 6), comprising:
a semiconductor die (a portion of 600; pg. 4 of translation: “the semiconductor wafer 600 to the front side array distributed with several chip (not shown)”; corresponds to a portion of Fig. 7: 700) having bond pads (601) on a device side surface (See annotated Fig. 7 for surface designation),
having a backside surface (See annotated Fig. 7 for surface designation) opposite the device side surface (vertically opposite) and having four sides (See annotated Fig. 7 for surface designation) extending between the device side surface and the backside surface (extending vertically);
light blocking material (704) on the device side surface (directly on) and the four sides (directly on);
semiconductor material (Fig. 7(g) before dicing: See annotation “semiconductor material segment”) on the four sides (indirectly horizontally on), wherein the semiconductor material and the light blocking material on the four sides are not coplanar (these materials have different vertical planes and are thus “not coplanar”);
a backside coating (706 is deposited on the backside surface in the claimed sequence) on the backside surface (directly on);
openings (See annotated figure 7(g)) in the light blocking material on the device side surface, the openings exposing (fully expose) under-bump metallization material (Fig. 6: 606, corresponds to Fig. 7: 701) on the bond pads (directly on, as shown in Fig. 6); and
terminals (705) that are formed by solder bumps or conductive post connects (Fig. 7(g): solder bumps are illustrated) on the under-bump metallization material (directly on).
Illustrated below is a marked and annotated figure of Fig. 7 of Gao.
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Gao illustrates the die in a cross-sectional view and thus teaches the die including at least two sides. However, Gao fails to teach specific details regarding the top-down/perspective shape of the die. Thus, Gao fails to teach “a semiconductor die having bond pads on a device side surface,
having a backside surface opposite the device side surface and having four sides extending between the device side surface and the backside surface;
light blocking material on the device side surface and the four sides;
semiconductor material on the four sides, wherein the semiconductor material and the light blocking material on the four sides are not coplanar;”.
Hattori discloses a die (Fig. 1: 101) having four sides extending between the device side surface and the backside surface (a quadrilateral shape is shown in the figure). Modifying the semiconductor die shape of Gao by incorporating the shape of Hattori would arrive at the claimed die shape. A person of ordinary skill in the art before the effective filing date would have had predictable results doing so because in each situation the die is incorporated on a wafer (Gao: pg. 4. “the semiconductor wafer 600 to the front side array distributed with several chip (not shown)”; Hattori: Fig. 1: wafer 100 and dies 101). Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date to have the claimed die shape because it is a mere change in shape of parts, consistent with the teachings elsewhere in the prior art. MPEP 2144.04 (IV)(B).
Illustrated below is a marked and annotated figure of Fig. 1 of Hattori.
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Gao teaches material but fails to teach this material being light blocking. Thus, Gao in view of Hattori fails to teach “light blocking material on the device side surface and the four sides;
semiconductor material on the four sides, wherein the semiconductor material and the light blocking material on the four sides are not coplanar;
a backside coating on the backside surface;
openings in the light blocking material on the device side surface […]”.
Ma discloses a layer of light blocking material (Fig. 8: 800; pg. 6 of translation: “black lithographic material form the solder resist layer 800”; pg. 7: “blocking the infrared ray”) on the device side surface (See annotated figure) and the four sides (See annotated figure). Modifying the material of Gao in view of Hattori to be the light blocking material of Ma would arrive at the claimed light blocking material configuration. Doing so would have been predictable to one of ordinary skill in the art before the effective filing date because in each situation a resist material is used for exposing under-bump metallization (Gao: Fig. 7: 701; Ma: Fig. 8: 400). Ma provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have the claimed light blocking material in that it would improve patterning of the material (pg. 7: “improves the imaging effect of the chip”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed light blocking material configuration because it would improve patterning of the material. MPEP 2143 (I)(G).
Illustrated below is a marked and annotated figure of Fig. 8 of Ma.
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Regarding claim 16, Gao in view of Hattori, and Ma discloses the apparatus of claim 12 (Ma: Fig. 8), wherein the light blocking material comprises a black matrix resist (800; pg. 6 of translation: “black lithographic material form the solder resist layer 800”).
Regarding claim 17, Gao in view of Hattori, and Ma discloses the apparatus of claim 12 (Ma: Fig. 8), wherein the light blocking material comprises an infrared blocking resist (pg. 7: “blocking the infrared ray”).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Gao, Hattori, and Ma as applied to claim 12 above, and further in view of Huang (US 20230066968 A1).
Regarding claim 13, Gao in view of Hattori and Ma discloses the apparatus of claim 12, but fails to teach the claimed configuration of the terminals “wherein the terminals comprise comprise: copper pillars on the under-bump metallization material and extending away from the device side surface to a distal end; and solder on the distal end of the copper pillars”.
Huang discloses wherein the terminals (Fig. 6: 182) comprise: copper pillars ([0025]: “copper posts (or pillar)”) on the under-bump metallization material (144) and extending away from the device side surface to a distal end; and solder ([0025]: “solder caps”) on the distal end of the copper pillars ([0025]: “conductive pillars with solder caps”). Modifying the terminals of Gao, Hattori, and Ma by using the terminals disclosed by Huang would arrive at the claimed terminal configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Huang teaches these terminals may be used alternative to solder ([0025]: “the conductive bumps 182 may include placing solder balls…The conductive bumps 182 may also include conductive pillars, or conductive pillars with solder caps”), and solder is the species of terminal disclosed by Gao (Gao: Fig. 7: solder is illustrated as terminals 705). Huang provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have the claimed terminal configuration in that it would enable denser arrangements of terminals, thereby enabling advanced circuitry (Huang: [0025]: “For advanced packaging of semiconductor devices 110 with many function circuitries, the sizes of conductive bumps 182 may be relatively small to enable more bumps to connect to an input/output (I/O) of semiconductor devices 110…As a result, the conductive bumps 182 with fine pitches and sizes, such as micro-bumps, are used for external connections. Micro-bumps may include copper posts”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed terminal configuration because it would enable advanced circuity. MPEP 2143 (I)(G).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Gao, Hattori, and Ma as applied to claim 12 above, and further in view of Shinoda (US 20150024576 A1).
Regarding claim 15, Gao in view of Hattori and Ma discloses the apparatus of claim 12, wherein the layer of light blocking material (Ma: Fig. 8: 800; pg. 6 of translation: “black lithographic material form the solder resist layer 800”; pg. 7: “blocking the infrared ray”) and the backside coating block infrared light.
Gao in view of Hattori and Ma fails to teach “[…] the backside coating block infrared light”.
Shinoda discloses a backside coating ([0140]: “the semiconductor chip having the protective film at the backside”) block infrared light ([0085]: “The protective film…infrared ray…can be blocked”). Modifying the backside coating of Gao, Hattori, and Ma by including the coating of Shinoda would arrive at the claimed coating configuration. Doing so would have been predictable to one of ordinary skill in the art before the effective filing date because in each situation the backside surface includes a protective coating (Gao: Fig. 7(g): 706; Shinoda: [0139]: “the dicing sheet with the protective film forming layer of the present invention has excellent expanding property”). Shinoda provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have the claimed backside coating configuration in that it would protect the die from cracking during manufacture ([0140]: “the protective film with high uniformity of the thickness can be easily formed at the chip backside, thus the cracks caused during the dicing step or packaging becomes difficult to occur”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed coating configuration because it would protect the die during manufacture. MPEP 2143 (I)(G).
Allowable Subject Matter
Claims 1-7, 9-10, and 20-21 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claims 1-7 and 9-10 is the inclusion of the limitation “patterning the light blocking material to expose the under-bump metallization material on the bond pads and to expose the scribe lanes between the filled trenches, wherein the device side surface is not covered by the light blocking material around the scribe lanes” in combination with the other sequences and limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “patterning”, “expose”, “device side surface”, and “not covered” in combination with all other sequences and limitations required in claim 1.
The primary reason for the allowable subject matter of claims 20-21 is the inclusion of the limitation “patterning the light blocking material to expose the under-bump metallization material on the bond pads and to expose the scribe lanes between the filled trenches, wherein the device side surface is not covered by the light blocking material around the scribe lanes” in combination with the other sequences and limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “patterning”, “expose”, “device side surface”, and “not covered” in combination with all other sequences and limitations required in claim 20.
Response to Arguments
Applicant's arguments filed 6/11/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claims 1 and 20 that: “Gao does not disclose or suggest “patterning the light blocking material to expose the under-bump metallization material on the bond pads and to expose the scribe lanes between the filled trenches, wherein the device side surface is not covered by the light blocking material around the scribe lanes.””; and “Claim 20 includes similar features”. Remarks at pg. 8.
Examiner’s reply:
Applicant’s arguments, see pg. 8, filed 6/11/2026, with respect to amended claims 1 and 20 have been fully considered and are persuasive. The rejection of these claims (and dependents therefrom) under 35 U.S.C. 103 has been withdrawn.
Applicant argues:
Applicant argues with respect to amended claim 12 that “Gao does not disclose or suggest “the semiconductor material and the light blocking material on the four sides are not coplanar.””. Remarks at pg. 9.
Examiner’s reply:
The examiner does not find the arguments persuasive because the claim as written reasonably includes a plurality of surface configurations, such as Applicant’s disclosed surface configuration, as well as alternative designated surfaces and planes. Accordingly, the rejection is maintained substantially similar as before, though has been adjusted as required by the instant claim amendments and to promote clarity of the record. MPEP 2111.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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