Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/28/2023 and 7/3/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12 (and dependent claims 12-19) and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation “the semiconductor device die” in line 9. There is insufficient antecedent basis for this limitation in the claim. For the sake of compact prosecution, claim 12 is interpreted in the instant Office action as follows: “the semiconductor device die” is equivalent to “the semiconductor die” based on antecedence for this term in line 2. This interpretation is to be confirmed by applicant in the next office action.
Claim 15 recites the limitation “the backside coating of light blocking material” in line. There is insufficient antecedent basis for this limitation in the claim. For the sake of compact prosecution, claim 15 is interpreted in the instant Office action as follows: “the backside coating of light blocking material” is equivalent to “the backside coating of light blocking tape” based on antecedence for this term in claim 12. This interpretation is to be confirmed by applicant in the next office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-2, 4, 6-10, 12, 14-17, and 19-22 are rejected under 35 U.S.C. 103 as being unpatentable over Gao (CN 107068618 A, from IDS) in view of Hattori (JP 2022167030 A), Ma (CN-110649055-A), and Shinoda (US 20150024576 A1).
Regarding claim 1, Gao discloses a method for making a packaged semiconductor device (Fig. 6), comprising:
forming under-bump metallization material (606, corresponds to Fig. 7: 701) on bond pads (601) of semiconductor dies (a portion of 600; pg. 4 of translation: “the semiconductor wafer 600 to the front side array distributed with several chip (not shown)”; corresponds to a portion of Fig. 7: 700) arranged in rows and columns on a device side surface of a semiconductor wafer (See annotated Fig. 7 for surface designation),
the semiconductor dies spaced from one another by scribe lanes (Fig. 7: See annotated figure),
the semiconductor wafer having a backside surface opposite the device side surface (See annotated Fig. 7 for surface designations);
forming trenches (702) extending from the device side surface into but not through the semiconductor wafer (702 does not fully extent through the dies of wafer 700) along sides of the semiconductor dies (See annotated Fig. 7 for surface designations), the trenches adjacent the scribe lanes (horizontally adjacent);
depositing light blocking material (704) over the device side surface (directly over),
the light blocking material filling the trenches (completely filling) to form filled trenches (trenches 702 filled with material 704) and forming a layer of the light blocking material (Fig. 7(b): the intermediate thickness of 704 in the method step of) covering the device side surface of the semiconductor wafer (directly covering);
patterning the layer of light blocking material (Fig. 7(c)) to expose (fully expose) the under-bump metallization material over the bond pads of the semiconductor dies (701 is fully exposed) and to expose (indirectly expose) the scribe lanes between the filled trenches (indirectly exposed because material 704 thickness is uniformly reduced including over the scribe lines);
forming solder bumps (705) on the under-bump metallization material (directly on);
backgrinding the backside surface (Fig. 7(e)) to thin the semiconductor wafer and to expose (fully expose) the light blocking material in the filled trenches (Fig. 7(e) fully exposes material 704 at the backside surface);
depositing a light blocking backside coating tape on the backside surface (706 is deposited on the backside surface in the claimed sequence, but is not the claimed tape);
dicing the semiconductor wafer along the scribe lanes (Fig. 7(g)) using either laser dicing or plasma dicing,
the dicing leaving semiconductor material edges on the sides of the semiconductor dies (See annotated Fig. 7(g) showing the semiconductor material. This material is indirectly on the fully exposed sides of the dies); and
expanding the semiconductor wafer along the scribe lanes to separate the semiconductor dies from one another to form packaged semiconductor dies.
Illustrated below is a marked and annotated figure of Fig. 7 of Gao.
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Gao fails to explicitly teach “dicing the semiconductor wafer along the scribe lanes using either laser dicing or plasma dicing”. However, Gao teaches cutting a wafer may include either laser cutting or plasma cutting (pg. 4: “laser, plasma, or blade cutting method in wafer 700 dicing groove 702 is formed”). Modifying the dicing method by using either laser dicing or plasma dicing would have been predictable to one of ordinary skill in the art before the effective filing date because in each situation the wafer is cut to at least some extent (the trenches 702 and the scribe lanes each cut a portion of the wafer 700), and Gao teaches these cutting techniques are comparable to the exemplary dicing technique (dicing technique: pg. 5: “blade 710”; cutting techniques: pg. 4: “laser, plasma, or blade cutting method in wafer”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed dicing method because it is using a technique disclosed elsewhere in the prior art with a similar structure in a similar way. MPEP 2143 (I)(C).
Gao fails to teach the method including “semiconductor dies arranged in rows and columns,” and “expanding the semiconductor wafer along the scribe lanes to separate the semiconductor dies from one another to form packaged semiconductor dies”.
Hattori discloses a method with dies (Fig. 1: 101) arranged in rows and columns (See annotated figure). Modifying the semiconductor die arrangement in the method of Gao by duplicating the dies in the same way as Hattori would arrive at the claimed arrangement in the method. A person of ordinary skill in the art before the effective filing date would have had predictable results doing so because in each situation the method includes a plurality of dies on a wafer (Gao: pg. 4. “the semiconductor wafer 600 to the front side array distributed with several chip (not shown)”; Hattori: Fig. 1: wafer 100 and dies 101). Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date to have the claimed die arrangement method because it is a mere duplication of parts consistent with the teachings elsewhere in the prior art. MPEP 2144.04 (VI)(B).
Hattori additionally discloses expanding the semiconductor wafer along the scribe lanes (103) to separate the semiconductor dies from one another to form packaged semiconductor dies (pg. 2: “the expand sheet 113 of the workset 110 is expanded to form a predetermined spacing between the chips 120 of the wafer 100”). Modifying the method of Gao by including the “expanding” method step of Hattori would arrive at the claimed expanding method configuration. Hattori provides a teaching to motivate one to include the expanding method configuration in that it would enable a reduction in damage during subsequent manufacturing steps (pg. 5: “damage due to contact between the chips 120 can be suppressed”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed expanding method configuration because it would enable a reduction in damage during manufacture. MPEP 2143 (I)(G).
Illustrated below is a marked and annotated figure of Fig. 1 of Hattori.
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Gao teaches depositing material but fails to teach this material being light blocking. Thus, Gao in view of Hattori fails to teach “depositing light blocking material over the device side surface, the light blocking material filling the trenches to form filled trenches and forming a layer of the light blocking material covering the device side surface of the semiconductor wafer;
patterning the layer of light blocking material to expose the under-bump metallization material over the bond pads of the semiconductor dies and to expose the scribe lanes between the filled trenches;
forming solder bumps on the under-bump metallization material;
backgrinding the backside surface to thin the semiconductor wafer and to expose the light blocking material in the filled trenches;”.
Ma discloses a method (Fig. 8) depositing light blocking material (800; pg. 6 of translation: “black lithographic material form the solder resist layer 800”; pg. 7: “blocking the infrared ray”) over the device side surface (See annotated figure). Modifying the method of Gao in view of Hattori by depositing this light blocking material as the material would arrive at the claimed method and light blocking material configuration. Doing so would have been predictable to one of ordinary skill in the art before the effective filing date because in each situation a resist material is used for exposing under-bump metallization (Gao: Fig. 7: 701; Ma: Fig. 8: 400). Ma provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have the claimed light blocking material and method configuration in that it would improve patterning of the material (pg. 7: “improves the imaging effect of the chip”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the method include the light blocking material configuration because it would improve patterning of the material. MPEP 2143 (I)(G).
Illustrated below is a marked and annotated figure of Fig. 8 of Ma.
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Gao in view of Hattori and Ma fails to teach “depositing a light blocking backside coating tape on the backside surface;”.
Shinoda discloses depositing a light blocking ([0085]: “The protective film…infrared ray…can be blocked”) backside coating tape ([0140]: “The dicing sheet with the protective film”) on the backside surface ([0140]: “the semiconductor chip having the protective film at the backside”). Modifying the method of Gao, Hattori, and Ma by including the tape of Shinoda would arrive at the claimed method. Doing so would have been predictable to one of ordinary skill in the art before the effective filing date because in each situation the backside surface is deposited on expanding tape (Hattori: Fig. 1: 113; Shinoda: [0139]: “the dicing sheet with the protective film forming layer of the present invention has excellent expanding property”). Shinoda provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have the claimed light blocking backside coating tape in that it would protect the die from cracking during manufacture ([0140]: “the protective film with high uniformity of the thickness can be easily formed at the chip backside, thus the cracks caused during the dicing step or packaging becomes difficult to occur”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the method include the claimed tape configuration because it would protect the die during manufacture. MPEP 2143 (I)(G).
Regarding claim 2, Gao in view of Hattori, Ma, and Shinoda discloses the method of claim 1 (Gao: Fig. 7), wherein after expanding the semiconductor wafer along the scribe lanes to separate the semiconductor dies from one another to form packaged semiconductor dies, the light blocking material covers the device side surface (704 is retained at method step Fig. 7(g). This method step corresponds to the method step where the expanding of Hattori is performed. Hattori makes no requirement for removal of light blocking materials or their analogues, i.e., solder resist. Thus, this material is retained in the same way shown by Gao.) and four sides (Gao: Fig. 7(g) shows material 704 is on the sides of the die but only shows a cross-sectional view. Hattori: Fig. 1 was relied upon in the claim 1 rejection to teach die arrangement. This die arrangement produces 4 sides of the die. Therefore, the material 704 of Gao is retained in the same way on these 4 sides of the die.) that extend perpendicularly from the device side surface to the backside surface of the packaged semiconductor dies (perpendicular is shown), and the backside surface is covered with the light blocking backside coating tape (directly covered), so that all external surfaces of the packaged semiconductor dies are covered with light blocking material (Fig. 7(g) shows all surfaces are covered).
Regarding claim 4, Gao in view of Hattori, Ma, and Shinoda discloses the method of claim 1 (Gao: Fig. 7(g)), wherein dicing the semiconductor wafer along the scribe lanes using either laser dicing or plasma dicing further comprises performing a plasma dicing process (selecting “plasma” as the dicing technique of Gao: pg. 5: “blade 710”; cutting techniques: pg. 4: “laser, plasma, or blade cutting method in wafer”) in the scribe lanes of the semiconductor wafer to etch through the semiconductor wafer (wafer 700 is fully etched through) in the scribe lanes to expose the light blocking backside coating tape (The wafer is fully etched through as shown in Gao: Fig. 7(g). Shinoda teaches the tape is still existing after the dies are cut; [0140]: “picking up the diced semiconductor chip with the protective film”, thus it is retained in the same way for the corresponding dicing step of Gao. Therefore, the tape is exposed in at least some direction.).
Regarding claim 6, Gao in view of Hattori, Ma, and Shinoda discloses the method of claim 1, wherein depositing a light blocking backside coating tape on the backside surface further comprises: attaching a first side of the light blocking backside coating tape to the backside surface of the wafer (Shinoda: [0092]: “the protective film forming layer against the chip”); and thermally curing the light blocking backside coating tape (Shinoda: [0066]: “heat curing resin”).
Regarding claim 7, Gao in view of Hattori, Ma, and Shinoda discloses the method of claim 1, wherein depositing a light blocking backside coating tape on the backside surface further comprises depositing a backside coating tape that blocks infrared light (Shinoda: [0085]: “The protective film…infrared ray…can be blocked”).
Regarding claim 8, Gao in view of Hattori, Ma, and Shinoda discloses the method of claim 7, wherein depositing a backside coating tape that blocks infrared light further comprises depositing ADWILL LC backside coating tape from LINTEC OF AMERICA, INC (Shinoda: [0153]: “LC2850” or [0154]: “LC2822”).
Regarding claim 9, Gao in view of Hattori, Ma, and Shinoda discloses the method of claim 1 (Ma: Fig. 8), wherein depositing light blocking material over the device side surface of the semiconductor wafer further comprises depositing a material that blocks infrared light (800; pg. 7: “blocking the infrared ray”).
Regarding claim 10, Gao in view of Hattori, Ma, and Shinoda discloses the method of claim 9 (Ma: Fig. 8) wherein depositing a material that blocks infrared light further comprises depositing a black matrix resist (800; pg. 6 of translation: “black lithographic material form the solder resist layer 800”).
Regarding independent claim 12 as noted in the 112(b) rejection, Gao discloses an apparatus (Fig. 6), comprising:
a semiconductor die (a portion of 600; pg. 4 of translation: “the semiconductor wafer 600 to the front side array distributed with several chip (not shown)”; corresponds to a portion of Fig. 7: 700) having bond pads (601) on a device side surface (See annotated Fig. 7 for surface designation),
having a backside surface opposite the device side surface (See annotated Fig. 7 for surface designation) and having four sides (See annotated Fig. 7 for surface designation) extending between the device side surface and the backside surface;
a layer of light blocking material (704) deposited on the device side surface (directly on), the light blocking material also covering the four sides extending between the device side surface (directly covering);
semiconductor material (Fig. 7(g) before dicing: See annotation “semiconductor material segment”) on the exterior of the light blocking material (this material is horizontally on and sandwiched between two portions of material 704) covering the four sides (horizontally covering), the semiconductor material spaced from the semiconductor die by the light blocking material covering the four sides (this material is horizontally on and sandwiched between two portions of material 704);
a backside coating (706 is deposited on the backside surface in the claimed sequence, but is not the claimed tape) of light blocking tape covering the backside surface (directly covering);
openings (See annotated figure 7(g)) in the layer of light blocking material on the device side surface, the openings exposing (fully expose) under-bump material (Fig. 6: 606, corresponds to Fig. 7: 701) formed on the bond pads (directly on, as shown in Fig. 6);
and terminals (705) that are formed by solder bumps or conductive post connects (Fig. 7(g): solder bumps are illustrated) formed on the under-bump material (directly on).
Gao illustrates the die in a cross-sectional view and thus teaches the die including at least two sides. However, Gao fails to teach specific details regarding the top-down/perspective shape of the die. Thus, Gao fails to teach “a semiconductor die having bond pads on a device side surface, having a backside surface opposite the device side surface and having four sides extending between the device side surface and the backside surface;
a layer of light blocking material deposited on the device side surface, the light blocking material also covering the four sides extending between the device side surface;
semiconductor material on the exterior of the light blocking material covering the four sides, the semiconductor material spaced from the semiconductor die by the light blocking material covering the four sides;”.
Hattori discloses a die (Fig. 1: 101) having four sides extending between the device side surface and the backside surface (a quadrilateral shape is shown in the). Modifying the semiconductor die shape of Gao by incorporating the shape of Hattori would arrive at the claimed die shape. A person of ordinary skill in the art before the effective filing date would have had predictable results doing so because in each situation the die is incorporated on a wafer (Gao: pg. 4. “the semiconductor wafer 600 to the front side array distributed with several chip (not shown)”; Hattori: Fig. 1: wafer 100 and dies 101). Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date to have the claimed die shape because it is a mere change in shape of parts consistent with the teachings elsewhere in the prior art. MPEP 2144.04 (IV)(B).
Gao teaches material but fails to teach this material being light blocking. Thus, Gao in view of Hattori fails to teach “a layer of light blocking material deposited on the device side surface, the light blocking material also covering the four sides extending between the device side surface;
semiconductor material on the exterior of the light blocking material covering the four sides, the semiconductor material spaced from the semiconductor die by the light blocking material covering the four sides;
a backside coating of light blocking tape covering the backside surface;
openings in the layer of light blocking material on the device side surface”.
Ma discloses a layer of light blocking material (Fig. 8: 800; pg. 6 of translation: “black lithographic material form the solder resist layer 800”; pg. 7: “blocking the infrared ray”) deposited on the device side surface (See annotated figure), the light blocking material also covering the four sides extending between the device side surface. Modifying the material of Gao in view of Hattori by depositing the light blocking material of Ma would arrive at the claimed light blocking material configuration. Doing so would have been predictable to one of ordinary skill in the art before the effective filing date because in each situation a resist material is used for exposing under-bump metallization (Gao: Fig. 7: 701; Ma: Fig. 8: 400). Ma provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have the claimed light blocking material in that it would improve patterning of the material (pg. 7: “improves the imaging effect of the chip”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the light blocking material configuration because it would improve patterning of the material. MPEP 2143 (I)(G).
Gao in view of Hattori and Ma fails to teach “a backside coating of light blocking tape covering the backside surface”.
Shinoda discloses a backside coating ([0140]: “the semiconductor chip having the protective film at the backside”) of light blocking ([0085]: “The protective film…infrared ray…can be blocked”) tape ([0140]: “The dicing sheet with the protective film”). Modifying the backside coating of Gao, Hattori, and Ma by including the tape of Shinoda would arrive at the claimed tape configuration. Doing so would have been predictable to one of ordinary skill in the art before the effective filing date because in each situation the backside surface includes a protective coating (Gao: Fig. 7(g): 706; Shinoda: [0139]: “the dicing sheet with the protective film forming layer of the present invention has excellent expanding property”). Shinoda provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have the claimed backside coating of light blocking tape in that it would protect the die from cracking during manufacture ([0140]: “the protective film with high uniformity of the thickness can be easily formed at the chip backside, thus the cracks caused during the dicing step or packaging becomes difficult to occur”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed tape configuration because it would protect the die during manufacture. MPEP 2143 (I)(G).
Regarding claim 14, Gao in view of Hattori, Ma, and Shinoda discloses the apparatus of claim 12 (Gao: Fig. 7(g)), wherein terminals that are formed by solder bumps or conductive post connects formed on the under-bump material are solder bumps (solder bumps are illustrated) formed by a solder ball drop (pg. 5: “set solder balls”) and reflow process (pg. 5: “reflow”).
Further as to claim 14, the claimed process step “formed by a solder ball drop and reflow process” have not given any patentable weight since a “product-by-process” claim is directed to a product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product-by-process” claim, and not the patentability of the process, and that old or obvious product produced by a new method is not patentable as a product, whether claimed in “product-by-process” claim or not. Note that applicant has the burden of proof in such case, as the above case law makes clear. MPEP 2113.
Regarding claim 15 as noted in the 112(b) rejection, Gao in view of Hattori, Ma, and Shinoda discloses the apparatus of claim 12, wherein the layer of light blocking material (Ma: Fig. 8: 800; pg. 6 of translation: “black lithographic material form the solder resist layer 800”; pg. 7: “blocking the infrared ray”) and the backside coating of light blocking tape ([0085]: “The protective film…infrared ray…can be blocked”) block infrared light.
Regarding claim 16, Gao in view of Hattori, Ma, and Shinoda discloses the apparatus of claim 12 (Ma: Fig. 8), wherein the layer of light blocking material comprises a black matrix resist (800; pg. 6 of translation: “black lithographic material form the solder resist layer 800”).
Regarding claim 17, Gao in view of Hattori, Ma, and Shinoda discloses the apparatus of claim 16 (Ma: Fig. 8), wherein the layer of light blocking material comprises an infrared blocking resist (pg. 7: “blocking the infrared ray”).
Regarding claim 19, Gao in view of Hattori, Ma, and Shinoda discloses the apparatus of claim 12, wherein the backside coating of light blocking tape comprises Adwill LC backside coating tape from LINTEC OF AMERICA, INC (Shinoda: [0153]: “LC2850” or [0154]: “LC2822”).
Regarding independent claim 20, Gao discloses a method for forming wafer-level chip scale packaged semiconductor devices (Fig. 6), comprising:
forming under-bump metallization material (606, corresponds to Fig. 7: 701) on bond pads (601) of semiconductor dies (a portion of 600; pg. 4 of translation: “the semiconductor wafer 600 to the front side array distributed with several chip (not shown)”; corresponds to a portion of Fig. 7: 700) arranged in rows and columns on a device side surface of a semiconductor wafer,
the semiconductor dies spaced from one another by scribe lanes (Fig. 7: See annotated figure) of less than 50 microns width (pg. 5: “the two intervals of the grooves 703 can be 50-100 microns” teaches spacing of trenches which renders a scribe line between these trenches. See annotated figure. Note: additional remarks are provided below regarding the claimed die spacing range) from die edge to die edge (See annotated Fig. 7(g) for “die edge”);
forming trenches (702) adjacent the scribe lanes (horizontally adjacent) extending from the device side surface into but not through the semiconductor wafer (702 does not fully extent through the dies of wafer 700) along edges of the semiconductor dies (See annotated Fig. 7 for surface designations);
depositing light blocking material (704) over the device side surface of the semiconductor wafer (directly over), the light blocking material filling the trenches (completely filling) to form filled trenches (trenches 702 filled with material 704) and forming a layer of the light blocking material (Fig. 7(b): the intermediate thickness of 704 in the method step of) covering the device side surface of the semiconductor dies (directly covering), the layer of light blocking material having a thickness of about 10 microns or less;
patterning the layer of light blocking material (Fig. 7(c)) to expose (fully expose) the under-bump metallization material over the bond pads of the semiconductor dies (701 is fully exposed) and to expose (indirectly expose) the scribe lanes between the filled trenches (indirectly exposed because material 704 thickness is uniformly reduced including over the scribe lines);
forming solder bumps (705) on the under-bump metallization (directly on);
backgrinding (Fig. 7(e)) a backside surface of the semiconductor wafer (See annotated figure for surface designation) to thin the semiconductor wafer and to expose (fully expose) the light blocking material in the filled trenches at the backside surface (Fig. 7(e) fully exposes material 704 at the backside surface);
depositing a light blocking backside coating tape on the backside surface (706 is deposited on the backside surface in the claimed sequence, but is not the claimed tape);
dicing the semiconductor wafer along the scribe lanes (Fig. 7(g)) using laser dicing or plasma dicing,
the dicing leaving semiconductor material edges (See annotated Fig. 7(g) showing the semiconductor material) along the filled trenches on the sides of the semiconductor dies (this material is indirectly on the fully exposed sides of the dies); and
expanding the semiconductor wafer to separate the semiconductor dies from one another to form packaged semiconductor devices.
Gao fails to teach “the semiconductor dies spaced from one another by scribe lanes of less than 50 microns width”. However, Gao teaches the scribe lane is substantially similar in width (pg. 5: “the two boundary is totally cut off”) to a portion of the wafer (See annotated Fig. 7: “semiconductor material segment”). Additionally, Gao establishes a scale for this portion of wafer by teaching trench spacing substantially similar to the claimed die spacing (pg. 5: “the two intervals of the grooves 703 can be 50-100 microns”). Furthermore, Gao teaches trench spacing may be modified according to dicing equipment (pg. 5: “adjusting width of the interval according to the blade”). Thus, the claimed die spacing range is at least close to the range disclosed in the prior art. Therefore, the claimed die spacing range would have been obvious to one having ordinary skill in the art before the effective filing date, since a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985). MPEP 2144.05 (I).
Gao fails to explicitly teach “dicing the semiconductor wafer along the scribe lanes using laser dicing or plasma dicing”. However, Gao teaches cutting a wafer may include laser cutting or plasma cutting (pg. 4: “laser, plasma, or blade cutting method in wafer 700 dicing groove 702 is formed”). Modifying the dicing method by using laser dicing or plasma dicing would have been predictable to one of ordinary skill in the art before the effective filing date because in each situation the wafer is cut to at least some extent (the trenches 702 and the scribe lanes each cut a portion of the wafer 700), and Gao teaches these cutting techniques are comparable to the exemplary dicing technique (dicing technique: pg. 5: “blade 710”; cutting techniques: pg. 4: “laser, plasma, or blade cutting method in wafer”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed dicing method because it is using a technique disclosed elsewhere in the prior art with a similar structure in a similar way. MPEP 2143 (I)(C).
Gao fails to teach the method including “semiconductor dies arranged in rows and columns,” and “expanding the semiconductor wafer to separate the semiconductor dies from one another to form packaged semiconductor devices”.
Hattori discloses a method with dies (Fig. 1: 101) arranged in rows and columns (See annotated figure). Modifying the semiconductor die arrangement in the method of Gao by duplicating the dies in the same way as Hattori would arrive at the claimed arrangement in the method. A person of ordinary skill in the art before the effective filing date would have had predictable results doing so because in each situation the method includes a plurality of dies on a wafer (Gao: pg. 4. “the semiconductor wafer 600 to the front side array distributed with several chip (not shown)”; Hattori: Fig. 1: wafer 100 and dies 101). Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date to have the claimed die arrangement method because it is a mere duplication of parts consistent with the teachings elsewhere in the prior art. MPEP 2144.04 (VI)(B).
Hattori additionally discloses expanding the semiconductor wafer to separate the semiconductor dies from one another to form packaged semiconductor devices (pg. 2: “the expand sheet 113 of the workset 110 is expanded to form a predetermined spacing between the chips 120 of the wafer 100”). Modifying the method of Gao by including the “expanding” method step of Hattori would arrive at the claimed expanding method configuration. Hattori provides a teaching to motivate one to include the expanding method configuration in that it would enable a reduction in damage during subsequent manufacturing steps (pg. 5: “damage due to contact between the chips 120 can be suppressed”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed expanding method configuration because it would enable a reduction in damage during manufacture. MPEP 2143 (I)(G).
Gao teaches depositing material but fails to teach this material being light blocking. Thus, Gao in view of Hattori fails to teach “depositing light blocking material over the device side surface of the semiconductor wafer, the light blocking material filling the trenches to form filled trenches and forming a layer of the light blocking material covering the device side surface of the semiconductor dies, the layer of light blocking material having a thickness of about 10 microns or less;
patterning the layer of light blocking material to expose the under-bump metallization material over the bond pads of the semiconductor dies and to expose the scribe lanes between the filled trenches;
forming solder bumps on the under-bump metallization; backgrinding a backside surface of the semiconductor wafer to thin the semiconductor wafer and to expose the light blocking material in the filled trenches at the backside surface;”.
Ma discloses a method (Fig. 8) depositing light blocking material (800; pg. 6 of translation: “black lithographic material form the solder resist layer 800”; pg. 7: “blocking the infrared ray”) over the device side surface (See annotated figure). Modifying the method of Gao in view of Hattori by depositing this light blocking material as the material would arrive at the claimed method and light blocking material configuration. Doing so would have been predictable to one of ordinary skill in the art before the effective filing date because in each situation a resist material is used for exposing under-bump metallization (Gao: Fig. 7: 701; Ma: Fig. 8: 400). Ma provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have the claimed light blocking material and method configuration in that it would improve patterning of the material (pg. 7: “improves the imaging effect of the chip”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the method include the light blocking material configuration because it would improve patterning of the material. MPEP 2143 (I)(G).
Gao in view of Hattori and Ma fails to teach “depositing a light blocking backside coating tape on the backside surface;”.
Shinoda discloses depositing a light blocking ([0085]: “The protective film…infrared ray…can be blocked”) backside coating tape ([0140]: “The dicing sheet with the protective film”) on the backside surface ([0140]: “the semiconductor chip having the protective film at the backside”). Modifying the method of Gao, Hattori, and Ma by including the tape of Shinoda would arrive at the claimed method. Doing so would have been predictable to one of ordinary skill in the art before the effective filing date because in each situation the backside surface is deposited on expanding tape (Hattori: Fig. 1: 113; Shinoda: [0139]: “the dicing sheet with the protective film forming layer of the present invention has excellent expanding property”). Shinoda provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have the claimed light blocking backside coating tape in that it would protect the die from cracking during manufacture ([0140]: “the protective film with high uniformity of the thickness can be easily formed at the chip backside, thus the cracks caused during the dicing step or packaging becomes difficult to occur”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the method include the claimed tape configuration because it would protect the die during manufacture. MPEP 2143 (I)(G).
Regarding claim 21, Gao in view of Hattori, Ma, and Shinoda discloses the method of claim 20, wherein expanding the semiconductor wafer to separate the semiconductor dies from one another to form packaged semiconductor devices further comprises: forming the packaged semiconductor devices having the layer of light blocking material over the device side surface (704 is retained at method step Fig. 7(g). This method step corresponds to the method step where the expanding of Hattori is performed. Hattori makes no requirement for removal of light blocking materials or their analogues, i.e., solder resist. Thus, this material is retained in the same way shown by Gao.), having the light blocking backside coating tape on the backside surface opposite the device side surface (Shinoda: the cited light blocking component of the tape), and having the light blocking material on the four sides (Gao: Fig. 7(g) shows material 704 is on the sides of the die but only shows a cross-sectional view. Hattori: Fig. 1 was relied upon in the claim 1 rejection to teach die arrangement. This die arrangement produces 4 sides of the die. Therefore, the material 704 of Gao is retained in the same way on these 4 sides of the die.) between the device side surface and the backside surface, whereby exterior surfaces of the packaged semiconductor devices are covered (all surfaces are fully and directly covered) with light blocking material (the collection of Gao: Fig. 7: 704 and Shinoda: the cited light blocking component of the tape).
Regarding claim 22, Gao in view of Hattori, Ma, and Shinoda discloses the method of claim 21, and further comprising leaving semiconductor material edges (See annotated Fig. 7(g) showing “semiconductor material segment”) on the exterior surfaces of the four sides of the packaged semiconductor devices (this material is horizontally on the sides of the dies before the completion of dicing/expanding), the semiconductor material edges spaced from the semiconductor dies by the light blocking material (the edges of this material is horizontally on and sandwiched between two portions of material 704).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Go, Hattori, Ma, and Shinoda as applied to claim 1 above, and further in view of Sherbin (US 20200176314 A1).
Regarding claim 3, Gao in view of Hattori, Ma, and Shinoda discloses the method of claim 1 (Gao: Fig. 7(g)), however fails to teach “wherein dicing the semiconductor wafer along the scribe lanes using either laser dicing or plasma dicing further comprises: using a stealth laser dicing process, focusing a laser beam into the semiconductor wafer beneath the device side surface, and traversing the semiconductor wafer along the scribe lanes with the laser beam to form stress dislocation regions within the semiconductor wafer”.
Sherbin discloses a method (Fig. 1) wherein dicing the semiconductor wafer (105) along the scribe lanes (106) using either laser dicing or plasma dicing (laser beam 131) further comprises: using a stealth laser dicing process ([0006]: “conventional stealth laser dicing”), focusing a laser beam into the semiconductor wafer ([0023]: “the IR laser beam is focused with a focal point embedded within a thickness of the wafer”) beneath the device side surface ([0025]: “a point of entry of the IR laser beam 131 from the front side”), and traversing the semiconductor wafer along the scribe lanes with the laser beam ([0023]: “scanning the IR laser beam relative to the wafer along intended cutting lines in the scribe streets”) to form stress dislocation regions within the semiconductor wafer ([0023]: “to form subsurface laser modified defect regions”). Modifying the method of Gao, Hattori, Ma, and Shinoda by incorporating the stealth laser dicing technique of Sherbin would arrive at the claimed dicing method configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success because in each situation a laser is used for dicing a wafer (Gao as applied in the claim 1 rejection: dicing technique: pg. 5: “blade 710”; cutting techniques: pg. 4: “laser, plasma, or blade cutting method in wafer”; Sherbin: [0023]: “to dice the wafer”). Sherbin provides a teaching to motivate one of ordinary skill in the art before the effective filing date to incorporate the stealth laser dicing process when dicing the semiconductor wafer in that it would enable the production of smaller dies, thereby enhancing manufacturing capability ([0025]: “Small die capabilities are also improved”).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Go, Hattori, Ma, and Shinoda as applied to claim 1 above, and further in view of Zensei (JP 2009145395 A).
Regarding claim 5, Gao in view of Hattori, Ma, and Shinoda disclose method of claim 1, however, Ma fails to teach specific recipe settings used when depositing the layer of light blocking material. Thus, the combination of references fails to teach “wherein depositing a layer of light blocking material over the device side surface of the semiconductor dies on the semiconductor wafer further comprises: dispensing a liquid pre-wet material onto the semiconductor wafer in a spin-coating process; using a first spin speed, allowing the pre-wet material to fill the trenches; dispensing liquid light blocking material onto the semiconductor wafer; using a second spin speed, displacing the pre-wet material and filling the trenches with the light blocking material; using a third spin speed greater than the first spin speed, making the thickness of the light blocking material on the device side surface uniform; and thermally curing the liquid light blocking material to form the layer of light blocking material”.
Zensei discloses a method wherein depositing a layer of light blocking material (pg. 5 of translation: “protective film”) over the device side surface of the semiconductor dies on the semiconductor wafer (pg. 5: “300 mm substrate”) further comprises: dispensing a liquid pre-wet material (pg. 5: “applying a prewetting agent”) onto the semiconductor wafer in a spin-coating process (pg. 5: “spin coating or the like can be mentioned”); using a first spin speed (pg. 5: “the wafer is rotated at a predetermined rotation speed of 1000 rpm or less”), allowing the pre-wet material to fill the trenches (pg. 5: “the pre-wetting agent is diffused throughout the substrate by centrifugal force”); dispensing liquid light blocking material (pg. 5: “a small amount of resist solution”) onto the semiconductor wafer (pg. 5: “a resist protective film is dropped on the approximate center of the substrate”); using a second spin speed (pg. 5: “1000 to 4000 rpm for a 300 mm substrate”), displacing the pre-wet material and filling the trenches with the light blocking material (pg. 5: “diffused throughout the resist film”); using a third spin speed (pg. 5: “the rotation speed of the substrate is increased again”) greater than the first spin speed (pg. 5: “1000 to 3000 rpm for a 300 mm substrate”. Note: with the exception of the overlapping endpoint of 1000 rpm, this range is entirely greater than the cited first spin speed range), making the thickness of the light blocking material on the device side surface uniform (pg. 5: “film thickness of the resist protective film is adjusted”); and thermally curing (pg. 5: “dried” must necessarily occur at some temperature, thus there is at least some thermal component to the curing) the liquid light blocking material to form the layer of light blocking material.
Modifying the method of Gao in view of Hattori, Ma, and Shinoda by incorporating the depositing technique of Zensei while depositing the layer of light blocking material (of Ma) would arrive at the claimed method. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success using this technique because in each situation the material applied is resist material (Ma: pg. 7: “black lithographic material forming solder resist layer 800 on the wiring layer by way of coating”; Zensei: pg. 5: “resist solution”). Zensei provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the claimed deposition technique in that it would enable using small amounts of liquid during manufacture, thereby reducing manufacturing cost (pg. 5: “even a small amount of resist solution can be diffused throughout the resist film”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed deposition method because it would enable reduced manufacturing cost.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Go, Hattori, Ma, and Shinoda as applied to claim 10 above, and further in view of Kaneko (US 20220213296 A1).
Regarding claim 11, Gao in view of Hattori, Ma, and Shinoda teaches the method of claim 10 (Ma: Fig. 8), and teaches the black matrix resist (cited in the claim 10 rejection). However, Ma fails to teach specific commercial formulations useful for this resist. Thus, the combination of references fails to teach “wherein depositing a material that blocks infrared light further comprises depositing SK-7000 resist material from Fujifilm Electronic Materials U.S.A., Inc., or depositing CFPR BK-8310 resist material Tokyo Ohka Kogyo (TOK) America, Inc., Milpitas, California, U.S.A”.
Kaneko discloses a finite selection of black matrix resist comprises SK-7000 resist material from Fujifilm Electronic Materials U.S.A., Inc., or depositing CFPR BK-8310 resist material Tokyo Ohka Kogyo (TOK) America, Inc., Milpitas, California, U.S.A (selecting SK-7000; [0594]: “SK-7000 (product name), which are black resist materials manufactured by FUJIFILM Electronic Materials Co., Ltd.”). Modifying the black resist matrix resist of Ma in the combination of Gao, Hattori, Ma, and Shinoda by choosing SK-7000 resist material from the finite selection disclosed by Kaneko would arrive at the claimed method and resist configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Kaneko discloses the resist is a commercially available black matrix resist ([0594]: “product name…manufactured”), thus it is a readily available material useful for the same purpose. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed method and resist configuration because it is a selection made from a finite selection of known suitable materials. MPEP 2143 (I)(E).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Go, Hattori, Ma, and Shinoda as applied to claim 12 above, and further in view of Huang (US 20230066968 A1).
Regarding claim 13, Gao in view of Hattori, Ma, and Shinoda discloses the apparatus of claim 12, wherein the terminals that are formed by solder bumps or conductive post connects formed on the under-bump material, but fails to teach the claimed configuration wherein these terminals “further comprise: copper pillars formed on the under-bump material and extending away from the device side surface of the semiconductor die to a distal end; and solder bumps formed on the distal end of the copper pillars, the copper pillars and the solder bumps forming copper pillar bumps”.
Huang discloses terminals (Fig. 6: 182) that are formed by solder bumps or conductive post connects formed on the under-bump material (144) further comprise: copper pillars ([0025]: “copper posts (or pillar)”) formed on the under-bump material and extending away from the device side surface of the semiconductor die to a distal end; and solder bumps ([0025]: “solder caps”) formed on the distal end of the copper pillars, the copper pillars and the solder bumps forming copper pillar bumps ([0025]: “conductive pillars with solder caps”). Modifying the terminals of Gao, Hattori, Ma, and Shinoda by using the terminals disclosed by Huang would arrive at the claimed terminal configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Huang teaches these terminals may be used alternative to solder bumps ([0025]: “the conductive bumps 182 may include placing solder balls…The conductive bumps 182 may also include conductive pillars, or conductive pillars with solder caps”). Huang provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have the claimed terminal configuration in that it would enable denser arrangements of terminals, thereby enabling advanced circuitry ([0025]: “For advanced packaging of semiconductor devices 110 with many function circuitries, the sizes of conductive bumps 182 may be relatively small to enable more bumps to connect to an input/output (I/O) of semiconductor devices 110…As a result, the conductive bumps 182 with fine pitches and sizes, such as micro-bumps, are used for external connections. Micro-bumps may include copper posts”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed terminal configuration because it would enable advanced circuity. MPEP 2143 (I)(G).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Go, Hattori, Ma, and Shinoda as applied to claim 17 above, and further in view of Kaneko.
Regarding claim 18, Gao in view of Hattori, Ma, and Shinoda discloses the apparatus of claim 17 (Ma: Fig. 8), and teaches the layer of light blocking material (cited in the claim 16 and 17 rejections). However, Ma fails to teach specific commercial formulations useful for this material. Thus, the combination of references fails to teach “wherein the layer of light blocking material comprises SK-7000 resist material from Fujifilm Electronic Materials U.S.A., Inc., or CFPR BK-8310 resist material from Tokyo Ohka Kogyo (TOK) America, Inc”.
Kaneko discloses a finite selection of black matrix resist comprises SK-7000 resist material from Fujifilm Electronic Materials U.S.A., Inc., or depositing CFPR BK-8310 resist material Tokyo Ohka Kogyo (TOK) America, Inc., Milpitas, California, U.S.A (selecting SK-7000; [0594]: “SK-7000 (product name), which are black resist materials manufactured by FUJIFILM Electronic Materials Co., Ltd.”). Modifying the black resist matrix resist of Ma in the combination of Gao, Hattori, Ma, and Shinoda by choosing SK-7000 resist material from the finite selection disclosed by Kaneko would arrive at the claimed resist configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Kaneko discloses the resist is a commercially available black matrix resist ([0594]: “product name…manufactured”), thus it is a readily available material useful for the same purpose. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed resist configuration because it is a selection made from a finite selection of known suitable materials. MPEP 2143 (I)(E).
Conclusion
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817