DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application TW 112150317 filed in Taiwan Intellectual Property Office (TIPO) on December 22, 2023 and receipt of a certified copy thereof.
Information Disclosure Statement
The information disclosure statement (IDS) filed on December 29, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner.
Election/Restrictions
Applicant’s election of Invention I (claims 1-19) in the reply filed on April 22, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Therefore, claim 20 drawn to non-elected invention has been withdrawn from examination for patentability.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 8-10 and 12 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Wu et al. US 2021/0118844.
Regarding claim 1, Wu teaches a composite substrate (e.g., S, Fig. 5, Fig. 6A) adaptable for connecting a plurality of dies (e.g., 101, Fig. 6A, Fig. 7, Fig. 1, and the description thereof; also see Figs. 2-5 and the description thereof for additional details), and the composite substrate comprising:
a printed circuit board (e.g., PCB; see the annotated Fig. 6A below);
at least one first redistribution layer (e.g., 1st RDL; see the annotated Fig. 6A below) disposed on the printed circuit board; and
a first connecting layer (e.g., 1st CL; see the annotated Fig. 6A below) disposed to electrically connect the at least one first redistribution layer and the printed circuit board,
wherein each of the plurality of dies (e.g., 101, Fig. 6A) is electrically connected to the at least one first redistribution layer (e.g., Fig. 6A, Fig. 5, Fig. 1), and is integrally disposed with the at least one first redistribution layer corresponding to each of the plurality of dies (e.g., Fig. 6A, Fig. 7).
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Annotated Fig. 6A of WU
Regarding claim 2, Wu teaches the composite substrate according to claim 1, wherein the first connecting layer comprises an adhesive (e.g., [53]).
Regarding claim 8, Wu teaches the composite substrate according to claim 1, further comprising a second connecting layer (e.g., 2nd CL; see the annotated Fig. 6A above) and at least one second redistribution layer (e.g., 2nd RDL; see the annotated Fig. 6A above) that are disposed on one side of the printed circuit board away from the at least one first redistribution layer, wherein the second connecting layer is disposed to electrically connect the at least one second redistribution layer and the printed circuit board (e.g., see the annotated Fig. 6A above).
Regarding claim 9, Wu teaches the composite substrate according to claim 1, further comprising a through hole (e.g., through hole in which the vias 149 are disposed; see the annotated Fig. 6A above) penetrating the first connecting layer, wherein the at least one first redistribution layer is electrically connected to the printed circuit board through the through hole (e.g., see the annotated Fig. 6A above).
Regarding claim 10, Wu teaches the composite substrate according to claim 1, wherein the at least one first redistribution layer comprises a plurality of conductive lines (e.g., 135, Fig. 6A, Fig. 5), and line widths of the plurality of conductive lines corresponding to each of the plurality of dies are smaller than line widths of the plurality of conductive lines that do not correspond to each of the plurality of dies (e.g., Fig. 6A, Fig. 5).
Regarding claim 12, Wu teaches the composite substrate according to claim 1, wherein the printed circuit board comprises a through hole whose width is gradually increased in a stacking direction of the composite substrate (e.g., through hole in which 149 is disposed and whose width gradually increased in a stacking direction along which the 2nd RDL, 2nd CL, PCB, 1st CL and 1st RDL are sequentially stacked; see the annotated Fig. 6A above), and the at least one first redistribution layer comprises a through hole whose width is gradually decreased in the stacking direction (e.g., through hole in which 137 (132) is disposed and whose width gradually decreased in the stacking direction discussed above; see the annotated Fig. 6A above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. US 2021/0118844 in view of Huang et al. US 2014/0263586.
Regarding claim 3, Wu teaches the composite substrate according to claim 1 as discussed above.
Wu does not explicitly teach wherein the first connecting layer utilizes a hybrid bonding technology to connect the at least one first redistribution layer and the printed circuit board.
Wu, however, recognizes that copper via/pad 149 of the first connection layer (1st CL) and the copper line/pad 147 of the printed circuit board (PCB) are bonded to each other, and their surrounding dielectric materials 145 are bonded to each other (see the annotated Fig. 6A above; [53], [52]).
Huang teaches wherein copper pads (112, 212) are bonded to each other and their surrounding dielectric materials (110, 210) are bonded to each other by hybrid bonding (e.g., Fig. 8, [17], [35], [36], [37]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate of Wu to include hybrid bonding as suggested by Huang for the purpose of realizing a seamless, bump/solder-free connection, thereby enhancing data transfer speeds and reducing latency for example. In this case, Wu in view of Huang thus teaches wherein the first connecting layer utilizes a hybrid bonding technology to connect the at least one first redistribution layer and the printed circuit board.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. US 2021/0118844 in view of Yee et al. US 2017/0062383.
Regarding claim 7, Wu teaches the composite substrate according to claim 1, wherein the at least one first redistribution layer comprises a plurality of conductive lines (e.g., 135, Fig. 6A) as discussed above.
Wu does not explicitly teach a roughness of each of the plurality of conductive lines falls within a range of 0.2 microns to 0.7 microns.
Wu, however, recognizes that the copper via/pad 137 and the copper line/pad 135 of the first redistribution layer (1st RDL) are bonded to each other, and their surrounding dielectric materials 133 are bonded to each other (see the annotated Fig. 6A above; [54], [52]).
Yee teaches wherein the copper pads and copper connector 502 are bonded to each other and their surrounding dielectric materials are bonded to each other by hybrid bonding, and to form a hybrid bond, the surface roughness of the connector and the dielectric materials should be controlled by polishing (e.g., [40]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to control and optimize the substrate of Wu to include the claimed roughness range for a hybrid bond for the purpose of realizing a seamless, bump/solder-free connection, thereby enhancing data transfer speeds and reducing latency for example.
Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. US 2021/0118844.
Regarding claim 4, Wu teaches the composite substrate according to claim 1, wherein each of the plurality of dies is connected to the at least one first redistribution layer through a plurality of solder bumps (e.g., 131, see the annotated Fig. 6A above), and the plurality of solder bumps are disposed between the corresponding die and the at least one first redistribution layer (e.g., see the annotated Fig. 6A above).
Wu does not explicitly teach a diameter of each of the plurality of solder bumps falls within a range of 10 microns to 200 microns.
Wu, however, recognizes that the conductive pads 132 accommodating 131 have sizes in the order of micro-meters (e.g., [56]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to control and optimize the substrate of Wu to have the claimed diameter range since it has been held that where the criticality of the claimed diameter range is not shown and the general and/or close conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Regarding claim 11, Wu teaches the composite substrate according to claim 10 as discussed above.
Wu does not explicitly teach wherein the line widths of the plurality of conductive lines corresponding to each of the plurality of dies fall within a range of 3 microns to 50 microns.
Wu, however, recognizes that the substrate S2 including the conductive lines 135 is formed using silicon fab processing techniques, which allows formation of feature sizes in the order of micro-meters.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to control and optimize the substrate of Wu to have the claimed line width range since it has been held that where the criticality of the claimed line width range is not shown and the general and/or close conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Allowable Subject Matter
Claims 5 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 13-19 are allowed at this time, pending updated search before the Examiner's next response, because the prior art of record neither anticipates nor render obvious the limitation of the base claim 13 that recites “at least one antenna, wherein the printed circuit board is disposed between the at least one antenna and the at least one first redistribution layer, and the at least one antenna is electrically connected to the plurality of dies through the composite substrate” in combination with other elements of the base claim 13.
Conclusion
The art made of record and not applied to the rejection is considered pertinent to applicant's disclosure. It is cited primarily to show inventions relevant to the examination of the instant invention.
For example, Shimizu et al. US 2015/0357276 and Hu US 2016/0064254 relate to a composite substrate including at least one redistribution layer; and a connecting layer disposed to be electrically connected to the redistribution layer.
For example, Wojnowski et al. US 2014/0110840 relates to a communication device including a composite substrate including a printed circuit board; at least one redistribution layer; and a connecting layer disposed to be electrically connected to the redistribution layer, and at least one antenna.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bo Bin Jang whose telephone number is (571) 270-0271. The examiner can normally be reached on M-F from 9:00 AM to 6:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://portal.uspto.gov/external/portal. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) OR 571-272-1000.
/BO B JANG/Primary Examiner, Art Unit 2818 July 16, 2026
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