Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed March 20, 2026.
Status of claims to be treated in this office action:
a. Independent: 1, 13, 16
b. Pending: 1-20
Claims 1, 4, 5, 12, 13, 16, and 17 have been amended.
Specification
The second and third objections to the disclosure, included below, which were filed in the Office Action dated December 22, 2025, are upheld. The second objection was not addressed and parts of the third objection need further changes.
Regarding para. [0053] of the Summary section, make the following revisions:
“the memory cell in the erase state E0 and the first program state P1 may be an on cell, and the memory cell in the second to seventh program states P2 to P7 may be an off cell”
Paras. [0071] and [0076] should be further amended as follows:
[0071]: The sub-block managing module 2000 may designate all sub-blocks (SB11 throughremaining sub-blocks as reclaim sub-blocks.
[0076]: The sub-block managing module 2000 may designate all sub-blocks SB11, SB12, and SB13 in the first memory block BLK1 as reclaim sub-blocks.
The amendment filed March 20, 2026 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows:
The following amendment to para. [0050], on pages 2-3, is not supported, as para. [0050] is concerned with only the first memory block BLK1.
“One or more than two of the sub-blocks SBn1, SBn2, and SBn3 may be selected and erased simultaneously”
Examiner believes the amendment should read:
“One or more than two of the sub-blocks SB11, SB12, and SB13 may be selected and erased simultaneously”
Applicant is required to cancel the new matter in the reply to this Office Action.
Additionally, page 2 includes an amendment to para. [0051], however this was not requested, and it appears that no amendment has been made.
Claim Objections
The claim objections are withdrawn pursuant to claim amendments.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Furthermore, the arguments were not persuasive and there was a change in scope to the independent claims.
In response to the arguments regarding 35 U.S.C. § 102 rejection of independent claim 1 on page 11:
Hong does not fail to describe the emphasized language of claim 1. Indeed, Hong teaches that there is a determination of whether to reclaim the second sub-block in Figs. 6-8, in paras. [0063]-[0064], and supported by [0070]. Specifically, there is a decision about which reclaim operation type to use to improve efficiency, and this decision determines whether a second word line will be reclaimed with the word line that includes a UECC.
Examiner agrees that Cai does not teach determining whether the second memory sub-block is a reclaim sub-block or performing subsequent operations based on that determination. However, Examiner asserts that Cai does teach identifying whether a reclaim operation should be performed on the second memory sub-block. Para. [0101] of Cai teaches: “If the error count of the most disturbed wordline exceeds the threshold value, at step 940, process 900 includes copying all valid MSB pages to another free block in the flash memory”. Examiner concludes that other word lines or pages (analogous to the second sub-block) may be reclaimed in the reclamation of the most disturbed word line (analogous to the first memory sub-block that has uncorrectable error(s)).
Examiner notes that the final argument regarding this 102 rejection corresponds to the last limitation of claim 1, which is rejected under 35 U.S.C. §112(a) and §112(b); see below. Regardless, Hong indeed teaches what the Examiner believes is the Specification-supported version of the limitation, which teaches that the second memory sub-block is either reclaimed or not reclaimed based on whether the second memory sub-block is a using sub-block or a not-used sub-block. Examiner points to the determination of which of a set of different reclaim operation types should be used to maximize efficiency per para. [0070]. Per Figs. 6-8, some of those reclaim operation types include reclaiming word line WL1a, which is analogous to the second memory sub-block, and per [0064], WL1a is “written,” or used/“using”. It would be inefficient to reclaim an unused/“not-used” sub-block.
In response to the arguments regarding 35 U.S.C. § 102 rejection of independent claims 13 and 16 on page 12: the arguments point to the arguments for claim 1, thus the Examiner points to the above responses.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
On page 4, lines 19-21 of the claims filed March 20, 2026, in the last limitation of independent claim 1, Applicant claims:
“wherein a memory sub-block of the first and second memory sub-blocks to be reclaimed varies depending on whether the second memory sub-block is the using sub-block or a not-used sub-block.”
The claim language indicated that the reclamation of the first memory sub-block depends on the using/not-used status of the second memory sub-block. There is no support in the Specification for this. This limitation, or nearly identical versions thereof, is repeated in the other independent claims, claims 13 and 16, on page 6, lines 19-21 and on page 7, lines 20-22, respectively.
Independent claims 1, 13, 16, and dependent claims 2-12, 14-15, and 17-20, which depend on the independent claims, are thus all rejected under 35 U.S.C. 112(a).
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
On page 4, line 14 and lines 16-17, in the third and fourth limitations of independent claim 1, respectively, Applicant claims: “memory sub-block as blocks”. This phrase is also used in claim 13 on page 6, line 14 and line 18, and in claim 16 on page 7, lines 14 and 16. This phrase is indefinite because it frames the first and second memory sub-blocks as blocks equivalent to the first and second memory block, instead of as sub-blocks. Examiner believes the phrase should be changed everywhere to “memory sub-block as sub-blocks”.
Additionally, on page 4, line 19, in the last limitation of claim 1, Applicant claims: “a memory sub-block of the first and second memory sub-blocks”. This phrase is also used in claim 13 on page 6, line 19, and in claim 16 on page 7, line 20. This phrase is indefinite because it suggests that a sub-block of a sub-block is being claimed.
Independent claims 1, 13, 16, and dependent claims 2-12, 14-15, and 17-20, which depend on the independent claims, are thus all rejected under 35 U.S.C. 112(a).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 6, 13, 16, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hong (US Pub. 20210249085 A1).
Regarding independent claim 1, Hong discloses a non-volatile integrated circuit memory device (Fig. 1: storage device 100; [0027]), comprising:
a first memory block (Fig. 6: first block BLK1; [0054]. Also see Figs. 7 & 8) having first and second memory sub-blocks therein ([0063]: referring to FIG. 8, the partial reclaim (P.R) may be performed by writing a portion of a block including data (or page) in which the UECC has occurred into a fresh block. According to Fig. 4 of the present application, a sub-block is a set of wordlines of the same block. It follows that a single wordline is a sub-block of just one element. First block BLK1 has sub-blocks WL1a and WL2a);
a second memory block (Fig. 6: second block BLK2; [0054]. Also see Figs. 7 & 8) having third and fourth memory sub-blocks therein (Fig. 8: sub-blocks WL7b and WL8b); and
a sub-block manager (Fig. 1: memory interface 127; [0080]; [0081]: The memory interface 127 may communicate commands, addresses, and data with the nonvolatile memory device 110 through an input/output channel) configured to:
determine whether the second memory sub-block is a reclaim sub-block when the first memory sub-block has an uncorrectable error (UECC) therein ([0064]: For example, it is assumed that the UECC has occurred in data written into a page of the second word line WL2a of the first block BLK1. In this case, a first area I including data of the second word line WL2a where the UECC has occurred and the first word line WL1a may be written into a second area II of the second block BLK2. Examiner asserts that WL2a is analogous to the first memory sub-block and WL1a is the second memory sub-block. WL2a has a UECC but WL1a does not. [0070]: Accordingly, in the storage device according to some example embodiments, a type of the reclaim operation may be selected depending on a situation to improve the operational efficiency of the storage device; [0051]: A detailed description of the type and operation of the reclaim will be given in detail with reference to FIGS. 6 to 8 below. Examiner asserts that the reclaim of WL2a may or may not include the reclaiming of WL1a as well, and therefore there is a determination);
identify, based on determining that the second memory sub-block is a reclaim sub- block and the first memory sub-block has an UECC, the first memory sub-block and the second memory sub-block as blocks on which a reclaim operation is to be performed (if the reclaim type of Fig. 8 is selected, both WL2a and WL1a, which are analogous to the first and second memory sub-blocks, are reclaimed); and
reclaim the first and second memory sub-blocks to the third and fourth memory sub-blocks, respectively, in response to the identifying the first and second memory sub-blocks as blocks on which a reclaim operation is to be performed ([0064]: the second word line WL2a where the UECC has occurred may be written into the eighth word line WL8b of the second block, and the first word line WL1a may be written into the seventh word line WL7b of the second block. Examiner asserts that when first sub-block WL2a has an uncorrectable error, both sub-blocks WL1a and WL2a are reclaimed to sub- blocks WL7b and WL8b);
wherein a memory sub-block of the first and second memory sub-blocks to be reclaimed varies depending on whether the second memory sub-block is a using sub-block or a not-used sub-block ([0064]: the first word line WL1a may be written into the seventh word line WL7b of the second block. Examiner concludes that since the word line WL1a, analogous to the second memory sub-block, is “written,” it is a using sub-block. [0070]: Accordingly, in the storage device according to some example embodiments, a type of the reclaim operation may be selected depending on a situation to improve the operational efficiency of the storage device. Examiner asserts that it would be inefficient to reclaim an unused sub-block).
Regarding claim 5, Hong discloses the limitations of claim 1. Further, through Hong:
wherein the sub-block manager (Fig. 1: 127) is configured to not designate the second memory sub-block as a reclaim sub-block when the second memory sub-block is the using sub-block or the not-used sub-block ([0061]: First, referring to FIG. 7, the partial reclaim may be performed by writing only data in which the UECC has occurred into a fresh block. Examiner notes that the only word line that is reclaimed is the word line with a UECC; a second word line is not reclaimed regardless of whether it is used).
Regarding claim 6, Hong discloses the limitations of claim 1. Further, through Hong:
wherein the sub-block manager (Fig. 1: 127) is configured to determine whether or not the second memory sub-block is a reclaim sub-block based on the number of error bits of the second memory sub-block ([0049]-[0051]: When the number of error bits described above increases, the memory cell of the nonvolatile memory device may not be able to be corrected using the error correction code (ECC). If the error bit level included in the read data cannot be corrected using an ECC block 128 of FIG. 1, an error called an uncorrectable ECC (UECC) is generated… In order to reduce or prevent the occurrence of the UECC, data from a memory block (source block) deteriorated by the retention reduction is moved in advance to a new fresh block (a destination block, a data-writable block) in a memory system, which is called reclaim).
Independent claim 13 contains a last limitation that is substantially the same as the last limitation of claim 1, and that limitation is thus rejected for the same reasons. Further through Hong:
A storage device (Fig. 1: storage device 100; [0027]), comprising:
a first memory block (Fig. 6: first block BLK1) having first to third memory sub-blocks therein (per Fig. 6 and [0054], BLK1 contains multiple word lines WL1a to WL8a. Using the same explanation from claim 1, a single word line is a sub-block of just one element. First block BLK1 contains sub-blocks WL1a, WL2a, and WL3a); and
a second memory block (second block BLK2; [0054]) having fourth to sixth memory sub-blocks therein (BLK2 contains sub-blocks WL6b, WL7b, and WL8b);
wherein the first memory sub-block has an uncorrectable error (UECC) therein ([0064]), the second memory sub-block is a using memory sub-block and the third memory sub-block is a not-used memory sub-block (in reference to Fig. 6, per [0055]: The block reclaim operation according to some example embodiments writes the entire data of a block including data in which the UECC has occurred to a fresh block; [0057]: However, in the case of the block reclaim according to some example embodiments, even data having no UECC occurred in one block (e.g., first block BLK1) is all written to a new block (e.g., the second block BLK2). Therefore, a storage space of the storage device including the nonvolatile memory device according to some example embodiments may be reduced. Examiner concludes that some word lines of BLK1 in Fig. 6 may be unused, since errors cannot exist in a word line that is unused); and
wherein the storage device (Fig. 1: 100) is configured to:
identify, based on determining that the second memory sub-block is a using sub- block, the first memory sub-block and the second memory sub-block as blocks on which a reclaim operation is to be performed ([0055]; [0057]); and
reclaim the first to second memory sub-blocks to the fourth to fifth memory sub-blocks, respectively, responsive to the identifying the first and second memory sub-blocks as blocks on which a reclaim operation is to be performed ([0064]);
Independent claim 16 contains limitations that are nearly identical to limitations from claims 1 and 13 except for containing a memory controller. All but the memory controller limitation are rejected for the same reasons as independent claims 1 and 13.
Hong further discloses:
a memory controller configured to control the memory device (Fig. 1: controller 120; [0074]: Referring back to FIG. 1, the nonvolatile memory device 110 may perform a write operation, a read operation, an erase operation, and/or a reclaim operation under the control of the controller 120);
the memory controller is configured to reclaim ([0074]) the first and second memory sub-blocks to the third and fourth memory sub-blocks, respectively ([0064]),
Regarding claim 20, Hong discloses the limitations of claim 16. Further, through Hong:
wherein the memory device is a flash memory ([0028]: The nonvolatile memory device 110 according to some example embodiments may include a 3D flash memory).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 7-9, 11, 14-15, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US Pub. 20210249085 A1) as applied to claims 1 and 13 above, and further in view of Cai (US Pub. 20170132125 A1).
Regarding claim 2, Hong discloses the limitations of claim 1, and further through
Hong:
wherein the first and second memory sub-blocks (Fig. 8: WL1a and WL2a) are erased in response to reclamation of the first and second memory sub-blocks ([0063]-[0064]).
Hong does not disclose erasing reclaimed sub-blocks.
However, Cai teaches erasing reclaimed sub-blocks ([0057]: The garbage collection (GC) procedure selects a few blocks with the least number of valid data and copies the valid data of those selected victim blocks to a free block. Then, garbage collection can erase those victim blocks that were selected to move data and put them in the list of free blocks. Examiner asserts that the garbage collection method is a reclamation process, and thus erasing is performed after reclamation. Also see Fig. 10, steps 1040, 1080, and 1096 (reclamations), and 1098 (erase)).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Cai to Hong wherein reclaimed sub-blocks are erased in order to reduce write amplification and thereby improve the lifetime of the storage device (Cai, [0060]).
Regarding claim 3, Hong discloses the limitations of claim 1. Further, through Hong:
wherein the first and second memory sub-blocks are sequentially erased ([0075]: The nonvolatile memory device 110 may receive an erase command and an address from the controller 120 to erase data in a storage space identified by the address. Examiner concludes that an address is assigned to each sub-block, and therefore erase may be performed sequentially for each sub-block to be erased) in response to reclamation of the first and second memory sub-blocks ([0063]-[0064]).
Hong does not disclose sequentially erasing reclaimed sub-blocks.
However, Cai teaches sequentially erasing reclaimed sub-blocks ([0057]; [0035]; [0067]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Cai to Hong wherein reclaimed sub-blocks are sequentially erased in order to reduce write amplification and thereby improve the lifetime of the storage device (Cai, [0060]).
Regarding claim 4, Hong discloses the limitations of claim 1. Hong discloses a sub-block manager but does not disclose:
designate the second memory sub-block as a reclaim sub-block when the second memory sub-block is the using sub-block, but not when the second memory sub-block is the not-used sub-block.
However, Cai teaches:
designate the second memory sub-block as a reclaim sub-block when the second memory sub-block is the using sub-block, but not when the second memory sub-block is the not-used sub-block ([0056]: The additional data generated by flash controller firmware can include at least…(2) additional data programming caused by data recycling because of read disturb reclaim where valid data in a reclaimed block are copied to free blocks to eliminate accumulated read disturb errors. Examiner concludes that if a block contains valid data, a sub-block within that block also contains valid data, and thus the second sub-block of the block is a using sub-block).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Cai to modified Hong wherein the second memory sub-block is designated as a reclaim sub-block when the second memory sub-block is the using sub-block, but not when the second memory sub-block is the not-used sub-block in order to reduce write amplification and thereby improve the lifetime of the storage device (Cai, [0060]).
Regarding claim 7, Hong discloses the limitations of claim 6, and further through
Hong:
wherein the sub-block manager (Fig. 1: 127) is further configured to compare the number of error bits of a predetermined word line of the second memory sub-block against a threshold value, and then determine whether the second memory sub-block is a reclaim sub-block according to a result of the comparison (in [0050]-[0051], Hong teaches that a reclaim will occur when the error bit level of a block is increased to the point where there are uncorrectable errors).
Hong does not explicitly disclose:
compare the number of error bits of a predetermined word line of the second memory sub-block against a threshold value, and then determine whether the second memory sub-block is a reclaim sub-block according to a result of the comparison.
However, Cai teaches:
compare the number of error bits of a predetermined word line ([0054]: A page, such as page 330, may share a common word-line and can represent a minimum programmable unit; [0069]: classifying the pages into multiple types based on error rate and selectively reclaiming or refreshing the data based on the page type classification. Examiner concludes that selecting a page could be analogous to selecting a word line) of the second memory sub-block against a threshold value (in reference to Fig. 7, per [0082]: at step 770, process 700 includes determining whether the errors in the second sub-block exceed a threshold value), and then determine whether the second memory sub-block is a reclaim sub-block according to a result of the comparison ([0083]-[0084]: If the errors in the second sub-block exceed a threshold value, at step 780, process 700 includes copying data associated with the second sub-block to a third memory block in the flash memory…Although not shown in FIG. 7, step 780 can also include updating a mapping table to indicate new mapping of logical addresses to addresses in the third memory block. At step 790, process 700 includes indicating that the first memory block is a block with its second sub-block reclaimed. In a two-level memory cell, this could represent an indication that the entire first memory block has been reclaimed).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Cai to modified Hong wherein there is a comparison of the number of error bits of a predetermined word line of the second memory sub-block against a threshold value, and then a determination of whether the second memory sub-block is a reclaim sub-block according to a result of the comparison in order to reduce write amplification and thereby improve the lifetime of the storage device (Cai, [0060]).
Regarding claim 8, Hong and Cai together disclose the limitations of claim 7, and further through Hong:
wherein the predetermined word line is the first programmed word line within the second memory sub-block (Fig. 8: WL2a; [0036]: In the first block BLK1…Memory cells (hereinafter, also referred to as pages) connected to the first word line WL1…may be programmed by selecting the first word line WL1 and the first string select line SSL1; per the reasoning provided in claim 1, a single wordline may be a sub-block of just one element, and thus the first wordline is the only wordline and will be programmed first).
Hong does not explicitly disclose:
the predetermined word line is the first programmed word line
However, Cai teaches:
the predetermined word line ([0054]; [0069]) is the first programmed word line ([0079]: process 700 includes determining one or more errors in the first sub-block of the first memory block…at step 730, process 700 includes determining whether the errors in the first sub-block exceed a threshold value; [0067]: the sub-blocks can represent pages of one kind of bits; [0072]: the first sub-block can represent an MSB page of the first memory block, and the second sub-block can represent an LSB page of the first memory block. Examiner concludes that a word line may be selected to be programmed before other word lines, and that one block is selected for checking error level at a time. Thus, Examiner concludes that the word line selected for programming may be the first word line of the block selected for programming)
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Cai to modified Hong wherein the predetermined word line is the first programmed word line in order to reduce write amplification and thereby improve the lifetime of the storage device (Cai, [0060]).
Regarding claim 9, Hong and Cai together disclose the limitations of claim 7. Further, through Cai:
wherein the predetermined word line ([0054]; [0069]; [0079]; [0072]) is determined based on an error correction level ([0058]: when the worst wordline (i.e. the wordline with most disturbed bits) in a block accumulates enough errors that could cause potential uncorrectable (by the ECC) error for the next read disturb check, all valid data in the block can be copied to a new free block).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Cai to modified Hong wherein the predetermined word line is determined based on an error correction level in order to reduce write amplification and thereby improve the lifetime of the storage device (Cai, [0060]).
Regarding claim 11, Hong and Cai together disclose the limitations of claim 7. Further, through Cai:
wherein the threshold value changes according to a program-erase cycle ([0073]: determining that the condition associated with the first sub-block is satisfied can include determining one or more errors associated with the first sub-block, and determining that the one or more errors associated with the first sub-block exceed a threshold value…the one or more errors associated with the first sub-block can be caused by a loss of data retention, for example, through P/E cycling as explained above; [0075]: In some embodiments, the determining that the condition associated with the first sub-block is satisfied can include determining a number of programming or P/E cycles associated with the first sub-block. The number of cycles associated with the first sub-block can be based on the number of cycles it takes for the first sub-block to reach an estimated number of errors. Such an estimated number of errors can be calculated based on the number of errors an Error Correction Code (ECC) at the flash memory controller can handle and/or fix. Examiner concludes that the P/E cycling can affect the threshold value for the maximum number of error bits).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Cai to modified Hong wherein the threshold value changes according to a program-erase cycle in order to reduce write amplification and thereby improve the lifetime of the storage device (Cai, [0060]).
Regarding claim 14, Hong discloses the limitations of claim 13. Except for “concurrently erase,” Claim 14 recites substantially the same limitations as claim 2, and is thus rejected for the same reasons. Further, through Hong:
concurrently erase the first to third memory sub-blocks ([0029]: Each or one or more of the memory blocks BLK1 to BLKz may form an erase unit of the nonvolatile memory device 110; [0075]: The nonvolatile memory device 110 may receive an erase command and an address from the controller 120 to erase data in a storage space identified by the address. Examiner concludes that since a block may be an erase unit, multiple sub-blocks may be erased concurrently, and that specific sub-blocks, identified by their addresses, may be erased concurrently).
Regarding claim 15, Hong discloses the limitations of claim 13. Claim 15 recites substantially the same limitations as claim 3, and is thus rejected for the same reasons.
Regarding claim 17, Hong discloses the limitations of claim 16. Further, through Hong:
wherein the memory controller (Fig. 1: 120) is configured to reclaim ([0074]) the first memory sub-block to the third memory sub-block ([0062]: it is assumed that the UECC has occurred in data written into a page of the second word line WL2a of the first block BLK1. In this case, data of the second word line WL2a where the UECC has occurred may be written to the eighth word line WL8b of the second block BLK2. Examiner concludes that one sub-block of a block may be reclaimed to another sub-block of a different block) when the second memory sub-block is the not-used sub-block.
Hong does not explicitly disclose:
reclaim the first memory sub-block to the third memory sub-block when the second memory sub-block is the not-used sub-block.
However, Cai teaches:
reclaim the first memory sub-block to the third memory sub-block when the second memory sub-block is the not-used sub-block ([0116]: When a block is partially recycled, for example when the first sub-block of a memory block has been reclaimed but the second sub-block has not been reclaimed; [0028]: many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. Examiner concludes that a first sub-block may be reclaimed while a second sub-block is not, and programming and reclaim can happen in parallel, so it is possible for the second sub-block to be unused or open while the first sub-block is reclaimed to a sub-block in another block).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Cai to modified Hong wherein the first memory sub-block is reclaimed to the third memory sub-block when the second memory sub-block is the not-used sub-block in order to reduce write amplification and thereby improve the lifetime of the storage device (Cai, [0060]).
Regarding claim 18, Hong discloses the limitations of claim 16. Aside from reclaiming two sub-blocks instead of three sub-blocks, Claim 18 recites substantially the same limitations as claims 2 and 14, and is thus rejected for the same reasons.
Regarding claim 19, Hong discloses the limitations of claim 16. Aside from reclaiming two sub-blocks instead of three sub-blocks, Claim 19 recites substantially the same limitations as claims 3 and 15, and is thus rejected for the same reasons.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hong (US Pub. 20210249085 A1) and Cai (US Pub. 20170132125 A1) as applied to claim 7 above, and further in view of Sehgal et al. (US Pat. 10573397 B1; “Sehgal”).
Regarding claim 10, Hong and Cai together disclose the limitations of claim 7. Hong discloses:
a height of the word line where an uncorrectable error (UECC) occurs in the first memory sub-block (in reference to Fig. 8, per [0064]: For example, it is assumed that the UECC has occurred in data written into a page of the second word line WL2a of the first block BLK1).
Also, Cai teaches determining a predetermined word line ([0054]; [0058]; [0069]; [0079]; [0072]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Cai to modified Hong wherein a predetermined word line is determined in order to reduce write amplification and thereby improve the lifetime of the storage device (Cai, [0060]).
Neither Hong nor Cai explicitly disclose:
wherein the predetermined word line is determined according to a height of the word line where an uncorrectable error (UECC) occurs in the first memory sub-block.
However, Sehgal teaches:
wherein the predetermined word line is determined according to a height of the word line where an uncorrectable error (UECC) occurs in the first memory sub-block (in reference to Figs. 14 & 17, per col. 24, lines 22-32: a higher incidence of error for word lines along the lower word lines of a word line group. For example, for over-programmed S3 states, this will correspond to the middle pages of such word lines having a higher BER. To this end, at step 1707 additional pages of data are read from the block containing the page found to have a high BER at step 1705. This can include reading all of the pages from all of the word lines of the block, or subset of these pages; for example, only particular pages (e.g., the middle page), only particular word lines (such as on word line group boundaries), or both can be read. Examiner concludes that a predetermined word line, which will be assessed for its error level, is determined according to its location within a block).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Sehgal to modified Hong wherein the predetermined word line is determined according to a height of the word line where an uncorrectable error (UECC) occurs in the first memory sub-block in order to monitor error rates across a device and dynamically adjust programming parameters to mitigate errors (Sehgal, col. 3, lines 25-45).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hong (US Pub. 20210249085 A1) and Cai (US Pub. 20170132125 A1) as applied to claim 7 above, and further in view of Tuers et al. (US Pub. 20160148708 A1; “Tuers”).
Regarding claim 12, Hong and Cai together disclose the limitations of claim 7. Cai discloses:
the threshold value varies ([0073])
the using sub-block or the not-used sub-block ([0056]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Cai to modified Hong wherein the threshold value varies, and the using sub-block or the not-used sub-block exist in order to reduce write amplification and thereby improve the lifetime of the storage device (Cai, [0060]).
Neither Hong nor Cai explicitly disclose:
wherein the threshold value varies depending on whether the second memory sub-block is the using sub-block or the not-used sub-block.
However, Tuers teaches:
wherein the threshold value varies depending on whether the second memory sub-block is the using sub-block or the not-used sub-block ([0079]: Data from a physical unit may have a high error rate for a number of reasons. Some high error rates result from transient conditions so that the next time the block is used (i.e. after the block is erased and new data is written) the physical unit may no longer have a high error rate. Examiner concludes that a “using” sub-block, which according to para. [0075] of the Specification of the present application is a sub-block that is at least partially programmed, may have a low error rate if it has been previously erased).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Tuers to modified Hong wherein the threshold value varies depending on whether the second memory sub-block is the using sub-block or the not-used sub-block in order to improve block operation by detecting physical areas that are prone to persistent errors (Tuers, [0008]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kim et al. (US Pub. 20230036616 A1): paras. [0085]-[0086], and [0088]-[0089], and Figs. 9 and 10 are relevant to claims 1, 13, and 16.
Park et al. (US Pub. 20170160934 A1): paras. [0089], [0110], and [0122], and Figs. 8, 11, and 16 are relevant to claims 1, 13, and 16.
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/Khamdan N. Alrobaie/ Primary Examiner, Art Unit 2824
/E.R.A./Examiner, Art Unit 2824
4/3/2026