DETAILED ACTION
This correspondence is in response to the communications received 03/09/2026. Claims 9 and 10 have been added. Claims 1, 3, 5, 7, and 8 have been amended. Claims 1-10 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment to claim 5 overcomes the objections outlined in the previous Office Action. The objections are withdrawn.
Applicant’s amendment to 8 overcomes the objection outlined in the previous Office Action. The objection is withdrawn.
Applicant’s amendments to claims 3 and 7 overcome the 112(a) rejection outlined in the previous Office Action. The rejection is withdrawn.
Response to Arguments
Applicant’s arguments with respect to independent claims 1 and 5 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, a method of manufacturing a silicon carbide semiconductor device ("silicon carbide SJ-MOSFET 300"), the method comprising:
preparing a silicon carbide semiconductor substrate of a first conductivity type ("n+-type silicon carbide substrate 1"), the silicon carbide semiconductor substrate having a first surface (upper surface of 1 as seen in Fig. 1) and a second surface (lower surface of 1 as seen in Fig. 1) opposite to each other (the upper and lower surfaces of 1 are opposite to each other);
forming a first semiconductor layer of the first conductivity type ("n--type drift layer 2") at the first surface of the silicon carbide semiconductor substrate (as seen in Fig. 1, 2 is at the first surface of 1), the first semiconductor layer having a first surface (upper surface of 2 as seen in Fig. 1) and a second surface (lower surface of 2 as seen in Fig. 1) opposite to each other (the upper and lower surfaces of 2 are opposite to each other), the second surface of the first semiconductor layer facing the first surface of the silicon carbide semiconductor substrate (the lower surface of 2 is facing the upper surface of 1);
inducing damage to a crystal structure of a target region in the first semiconductor layer, the target region being in a surface layer of the first semiconductor layer at the first surface thereof, and located at a depth of more than 3.0 µm from the first surface of the first semiconductor layer (see [0037]); and
after the inducing damage to the crystal structure, ion-implanting a dopant of a second conductivity type into the surface layer of the first semiconductor layer where the crystal structure is damaged, thereby, forming a plurality of column regions of the second conductivity type in the first semiconductor layer ("first p-type column regions 30-1").
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-6, and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et al. (US 20210183995 A1) in view of Domae (US 7,544,549 B2) in view of Schulze et al. (US 10,903,078 B2).
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Regarding claim 1, Figs. 1-8 of Kobayashi disclose a method of manufacturing a silicon carbide semiconductor device (“silicon carbide SJ-MOSFET 300”, [0032], see title), the method comprising:
preparing a silicon carbide semiconductor substrate of a first conductivity type (“First, the n+-type silicon carbide substrate 1 containing an n-type silicon carbide is prepared”, [0044]) the silicon carbide semiconductor substrate having a first surface (the upper surface of 1 as seen in Fig. 1 is a first surface) and a second surface (the lower surface of 1 as seen in Fig. 1 is a second surface) opposite to each other (as seen in Fig. 1, the upper and lower surfaces of 1 are opposite to each other);
forming a first semiconductor layer of the first conductivity type (“on a first main surface of the n+-type silicon carbide substrate 1, while an n-type impurity, for example, nitrogen atoms, is doped, the n−-type drift layer 2 containing silicon carbide is epitaxially grown”, [0044]) at the first surface of the silicon carbide semiconductor substrate (as seen in Fig. 1, 2 is at the first surface of 1), the first semiconductor layer having a first surface (the upper surface of 2 as seen in Fig. 1 is a first surface) and a second surface (the lower surface of 2 as seen in Fig. 1 is a second surface) opposite to each other (as seen in Fig. 1, the upper and lower surfaces of 2 are opposite to each other), the second surface of the first semiconductor layer facing the first surface of the silicon carbide semiconductor substrate (as seen in Fig. 1, the lower surface of 2 is facing the upper surface of 1);
after the inducing damage to the crystal structure (Kobayashi does not disclose inducing damage to the crystal structure, a secondary reference will be used to teach this limitation below), ion-implanting a dopant of a second conductivity type (“Subsequently, a p-type impurity such as aluminum is implanted through the openings of the oxide film, thereby forming first p-type column regions 30-1”, [0045]) into the surface layer of the first semiconductor layer (as seen in Fig. 6, 30-1 is formed into the surface layer of 2) where the crystal structure is damaged (this limitation is also taught by the secondary reference), thereby, forming a plurality of column regions of the second conductivity type in the first semiconductor layer (as seen in Fig. 6, 30-1 is a plurality of column regions of a second conductivity type in 2, where as seen in Fig. 2, 30-1 is only the bottom most portion of “p-type column regions 30”, [0034]).
Kobayashi fails to disclose “inducing damage to a crystal structure of a target region in the first semiconductor layer, the target region being in a surface layer of the first semiconductor layer at the first surface thereof, and located at a depth of more than 3.0 µm from the first surface of the first semiconductor layer; and
after the inducing damage to the crystal structure, ion-implanting a dopant of a second conductivity type into the surface layer of the first semiconductor layer where the crystal structure is damaged.”
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However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 1-7 of Domae teach inducing damage to a crystal structure of a target region in the first semiconductor layer (“Ar+ ions are ion-implanted in the device forming area 18 vertically to the substrate 12”, col. 11, lines 6 and 7, where “Each Ar ion-implanted region 28 is a region in which a crystal defect derived from the ion implantation of Ar exists in the device forming area 18”, col. 9, lines 13-15, and 18 of Domae is equivalent to 2 of Kobayashi. The crystal defects constitute damage to the crystal structure. Further “the ion implantation of Ar is effected on the source forming predeterminate area 20' and the drain forming predeterminate area 22'”, col. 11, lines 10-12, where 20’ and 22’ of Domae are target regions equivalent to 30 of Kobayashi including 30-1.), the target region being in a surface layer of the first semiconductor layer at the first surface (as seen in Fig. 6 of Kobayashi, 30-1 which is an instance of 30 is in a surface layer of 2 at the upper surface of 2); and
after the inducing damage to the crystal structure, ion-implanting a dopant of a second conductivity type into the surface layer of the first semiconductor layer where the crystal structure is damaged (as seen in Fig. 4(c), 20’ and 22’ are formed in 28).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “inducing damage to a crystal structure of a target region in the first semiconductor layer, the target region being in a surface layer of the first semiconductor layer at the first surface thereof; and
after the inducing damage to the crystal structure, ion-implanting a dopant of a second conductivity type into the surface layer of the first semiconductor layer where the crystal structure is damaged” as taught by Domae in the system of Kobayashi for the purpose of mitigating floating body effects such as single latch up (“in order to solve these problems with the floating body effects, there has been known a prior art wherein Ar ions or the like are implanted in a source region and a drain region to artificially form crystal defects in a silicon semiconductor layer, and the crystal defects are constituted as recombination centers of holes”, col. 1, lines 48-55).
Kobayashi in combination with Domae fails to disclose “the target region being in a surface layer of the first semiconductor layer at the first surface thereof, and located at a depth of more than 3.0 µm from the first surface of the first semiconductor layer”.
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However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 7a-7h of Schulze teach the target region being in a surface layer of the first semiconductor layer at the first surface thereof, and located at a depth of more than 3.0 µm from the first surface of the first semiconductor layer (“Ions may be implanted into the silicon carbide wafer 300 with a very high dose to generate sub-surface amorphization/supersaturation, e.g. in a sub-surface region 312, as shown in FIG. 7a. The implantation may be performed with a high dose into a depth of e.g. 0.5-5 μm”, col. 22, lines 41-46).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “the target region being in a surface layer of the first semiconductor layer at the first surface thereof, and located at a depth of more than 3.0 µm from the first surface of the first semiconductor layer” as taught by Schulze in the system of Kobayashi in combination with Domae for the purpose of maximizing the size of the source and drain regions of Domae to further increase the number of recombination centers.
Regarding claim 2, Figs. 1-8 of Kobayashi in combination with Figs. 1-7 of Domae and Figs. 7a-7h of Schulze disclose the method according to claim 1, Figs. 1-7 of Domae further disclose wherein the inducing damage to the crystal structure includes implanting ions of neon, argon, krypton, or xenon into the target region in the surface layer (as mentioned above, “Ar ion-implanted region 28 is a region in which a crystal defect derived from the ion implantation of Ar”, col. 9, lines 13-14).
Regarding claim 4, Figs. 1-8 of Kobayashi in combination with Figs. 1-7 of Domae and Figs. 7a-7h of Schulze disclose the method according to claim 1, Figs. 1-8 of Kobayashi further disclose wherein each of the plurality of column regions has a thickness of 1.0 μm or more (“A depth of the p-type column regions 30 may be in a range from 3 μm to 10 μm for a breakdown voltage of 1200V, in a range from 5 μm to 15 μm for a breakdown voltage of 1700V, and in a range from 10 μm to 30 μm for a breakdown voltage of 3300V”, [0038]).
Regarding claim 5, Figs. 1-8 of Kobayashi disclose a method of manufacturing a silicon carbide semiconductor device (“silicon carbide SJ-MOSFET 300”, [0032], see title), the method comprising:
preparing a silicon carbide semiconductor substrate of a first conductivity type (“First, the n+-type silicon carbide substrate 1 containing an n-type silicon carbide is prepared”, [0044]) the silicon carbide semiconductor substrate having a first surface (the upper surface of 1 as seen in Fig. 1 is a first surface) and a second surface (the lower surface of 1 as seen in Fig. 1 is a second surface) opposite to each other (as seen in Fig. 1, the upper and lower surfaces of 1 are opposite to each other);
forming a semiconductor layer (“on a first main surface of the n+-type silicon carbide substrate 1, while an n-type impurity, for example, nitrogen atoms, is doped, the n−-type drift layer 2 containing silicon carbide is epitaxially grown”, [0044]) with a parallel pn region (as seen in Fig. 1, 2 has a parallel pn region formed by “p-type column regions 30”, [0034], and “n-type column regions 31”, [0034]) on the first surface of the silicon carbide semiconductor substrate (as seen in Fig. 1, 2 is at the first surface of 1), including
forming a first semiconductor layer of the first conductivity type (2 is a first semiconductor layer that is n-type) at the first surface of the silicon carbide semiconductor substrate (as seen in Fig. 1, 2 is at the first surface of 1), the first semiconductor layer having a first surface (the upper surface of 2 as seen in Fig. 1 is a first surface) and a second surface (the lower surface of 2 as seen in Fig. 1 is a second surface) opposite to each other (as seen in Fig. 1, the upper and lower surfaces of 2 are opposite to each other), the second surface of the first semiconductor layer facing the first surface of the silicon carbide semiconductor substrate (as seen in Fig. 1, the lower surface of 2 is facing the upper surface of 1); and
forming in the first semiconductor layer, at the first surface thereof, the parallel pn region in which a plurality of first column regions of the first conductivity type (31 is a plurality of first column regions of the first conductivity type) and a plurality of second column regions of a second conductivity type (30 are a plurality of second column regions of a second conductivity type, where “the p-type column regions 30 are formed by ion implantation”, [0041], and as seen in Fig. 1, 31 and 30 are formed in 2 at the upper surface thereof as a parallel pn region) are disposed repeatedly alternating with one another in a plane parallel to the first surface of the first semiconductor layer (as seen in Fig. 1, 31 and 30 are disposed repeatedly alternating with one another in a plane parallel to the upper surface of 2), the parallel pn region having a first surface (the upper surface of 31 as seen in Fig. 1 is a first surface) and a second surface (the lower surface of 31 as seen in Fig. 1 is a second surface) opposite to each other (as seen in Fig. 1, the upper and lower surfaces of 31 are opposite to each other), the second surface of the parallel pn region facing the second surface of the first semiconductor layer (as seen in Fig. 1, the lower surface of 31 is facing the lower surface of 2);
forming a second semiconductor layer of the second conductivity type at the first surface of the parallel pn region (“on the surfaces of the n-type column regions 31 and the p-type column regions 30, the p−-type base regions 16 doped with a p-type impurity such as aluminum are formed”, [0049], wherein the surfaces of 31 and 30 are the upper surfaces);
selectively forming a first semiconductor region (“n+-type source regions 17”, [0036]) of the first conductivity type in the second semiconductor layer (“on the surfaces of the p−-type base regions 16, an ion implantation mask having predetermined openings is formed by photolithography using, for example, an oxide film. An n-type impurity such as phosphorus (P) is ion-implanted through the openings, thereby forming the n+-type source regions 17 in portions of the p−-type base regions 16”, [0049]), the first semiconductor region having a doping concentration higher than a doping concentration of the first semiconductor layer (as mentioned previously, 17 is denoted as “n+-type” whereas 2 is denoted as “n--type” therefore it is known in the art that 17 has a doping concentration higher than a doping concentration of 2);
forming a trench (“trenches 23 that penetrate the p−-type base regions 16 and reach the n-type column regions 31 are formed by dry etching”, [0051]) that penetrates through the first semiconductor region and the second semiconductor layer and reaches the parallel pn region (as seen in Fig. 1, 23 penetrates through 17 and 16 and reaches 31 of the parallel pn region);
forming a gate electrode in the trench via a gate insulating film (“on the gate insulating films 19, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided. The polycrystalline silicon layer may be formed so as to be embedded in the trenches 23. The polycrystalline silicon layer is patterned by photolithography to be left in the trenches 23, thereby forming the gate electrodes 20”, [0053]); and
forming a first electrode (“a p-type impurity such as aluminum is ion-implanted in portions of the p−-type base regions 16, at the surfaces thereof, whereby the p++-type contact regions 18 are provided”, [0049], as seen in Fig. 1, 18 is an electrode connected to 30) in contact with the first semiconductor region and the second semiconductor layer (as seen in Fig. 1, 18 is in contact with 17 and 16), wherein
the forming the semiconductor layer with the parallel pn region includes
forming the first semiconductor layer of the first conductivity type by epitaxial growth (“the n−-type drift layer 2 containing silicon carbide is epitaxially grown”, [0044]),
after the inducing damage to the crystal structure (Kobayashi does not disclose inducing damage to the crystal structure, a secondary reference will be used to teach this limitation below), ion-implanting a dopant of the second conductivity type (“Subsequently, a p-type impurity such as aluminum is implanted through the openings of the oxide film, thereby forming first p-type column regions 30-1”, [0045]) into the surface layer of the first semiconductor layer (as seen in Fig. 6, 30-1 is formed into the surface layer of 2) where the crystal structure is damaged (this limitation is also taught by the secondary reference), thereby, forming the plurality of second column regions of the second conductivity type in the first semiconductor layer (as seen in Fig. 6, 30-1 is a plurality of column regions of a second conductivity type in 2, where as seen in Fig. 2, 30-1 is only the bottom most portion of “p-type column regions 30”).
Figs. 1-8 of Kobayashi fail to disclose “the forming the semiconductor layer with the parallel pn region includes
inducing damage to a crystal structure of a target region in the first semiconductor layer, the target region being in a surface layer of the first semiconductor layer at the first surface thereof, and located at a depth of more than 3.0 µm from the first surface of the first semiconductor layer, and
after the inducing damage to the crystal structure, ion-implanting a dopant of the second conductivity type into the surface layer of the first semiconductor layer where the crystal structure is damaged”.
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 1-7 of Domae teach forming the semiconductor layer with the parallel pn region includes
inducing damage to a crystal structure of a target region of the first semiconductor layer (“Ar+ ions are ion-implanted in the device forming area 18 vertically to the substrate 12”, col. 11, lines 6 and 7, where “Each Ar ion-implanted region 28 is a region in which a crystal defect derived from the ion implantation of Ar exists in the device forming area 18”, col. 9, lines 13-15, and 18 of Domae is equivalent to 2 of Kobayashi. The crystal defects constitute damage to the crystal structure. Further “the ion implantation of Ar is effected on the source forming predeterminate area 20' and the drain forming predeterminate area 22'”, col. 11, lines 10-12, where 20’ and 22’ of Domae are target regions equivalent to 30 of Kobayashi including 30-1.), the target region being in a surface layer of the first semiconductor layer at the first surface (as seen in Fig. 6 of Kobayashi, 30-1 which is an instance of 30 is in a surface layer of 2 at the upper surface of 2); and
after the inducing damage to the crystal structure, ion-implanting a dopant of the second conductivity type into the surface layer of the first semiconductor layer where the crystal structure is damaged (as seen in Fig. 4(c), 20’ and 22’ are formed in 28).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “inducing damage to a crystal structure of a target region of the first semiconductor layer, the target region being in a surface layer of the first semiconductor layer at the first surface thereof; and
after the inducing damage to the crystal structure, ion-implanting a dopant of the second conductivity type into the surface layer of the first semiconductor layer where the crystal structure is damaged” as taught by Domae in the system of Kobayashi for the purpose of mitigating floating body effects such as single latch up (“in order to solve these problems with the floating body effects, there has been known a prior art wherein Ar ions or the like are implanted in a source region and a drain region to artificially form crystal defects in a silicon semiconductor layer, and the crystal defects are constituted as recombination centers of holes”, col. 1, lines 48-55).
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 7a-7h of Schulze teach the target region being in a surface layer of the first semiconductor layer at the first surface thereof, and located at a depth of more than 3.0 µm from the first surface of the first semiconductor layer (“Ions may be implanted into the silicon carbide wafer 300 with a very high dose to generate sub-surface amorphization/supersaturation, e.g. in a sub-surface region 312, as shown in FIG. 7a. The implantation may be performed with a high dose into a depth of e.g. 0.5-5 μm”, col. 22, lines 41-46).
Kobayashi in combination with Domae fails to disclose “the target region being in a surface layer of the first semiconductor layer at the first surface thereof, and located at a depth of more than 3.0 µm from the first surface of the first semiconductor layer”.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “the target region being in a surface layer of the first semiconductor layer at the first surface thereof, and located at a depth of more than 3.0 µm from the first surface of the first semiconductor layer” as taught by Schulze in the system of Kobayashi in combination with Domae for the purpose of maximizing the size of the source and drain regions of Domae to further increase the number of recombination centers.
Figs. 1-8 of Kobayashi further disclose the forming the first semiconductor layer, the inducing damage and the ion-implanting are performed one or more times (as discussed above, the process is performed at least once, further “while the processes of the ion implantation to the epitaxial growth are repeatedly performed 8 times, this number is dependent on the film thicknesses of the parallel pn structures 33, the acceleration energy of the ion implantations, etc. and therefore, may be another number”, [0048], this repetition would also include the Ar+ ion-implantation taught by Domae in order to incorporate the previously discussed benefits in each layer of 2).
Regarding claim 6, Figs. 1-8 of Kobayashi in combination with Figs. 1-7 of Domae and Figs. 7a-7h of Schulze disclose the method according to claim 5, Figs. 1-7 of Domae further disclose wherein the inducing damage to the crystal structure includes implanting ions of neon, argon, krypton, or xenon into the target region in the surface layer (as mentioned above, “Ar ion-implanted region 28 is a region in which a crystal defect derived from the ion implantation of Ar”, col. 9, lines 13-14).
Regarding claim 8, Figs. 1-8 of Kobayashi in combination with Figs. 1-7 of Domae and Figs. 7a-7h of Schulze disclose the method according to claim 5, Figs. 1-8 of Kobayashi further disclose wherein each of the plurality of second column regions has a thickness of 1.0 μm or more (“A depth of the p-type column regions 30 may be in a range from 3 μm to 10 μm for a breakdown voltage of 1200V, in a range from 5 μm to 15 μm for a breakdown voltage of 1700V, and in a range from 10 μm to 30 μm for a breakdown voltage of 3300V”, [0038]).
Regarding claim 9, Figs. 1-8 of Kobayashi in combination with Figs. 1-7 of Domae and Figs. 7a-7h of Schulze disclose the method according to claim 1, Figs. 7a-7h of Schulze further disclose wherein the target region is located at a depth of 4.0µm or more from the first surface of the first semiconductor layer (as discussed previously, Schulze discloses that ion implantation and amorphization can take place down to a depth of 5 µm).
Regarding claim 10, Figs. 1-8 of Kobayashi in combination with Figs. 1-7 of Domae and Figs. 7a-7h of Schulze disclose the method according to claim 5, Figs. 7a-7h of Schulze further disclose wherein the target region is located at a depth of 4.0µm or more from the first surface of the first semiconductor layer (as discussed previously, Schulze discloses that ion implantation and amorphization can take place down to a depth of 5 µm).
Claims 3 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et al. (US 20210183995 A1) in view of Domae (US 7,544,549 B2) in view of Schulze et al. (US 10,903,078 B2) in view of Iguchi et al. (US 10,727,060 B2).
Regarding claim 3, Figs. 1-8 of Kobayashi in combination with Figs. 1-7 of Domae and Figs. 7a-7h of Schulze disclose the method according to claim 1.
Kobayashi in combination with Domae and Schulze fails to disclose “further comprising:
after the ion-implanting the dopant in the surface of the first semiconductor layer, performing a heat treatment to fully recover the damaged crystal structure, wherein
the target region has an extent where a 4H-SiC crystal structure therein is recoverable by an activation annealing treatment for the dopant ions implanted.”
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 1-14 of Iguchi teach further comprising:
after the ion-implanting the dopant in the surface of the first semiconductor layer, performing a heat treatment to fully recover the damaged crystal structure (“A wide band gap semiconductor or an insulator, such as SiC, particularly 4H-SiC, has a small diffusion coefficient of an impurity atom (dopant). For example, when the semiconductor substrate is 4H-SiC, a high dose ions of about 1015 per square centimeter or more is implanted to the (0001) plane (or (000-1) plane) of 4H-SiC. In such case, in order to enhance activation of the impurity atoms together with recrystallization of the 4H-SiC, the semiconductor substrate is heated to a temperature range of 300° C. to 800° C. during ion implantation, and after the ion implantation, it is necessary to anneal the semiconductor substrate in a high temperature range of 1600° C. to 1800° C”, col. 1, lines 26-37, thus Iguchi teaches that 4H-SiC is a suitable wide band gap semiconductor, and that an annealing process to active impurity ions can cause recrystallization of 4H-SiC, thereby recovering its original crystal structure), wherein
the target region has an extent where a 4H-SiC crystal structure therein is recoverable by the heat treatment for the dopant ions implanted (as discussed above, Iguchi teaches that the 4H-SiC crystal structure is recoverable a heat treatment to activate impurity ions).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “further comprising:
after the ion-implanting the dopant in the surface of the first semiconductor layer, performing a heat treatment to fully recover the damaged crystal structure, wherein
the target region has an extent where a 4H-SiC crystal structure therein is recoverable by an activation annealing treatment for the dopant ions implanted” as taught by Iguchi in the system of Kobayashi in combination with Domae and Schulze for the purpose of mitigating crystal structure damage caused during device processing.
Regarding claim 7, Figs. 1-8 of Kobayashi in combination with Figs. 1-7 of Domae and Figs. 7a-7h of Schulze disclose the method according to claim 5, Figs. 1-8 of Kobayashi further disclose further comprising:
after the forming the first semiconductor region and before the forming the trench, performing a heat treatment (as seen in [0046], 2 is first formed, then in [0050], a heat treatment is performed as an activation process, lastly in [0051], 23 are formed, thus after forming 2 and before forming 23, a heat treatment is performed).
Kobayashi in combination with Domae and Schulze fails to disclose “performing a heat treatment to fully recover the damaged crystal structure, wherein
the target region has an extent where a 4H-SiC crystal structure therein is recoverable by the heat treatment for the dopant ions implanted.”
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 1-14 of Iguchi teach performing a heat treatment to fully recover the damaged crystal structure (“A wide band gap semiconductor or an insulator, such as SiC, particularly 4H-SiC, has a small diffusion coefficient of an impurity atom (dopant). For example, when the semiconductor substrate is 4H-SiC, a high dose ions of about 1015 per square centimeter or more is implanted to the (0001) plane (or (000-1) plane) of 4H-SiC. In such case, in order to enhance activation of the impurity atoms together with recrystallization of the 4H-SiC, the semiconductor substrate is heated to a temperature range of 300° C. to 800° C. during ion implantation, and after the ion implantation, it is necessary to anneal the semiconductor substrate in a high temperature range of 1600° C. to 1800° C”, col. 1, lines 26-37, thus Iguchi teaches that 4H-SiC is a suitable wide band gap semiconductor, and that an annealing process to active impurity ions can cause recrystallization of 4H-SiC, thereby recovering its original crystal structure, further the heat treatment of Iguchi can be substituted for the heat treatment of Kobayashi), wherein
the target region has an extent where a 4H-SiC crystal structure therein is recoverable by the heat treatment for the dopant ions implanted (as discussed above, Iguchi teaches that the 4H-SiC crystal structure is recoverable a heat treatment to activate impurity ions).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “performing a heat treatment to fully recover the damaged crystal structure, wherein
the target region has an extent where a 4H-SiC crystal structure therein is recoverable by the heat treatment for the dopant ions implanted” as taught by Iguchi in the system of Kobayashi in combination with Domae and Schulze for the purpose of mitigating crystal structure damage caused during device processing.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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