Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed February 5, 2026.
Status of claims to be treated in this office action:
a. Independent: 1, 8, 15
b. Pending: 1-20
Claims 1, 4, 8, 11, 15, and 18 have been amended.
Specification
The new title has been reviewed and accepted by the Examiner. The amendments to the Specification have been reviewed and are accepted by the Examiner. The objections to the Specification are withdrawn.
Response to Arguments
Applicant’s arguments with respect to claims 1-5, 7-12, and 14-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. New grounds of rejection are made in view of Kim et al. (US Pub. 20180218775 A1; “Kim”). Kim teaches a plurality of loops, a verify cycle after the program cycle, a verify cycle comprising multiple intervals or periods, turning off the DSG transistor in the unselect memory string during both pre- and post-pulse periods of a first loop, and turning on the DSG transistor during the pre-pulse period of a second loop in Figs. 7 and 17, and paras. [0034]-[0035].
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-11, and 13-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Kim (US Pub. 20180218775 A1).
Regarding independent claim 1, Kim discloses a memory device (Fig. 1: memory device 20; [0030]), comprising:
memory strings (Fig. 3: strings CSTRs; [0051]) each comprising a drain select gate (DSG) transistor (string select transistor SST; [0051]), memory cells (Memory cell transistors MCTs; [0051]), and a source select gate (SSG) transistor (ground select transistor GST; [0051]); and
a peripheral circuit (Fig. 2: voltage generator 140, row decoder 150, control logic 110, page buffer circuit 120, and data I/O circuit 130) coupled to the memory strings and configured to, in a program operation, program a select memory cell of the memory cells in a select memory string of the memory strings ([0006]: The method comprises performing a program operation to program a first memory cell of a selected memory cell string which is coupled to a bit line through a first string select transistor), and inhibit an unselect memory cell of the memory cells in an unselect memory string of the memory strings ([0043]: The inhibition string is a string in which programming operation is inhibited. Hereinafter, the inhibition string is also referred to as “unselected memory cell string.”), the program operation comprising a plurality of loops, a loop of the plurality of the loops comprising a program cycle and a verify cycle after the program cycle, the verify cycle comprising a pre-pulse period, a verify period after the pre-pulse period, and a post- pulse period after the verify period ([0034]: when a plurality of program loops for programming data to the memory cells of the memory cell array 22 are performed… The program loop may include a program interval, at which a program voltage is applied to the selected memory cells, and a verification interval, at which a verification voltage is applied to the selected memory cells to confirm a programming state of the selected memory cells, and a pre-pulse interval, at which a pre-pulse operation is performed, may be further included in the program loop in addition to the program interval and the verification interval, or the pre-pulse controller 24 may control a pre-pulse operation so that the pre-pulse interval is included in the verification interval; Fig. 7: first verification interval A is analogous to a pre-pulse period. See annotated screenshot below for Examiner’s identification of the post-pulse period), wherein the peripheral circuit comprises:
a word line driver (Fig. 2: row decoder 150; [0040]) configured to:
in the pre-pulse period and the post-pulse period in the verify cycle of a first loop of the program operation, turn off the DSG transistor in the unselect memory string (per Fig. 17, the Nth Loop in Loop Group_2 does not include a pre-pulse operation; Fig. 7 illustrates the pre-pulse operation; per Figs. 15-16C, there is a determination about whether to perform the pre-pulse operation; [0035]: the pre-pulse controller 24 may set a pre-pulse inhibition loop that does not perform a pre-pulse operation among the program loops. Examiner concludes that there are some program-verify cycles which do not include a voltage pulse on the unselected SSL. Thus, the string select transistor of the unselected memory string, analogous to the “DSG transistor in the unselect memory string”, is turned off); and
in at least one of the pre-pulse period or the post-pulse period in the verify cycle of a second loop of the program operation after the first loop, turn on the DSG transistor in the unselect memory string (per Fig. 17, the N+1 loop in Loop Group_3 includes a pre-pulse operation; Fig. 7 shows that the string select transistor of the unselected memory string is turned on during the first verification interval A, which is analogous to the pre-pulse period).
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Regarding claim 2, Kim discloses the limitations of claim 1, and further through Kim:
wherein the program operation is an incremental step pulse program (ISPP) (Figs. 6, 11A, and 17 show incremental step pulse programming), and the first loop and the second loop are a starting loop and an ending loop of the ISPP, respectively ([0074]: The inventive concept may be applied to a multi level cell (MLC) in which 2-bit or 3-bit or higher data is stored; per claim 10: a plurality of program loops including a Nth (where N is a natural number of 1 or greater) program loop are performed).
Regarding claim 3, Kim discloses the limitations of claim 1, and further through Kim:
wherein the word line driver (Fig. 2: 150) is further configured to:
in the pre-pulse period and the post-pulse period in the first loop of the program operation, turn off the SSG transistor in the unselect memory string (refer to the penultimate limitation of claim 1 and refer to claim 2); and
in the at least one of the pre-pulse period or the post-pulse period in the second loop of the program operation, turn on the SSG transistor in the unselect memory string (refer to the last limitation of claim 1 and refer to claim 2).
Regarding claim 4, Kim discloses the limitations of claim 3, and further through Kim:
wherein the word line driver (Fig. 2: 150) is further configured to:
in the verify period (Fig. 7: second verification interval B; [0059]; [0064]: in the second verification interval B, a BLSHF signal for activating a bit line select transistor may be changed from a low level to a high level…to perform an operation for verifying the data) between the pre-pulse period and the post-pulse period in the first loop of the program operation, turn off the DSG transistor and the SSG transistor in the unselect memory string (per Fig. 7, the Unsel_SSLs & GSLs are at a low voltage during second verification interval B); and
in the verify period between the pre-pulse period and the post-pulse period in the second loop of the program operation, turn off the DSG transistor and the SSG transistor in the unselect memory string (per all timing diagrams that include Unsel_SSLs & GSLs, the voltage is low during the verify period).
Regarding claim 6, Kim discloses the limitations of claim 3, and further through Kim:
wherein the word line driver (Fig. 2: 150) is further configured to:
in the pre-pulse period in the second loop of the program operation (Fig. 17, the N+1 loop in Loop Group_3), turn on the DSG transistor and the SSG transistor in the unselect memory string (per Fig. 7, for those program loops that include the pre-pulse operation, or the turning on of the string select and ground select transistors of the unselected memory string, the turning on occurs during the first verification interval A); and
in the post-pulse period in the second loop of the program operation, turn off the DSG transistor and the SSG transistor in the unselect memory string (as above, Unsel_SSLs & GSLs are otherwise at a low voltage).
Regarding claim 7, Kim discloses the limitations of claim 1, and further through Kim:
wherein the DSG transistor in the select memory string is electrically separated from the DSG transistor in the unselect memory string ([0052]: An unselected memory cell string among the plurality of strings connected to the selected bit line BL<1> may be a string in which the selected bit line BL<1> and the channel are electrically cut off).
Independent claim 8 is mostly the same in claimed subject matter as claim 1 except for being drafted in method format instead of device format, and is thus rejected for the same reasons as independent claim 1.
Independent claim 15 is mostly the same in claimed subject matter as claim 1 except for containing a memory controller and a system that comprises the components claimed in independent claim 1. All but the memory controller and system limitation are thus rejected for the same reasons as independent claim 1.
Kim discloses:
a system (Fig. 1: memory system 1; [0030])
a memory controller (memory controller 10; [0030]) coupled to the memory device and configured to control the memory device ([0031]: the memory controller 10 may control program (or writing), read (or comprehend), and erase (or remove) operations with respect to the memory device 20).
Regarding claims 9 and 16, Kim discloses the limitations of claims 8 and 15, respectively. Claims 9 and 16 recite the exact same limitations as claim 2 and henceforth they are rejected for the same reasons.
Regarding claims 10 and 17, Kim discloses the limitations of claims 8 and 15, respectively. Claim 17 recites the exact same limitations as claim 3 and claim 10 recites substantially the same limitations as claim 3, and henceforth they are rejected for the same reasons.
Regarding claims 11 and 18, Kim discloses the limitations of claims 10 and 17, respectively. Claim 18 recites the exact same limitations as claim 4 and claim 11 recites substantially the same limitations as claim 4, and henceforth they are rejected for the same reasons.
Regarding claim 13, Kim discloses the limitations of claim 10. Claim 13 recites the same limitations as claim 6, and henceforth claim 13 is rejected for the same reasons.
Regarding claims 14 and 19, Kim discloses the limitations of claims 8 and 15, respectively. Claim 19 recites the exact same limitations as claim 7 and claim 14 recites substantially the same limitations as claim 7, and henceforth they are rejected for the same reasons.
Regarding claim 20, Kim discloses the limitations of claim 15, and further through Kim:
wherein the memory device is a NAND Flash memory device ([003]: the plurality of memory cells may be flash memory cells, and the memory cell array 22 may be a NAND flash memory cell array).
Allowable Subject Matter
Claims 5 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Baek et al. (US Pub. 20250069668 A1): paras. [0058] and [0062], and Figs. 7-9 are relevant to claims 1, 8, and 15.
Lee (US Pub. 20210210146 A1): para. [0104] and Figs. 4-5, 7, and 11 are relevant to claims 1, 8, and 15.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.R.A./Examiner, Art Unit 2824
/HAN YANG/Primary Examiner, Art Unit 2824
3/20/2026