DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Pursuant to the election of invention I without traverse on July 6, 2026, claims 16-20 are withdrawn from consideration.
Specification
Paragraph 20 of the specification includes the following: “In addition, and the well region 110 laterally extends around and encircles the finger structures F as shown in FIG. 1A.” This is ungrammatical.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims [] are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a transistor finger structure extending longitudinally along the first direction and including a drain finger having opposite drain finger ends spaced apart from one another along the first direction in the semiconductor layer and including majority carrier dopants of a second type, and source fingers laterally spaced apart from opposite sides of the drain finger along the second direction in the semiconductor layer and including majority carrier dopants of the second type”. It is not clear whether the source fingers are listed along with the drain fingers as part of the transistor finger structure, or if they are listed along with the transistor finger structure.
Claim 1 recites “source fingers laterally spaced apart from opposite sides of the drain finger along the second direction in the semiconductor layer and including majority carrier dopants of the second type; and a well region including majority carrier dopants of the first type in the semiconductor layer, the source fingers extending in respective portions of the well region, and the well region laterally extending around and encircling the finger structure.” Claim 2 recites “the source fingers comprise a second well region extending in the respective portions of the well region, the second well region including majority carrier dopants of the first type in the semiconductor layer, the second well region laterally extending around and encircling the finger structure, and the second well region having an end portion that extends beyond a lateral end of the well region along the first direction.” Thus there are a three elements recited: a source finger of the second conductivity type; a well region of the first type; and a second well region of the first type. These appear to correspond to the source finger S, the well region 110, and the second well region 114. 110 and 114 are of the first type ([0020], [0022]). Looking at FIG. 1, the source finger S appears to identify the source electrode. The specification states at [0018] that “The respective transistor finger structures also include two source fingers S laterally spaced apart from opposite sides of the corresponding drain finger D along the second direction Y in the semiconductor layer 104. The source fingers S includes majority carrier dopants of the second type N.” However, there is no identification of what is the N-doped source finger.
Claims 8 and 10 have the same problem.
Claim 3 recites “the end portion”, which lacks antecedent basis.
The remaining claims are rejected based on their dependencies.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Todd, US 2020/0006550 A1.
Claim 1: Todd discloses
a semiconductor layer (106) having a side extending in a plane of orthogonal first and second directions and including majority carrier dopants of a first type (P, [0010]);
a transistor finger structure extending longitudinally along the first direction (horizontal, FIG. 2) and including a drain finger having opposite drain finger (DRAIN) ends spaced apart from one another along the first direction in the semiconductor layer and including majority carrier dopants of a second type (112, N), and source fingers (SOURCE, FIG. 2) laterally spaced apart from opposite sides of the drain finger along the second direction in the semiconductor layer and including majority carrier dopants of the second type (110, N);
and a well region (108) including majority carrier dopants of the first type (P, FIG. 1) in the semiconductor layer, the source fingers extending in respective portions of the well region, and the well region laterally extending around and encircling the finger structure. Note that the well region 108 is on both sides of FIG. 1, corresponding to the vertical direction of FIG. 2, and on the horizontal end of FIG. 2, as shown in FIG. 3 (as well as the other end that is not shown in that figure.)
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Claim 1 is rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Wang, US 2021/0167205 A1.
Claim 1: Wang discloses
a semiconductor layer (214) having a side extending in a plane of orthogonal first and second directions and including majority carrier dopants of a first type (P, [0017]);
a transistor finger structure extending longitudinally along the first direction (vertical, FIG. 3) and including a drain finger (23oD) having opposite drain finger ends spaced apart from one another along the first direction in the semiconductor layer and including majority carrier dopants of a second type ([0045]), and source fingers (230S) laterally spaced apart from opposite sides of the drain finger along the second direction in the semiconductor layer and including majority carrier dopants of the second type ([0046]);
and a well region (242) including majority carrier dopants of the first type ([0049]) in the semiconductor layer, the source fingers extending in respective portions of the well region, and the well region laterally extending around and encircling the finger structure (FIG. 3).
Claims 1-3m 6m and 7 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Edwards, US 2017/0179260 A1.
Claim 1: Edwards discloses
a semiconductor layer (115) having a side extending in a plane of orthogonal first and second directions and including majority carrier dopants of a first type (p, [0023]);
a transistor finger (FIG. 2B) structure extending longitudinally along the first direction (horizontal, FIG. 2B) and including a drain finger (145) having opposite drain finger ends spaced apart from one another along the first direction in the semiconductor layer and including majority carrier dopants of a second type (“n+ source-p-body-n+ drain”, [0029]), and source fingers (148) laterally spaced apart from opposite sides of the drain finger along the second direction in the semiconductor layer and including majority carrier dopants of the second type ([0035]);
and a well region (130) including majority carrier dopants of the first type ([0026]) in the semiconductor layer, the source fingers extending in respective portions of the well region, and the well region laterally extending around and encircling the finger structure (FIGS. 2A and 2B).
Claim 2: the source fingers comprise a second well region (140) extending in the respective portions of the well region, the second well region including majority carrier dopants of the first type ([0031]) in the semiconductor layer, the second well region laterally extending around and encircling the finger structure, and the second well region having an end portion that extends beyond a lateral end of the well region along the first direction (FIGS. 2A and 2B). As 140 surrounds 148, it will extend beyond it in all directions.
Claim 3: the lateral end of the well region has a first width along the first direction, and the end portion of the second well region is wider than the first width along the first direction (FIG. 3).
Claim 6: Edwards discloses an implanted region (142a) including majority carrier dopants of the first type (p, [0035]: “backgate/body contact region 142a can be formed within the DWELL 130 by adding a p+ SD (PSD) implant”) in a lateral top portion of the second well region spaced apart from the transistor finger structure along the second direction, and a conductive contact (142) extending from the implanted region to a metallization structure (FIG. 3).
Claim 7: a lateral end of the well region has a first width along the first direction, a lateral top portion of the well region has a second width along the second direction, and the first width is greater than the second width (FIG. 2A). As the well region tapers down, it will meet this limitation.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 5, and 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Edwards in view of Birner, US 2017/0373187 A1.
Claim 4: Edwards discloses an implanted region (148) including majority carrier dopants of the first type (“n+ source 148”, [0035]) in the end portion of the second well region, and a conductive contact (143) extending from the implanted region to a metallization structure. The metallization structure is not shown but is mentioned (“metallization processing generally follow” the disclosed manufacturing steps [0033]). Those in the art would have recognized that the contact 142 would lead to the metallization structure. See Birner, FIG. 11, showing metallization structure 160 connected to source drain and gate contacts. This would have been understood to be the arrangement suggested by Edwards.
Claim 5: Edwards discloses a second implanted region (142a) including majority carrier dopants of the first type (p, [0035]: “backgate/body contact region 142a can be formed within the DWELL 130 by adding a p+ SD (PSD) implant”) in a lateral top portion of the second well region spaced apart from the transistor finger structure along the second direction, and a second conductive contact (142) extending from the second implanted region to a metallization structure (FIG. 3).
Claim 8: Edwards discloses
a semiconductor layer (115) having a side extending in a plane of orthogonal first and second directions and including majority carrier dopants of a first type (p, [0023]);
a transistor finger (FIG. 2B) structure extending longitudinally along the first direction (horizontal, FIG. 2B) and including a drain finger (145) having opposite drain finger ends spaced apart from one another along the first direction (horizontal, FIG. 2B) in the semiconductor layer and including majority carrier dopants of a second type (“n+ source-p-body-n+ drain”, [0029]), and source fingers (148) laterally spaced apart from opposite sides of the drain finger along the second direction (vertical, FIG. 2B) in the semiconductor layer and including majority carrier dopants of the second type ([0035]);
a well region (130) including majority carrier dopants of the first type ([0026]) in the semiconductor layer, the second well region laterally extending around and encircling the finger structure (FIGS. 2A and 2B);
an implanted region (142a) including majority carrier dopants of the first type ([0035]) in an end portion of the well region spaced apart from the transistor finger structure along the first direction;
and a conductive contact (142) extending from the implanted region to a metallization structure.
The metallization structure is not shown but is mentioned (“metallization processing generally follow” the disclosed manufacturing steps [0033]). Those in the art would have recognized that the contact 142 would lead to the metallization structure. See Birner, FIG. 11, showing metallization structure 160 connected to source drain and gate contacts. This would have been understood to be the arrangement suggested by Edwards.
Claim 9 discloses a second implanted region including majority carrier dopants of the first type in a lateral top portion of the well region spaced apart from the transistor finger structure along the second direction, and a second conductive contact extending from the second implanted region to a metallization structure.
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Claim 10: the source fingers extend in respective portions of a second well region (140) including majority carrier dopants of the first type in the semiconductor layer.
Claim 11: the second well region extends into the semiconductor layer along a third direction (vertical) that is orthogonal to the first and second directions, and the second well region is deeper than the well region along the third direction (FIG. 3).
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Edwards in view of Birner, and Mun, US 2023/0059226 A1.
Claim 12: Edwards does not disclose a deep trench isolation structure. Mun discloses a deep trench isolation structure (18) laterally surrounding the transistor finger structure in the semiconductor layer (FIG. 4), the deep trench isolation structure extending through the semiconductor layer to a semiconductor substrate along a third direction (vertical) that is orthogonal to the first and second directions (FIG. 7A), and the deep trench isolation structure laterally spaced apart from the well region along the first direction (well 38 and/or 40 of Mun would correspond to the well 130 of Edwards). It would have been obvious to have had such a structure in Edwards in order to electrically isolate and protect the device (Mun [0026]).
Claim 13: in Edwards in view of Mun, the deep trench isolation structure is adjacent to a portion of the well region along the second direction (Mun FIG. 7A).
Claim 14: a second implanted region (142a) including majority carrier dopants of the first type ([0035]) in a lateral top portion of the well region spaced apart from the transistor finger structure along the second direction, and a second conductive contact extending from the second implanted region to a metallization structure.
The metallization structure is not shown but is mentioned (“metallization processing generally follow” the disclosed manufacturing steps [0033]). Those in the art would have recognized that the contact 142 would lead to the metallization structure. See Birner, FIG. 11, showing metallization structure 160 connected to contacts. This would have been understood to be the arrangement suggested by Edwards.
Claim 15: a second implanted region (142a) including majority carrier dopants of the first type ([0035]) in a lateral top portion of the well region spaced apart from the transistor finger structure along the second direction, and a second conductive contact extending from the second implanted region to a metallization structure.
The metallization structure is not shown but is mentioned (“metallization processing generally follow” the disclosed manufacturing steps [0033]). Those in the art would have recognized that the contact 142 would lead to the metallization structure. See Birner, FIG. 11, showing metallization structure 160 connected to contacts. This would have been understood to be the arrangement suggested by Edwards.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Mori, US 2017/0250259 A1, drain finger DR, deep trench isolation DTI.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER BRADFORD/Primary Examiner, Art Unit 2897
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