DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention I, claims 1-8 and 16-20, in the reply filed on 05/01/2025 is acknowledged.
Claims 9-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 05/01/2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sawamoto (US 2018/0197822).
Regarding claim 1, Sawamoto discloses, in FIGS. 1-3 and in related text, a method of manufacturing a semiconductor device, the method comprising:
providing a microelectronics package comprising:
a leadframe comprising a peripheral ring (20) that defines a perimeter of the microelectronics package;
a plurality of ground leads (22) attached to or integral with the leadframe, each of the plurality of ground leads including a ground pad (22) that is exposed through a bottom of the microelectronics package;
a plurality of signal pads (12) exposed through the bottom of the microelectronics package (see Sawamoto, FIGS. 1-2, [0039]-[0040]);
one or more microelectronic components (31) each affixed to one or both of the leadframe and one or more of the plurality of signal pads (see Sawamoto, FIGS. 1-2, [0038]: die 31 is attached to signal pads 12 by bonding wires 32); and
a layer of molding compound (41) disposed over the leadframe (20), the plurality of ground leads (22), the plurality of signal pads (12), and the one or more microelectronic components (31) (see Sawamoto, FIG. 2, [0048]);
making a first cut (with dicing blade 72) into the microelectronics package at the perimeter, the first cut extending from a top of the microelectronics package into the peripheral ring of the leadframe to expose one or more contact surfaces of the peripheral ring (see Sawamoto, FIG. 2, [0049]); and
forming a shielding enclosure (51) that completely covers the top of the microelectronics package and a plurality of sides of the microelectronics package formed by the first cut, and that contacts the peripheral ring at the one or more contact surfaces, the shielding enclosure comprising an electromagnetic shielding material (metal), and the shielding enclosure maintaining contact with the peripheral ring (20) entirely around the microelectronics package (see Sawamoto, FIG. 3, [0051]-[0052]).
Regarding claim 2, Sawamoto discloses the method of claim 1.
Sawamoto discloses wherein the layer of molding compound (41) extends to the perimeter (20), and making the first cut comprises cutting vertically through the layer of molding compound to a first depth within the peripheral ring to form the plurality of sides including a vertical contact surface (23) of the one more contact surfaces (see Sawamoto, FIG. 2, [0039], [0049]).
Regarding claim 3, Sawamoto discloses the method of claim 1.
Sawamoto discloses wherein making the first cut comprises forming a notch in the peripheral ring (20) extending inward from the perimeter, the one or more contact surfaces comprising a vertical surface (23) and a horizontal surface (top surface of 22) defined by the notch (see Sawamoto, FIGS. 1-2, [0039], [0049]).
Regarding claim 4, Sawamoto discloses the method of claim 3.
Sawamoto discloses wherein forming the shielding enclosure (51) comprises:
forming a top plate of the shielding enclosure on the top of the microelectronics package (over upper surface 41b);
forming a plurality of side plates of the shielding enclosure each on a corresponding side of the of the plurality of sides (covering side surface 41a), the plurality of side plates each being integral with the top plate and with adjacent side plates and each contacting the vertical surface (23) of the notch; and
forming a connecting portion of the shielding enclosure on the horizontal surface (top surface of 22) of the notch, the connecting portion being integral with the plurality of side plates and extending around the perimeter (see Sawamoto, FIG. 3, [0051]-[0052]).
Regarding claim 5, Sawamoto discloses the method of claim 1.
Sawamoto discloses wherein forming the shielding enclosure comprises depositing the electromagnetic shielding material onto the microelectronics package with a metal plating process (see Sawamoto, [0051]).
Claims 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sawamoto (US 2018/0197822).
Regarding claim 16, Sawamoto discloses, in FIGS. 1-3 and in related text, a method of manufacturing a packaged semiconductor device, the method comprising:
providing a quad flat no-lead microelectronics package comprising (see Sawamoto, [0036]):
a leadframe comprising a peripheral ring (20) that defines a perimeter of the microelectronics package;
a plurality of ground pads (22) and a plurality of signal pads (12) exposed through a bottom of the microelectronics package, the ground pads in electrical communication with the leadframe (see Sawamoto, FIGS. 1-2, [0039]-[0040]);
one or more microelectronic components (31) each affixed to one or both of the leadframe and one or more of the plurality of signal pads (see Sawamoto, FIGS. 1-2, [0038]: die 31 is attached to signal pads 12 by bonding wires 32); and
a layer of molding (41) compound disposed over the leadframe (20), the plurality of ground pads (22), the plurality of signal pads (12), and the one or more microelectronic components (31) (see Sawamoto, FIG. 2, [0048]);
exposing (by cutting with dicing blade 72) one or more contact surfaces of the peripheral ring (20) entirely around a perimeter of the microelectronics package (see Sawamoto, FIG. 2, [0049]); and
forming a shielding enclosure (51) that completely covers the layer of molding compound (41) and contacts the peripheral ring (20) at the one or more contact surfaces, the shielding enclosure comprising an electromagnetic shielding material (metal), and the shielding enclosure maintaining contact with the peripheral ring (20) entirely around the microelectronics package (see Sawamoto, FIG. 3, [0051]-[0052]).
Regarding claim 17, Sawamoto discloses the method of claim 16.
Sawamoto discloses wherein the layer of molding compound (41) extends to the perimeter (over 20), and exposing the one or more contact surfaces comprises making a first cut (with dicing blade 72) into the microelectronics package at the perimeter, the first cut extending from a top of the microelectronics package through the layer of molding compound to expose a horizontal surface (top surface of 22) of the one or more contact surfaces of the peripheral ring (20) (see Sawamoto, FIG. 2, [0049]).
Regarding claim 18, Sawamoto discloses the method of claim 16.
Sawamoto discloses wherein exposing the one or more contact surfaces further comprises making a first cut (with dicing blade 72) into the peripheral ring to form a notch comprising a horizontal surface (top surface of 22) and a vertical surface (23) of the one or more contact surfaces of the peripheral ring (20) (see Sawamoto, FIGS. 1-2, [0039], [0049]).
Regarding claim 19, Sawamoto discloses the method of claim 18.
Sawamoto discloses wherein forming the shielding enclosure (51) comprises:
forming a top portion of the shielding enclosure on a top surface of the layer of molding compound (41) (over upper surface 41b);
forming a connecting portion of the shielding enclosure on the horizontal surface (top surface of 22) of the notch, the connecting portion extending around the microelectronics package; and
forming a plurality of side portions of the shielding enclosure each (covering side surface 41a):
extending vertically between the top portion and the connecting portion;
being attached to or integral with the top portion, the connecting portion, and adjacent side portions; and
contacting the vertical surface (23) of the notch (see Sawamoto, FIG. 3, [0051]-[0052]).
Claim 16 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Swan (US 8,053,872).
Regarding claim 16, Swan discloses, in FIGS. 7-11 and in related text, a method of manufacturing a packaged semiconductor device, the method comprising:
providing a quad flat no-lead microelectronics package comprising (see Swan, column 2, line 65 to column 3, line 7):
a leadframe comprising a peripheral ring (ring of ground pads 16) that defines a perimeter of the microelectronics package (see Swan, FIG. 2, column 5, lines 4 to 22);
a plurality of ground pads (16) and a plurality of signal pads (14) exposed through a bottom of the microelectronics package, the ground pads in electrical communication with the leadframe (see Swan, FIG. 7, column 4, line 60 to column 5, line 22);
one or more microelectronic components (20) each affixed to one or both of the leadframe and one or more of the plurality of signal pads (14) (see Swan, FIGS. 8-9, column 5, lines 23 to 34: die 20 is attached to signal pads by wire bonds 22); and
a layer of molding compound (26) disposed over the leadframe (ring of ground pads 16), the plurality of ground pads (16), the plurality of signal pads (14), and the one or more microelectronic components (20);
exposing one or more contact surfaces of the peripheral ring (ring of ground pads 16) entirely around a perimeter of the microelectronics package (see Swan, FIG. 10, column 5, lines 35 to 42); and
forming a shielding enclosure (34) that completely covers the layer of molding compound (26) and contacts the peripheral ring (ground pads 16) at the one or more contact surfaces, the shielding enclosure comprising an electromagnetic shielding material (metals), and the shielding enclosure maintaining contact with the peripheral ring entirely around the microelectronics package (see Swan, FIG. 11, column 5, line 43 to column 6, line 25).
Allowable Subject Matter
Claims 6-8 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of records, individually or in combination, do not disclose nor teach “wherein the plurality of signal pads are each electrically connected to the peripheral ring of the leadframe, the method further comprising severing an electrical connection between the peripheral ring and the plurality of signal pads” in combination with other limitations as recited in claim 6.
The prior art of records, individually or in combination, do not disclose nor teach “wherein: the microelectronics package further comprises a plurality of conductive connecting portions each: attached to or integral with a corresponding one of the plurality of signal pads; attached to the peripheral ring of the leadframe; disposed approximate the bottom of the microelectronics package; and having a thickness that is less than a thickness of the leadframe; the plurality of ground leads each has the thickness of the leadframe; and the method further comprises making a second cut into the bottom of the microelectronics package inward of the peripheral ring and through the plurality of connecting portions and the plurality of ground leads, the second cut having a depth at least equal to the thickness of the plurality of connecting portions and less than the thickness of the plurality of ground leads” in combination with other limitations as recited in claim 8.
The prior art of records, individually or in combination, do not disclose nor teach “severing an electrical connection between the plurality of signal pads and the peripheral ring” in combination with other limitations as recited in claim 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811
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