DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/16/2026, 02/06/2025, 08/21/2024 and 03/21/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Therefore, the “a first plate coupled directly to the second control terminal” in Claim 1; and “coupling a bypass capacitor directly between each gate and a fixed voltage node” in Claim 16; and “a capacitor having a first plate coupled directly to the second control terminal” in Claim 20 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 17 objected to because of the following informalities:
In Claim 17, line 1, the recitations of “an amplifier” should change to read as ---the amplifier---.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In Claim 1, line 7, the recites of ““a first plate coupled directly to the second control terminal” is unclear because at least an inductor being connected between capacitor CDCP1 and gate terminal of the transistor. Even in the light of the original specification does not appear clearly defined as to how the first plate coupled directly to the second control terminal. Further clarification is needed.
Claims 16 & 20, recites similarly the limitations of “coupling a bypass capacitor directly between each gate and a fixed voltage node” in Claim 16; and “a capacitor having a first plate coupled directly to the second control terminal” in Claim 20. Thus, Claims 16 & 20 are rejected in the same manner as discussed in Claim 1.
For the purpose of the examining the examiner interpret “coupled directly” to read as ----coupled---; and “coupling a bypass capacitor directly between” to read as --- coupling a bypass capacitor between---.
Claims 2-15, 17-19 &21-26 are rejected due to their dependency.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 6-7 & 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shigematsu (US 20030011436 A1, of record).
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Regarding claims 1, 7 & 16:
Shigematsu discloses in Fig. 3, a power amplifier cell or method comprising:
a first transistor (transistor Q1) having a first current terminal (source terminal of Q1) coupled to a fixed voltage node (ground node), a second current terminal (drain terminal of Q1), and a first control terminal (gate terminal of Q1);
a second transistor (Q2) having a third current terminal (source terminal of Q2) coupled to the second current terminal, a fourth current terminal (drain terminal Q2), and a second control terminal (gate terminal of Q2);and
a capacitor (Cgate) having a first plate (top plate) coupled
Regarding claim 4:
Shigematsu discloses in Fig. 3, wherein inductance (see inductor lcg) between the first plate (top plate) and the second control terminal (gate terminal of Q2) is parasitic inductance.
Regarding claims 6 & 14:
Shigematsu discloses in Fig. 3, wherein the fixed voltage node is ground (see ground of Fig. 3).
Claims 1-3, 6-10 & 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lehtola (US 9,923,523 B2).
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Regarding claim 1:
Lehtola discloses in Fig. 8, a power amplifier cell (167, 168, Col. 4, lines 55-57, It will be understood that one or more features of the present disclosure can also be implemented in or with other types of transistors such as field-effect transistors FETs) comprising:
a first transistor (FET1) having a first current terminal (source) coupled to a fixed voltage node (ground node), a second current terminal (drain), and a first control terminal (gate);
a second transistor (FET2) having a third current terminal (source) coupled to the second current terminal, a fourth current terminal (drain), and a second control terminal (gate); and
a capacitor (C1) having a first plate (top plate) coupled [[directly]] to the second control terminal and a second plate (bottom plate) coupled to the fixed voltage node (ground node).
Regarding claim 2:
Lehtola discloses in Fig. 8, wherein there is no intervening inductor (none inductor) component coupled between the first plate (top plate) and the second control terminal (gate of FET2).
Regarding claim 3:
Lehtola discloses in Fig. 8, wherein there is no intervening resistor (none resistor) component coupled between the first plate (top plate) and the second control terminal (gate of FET2).
Regarding claims 6 & 14:
Lehtola discloses in Fig. 8, wherein the fixed voltage node is ground (ground as seen from Fig. 8).
Regarding claim 7:
Lehtola discloses in Fig. 8, a power amplifier (Fig. 8) comprising a plurality of the power amplifier cells of claim 1.
Regarding claim 8:
Lehtola discloses in Fig. 8, wherein the plurality of power amplifier cells comprises a Doherty power amplifier (Col. 1, lines 29-30, a Doherty power amplifier PA).
Regarding claim 9:
Lehtola discloses in Fig. 8, wherein there is no intervening inductor component coupled between the first plate and the second control terminal (as can be seen from Fig. 8).
Regarding claim 10:
Lehtola discloses in Fig. 8, wherein there is no intervening resistor component coupled between the first plate and the second control terminal (Fig 8 show none resistor).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shigematsu.
Regarding claim 5:
Shigematsu discloses in Fig. 3 wherein the capacitor (Cgate) connected to the inductor (lcg) except for the capacitor has capacitance sized to resonate with the parasitic inductance at a resonant frequency substantially higher than a desired frequency of operation of the power amplifier cell.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have characterized the capacitor has capacitance sized to resonate with the parasitic inductance at a resonant frequency substantially higher than a desired frequency of operation of the power amplifier cell, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claim(s) 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lehtola (US 9,923,523 B2) in view of Shigematsu (US 20030011436 A1, of record).
Regarding claim 11 & 12:
Lehtola discloses the limitations as discussed in claim 7.
Lehtola does not disclose further comprising an inductor and resistor being connected to the second control terminal of the second transistor.
Shigematsu discloses a resistor Rgate and inductor lcg being connected to the gate terminal of Q2.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit of Lehtola to include resistor and inductor as taught by Shigematsu in order to have imparted the advantageous benefit of preventing the oscillation and reducing the sensitivity of the unit circuit to frequencies in the high frequency range of the circuit (see par. [0041], lines 3-8), thereby suggesting the obviousness of such a modification.
Accordingly, as an obvious consequence combination above, the combination (Lehtola in view of Shigematsu) further teaches wherein inductance between the first plate and the second control terminal is parasitic inductance; (Claim 12) further comprising a resistor coupled between the parasitic inductance and the first plate.
Regarding claim 13:
The combination (Lehtola in view of Shigematsu) discloses the limitations of claim 11 and resistor being connected to the inductor except for wherein the capacitor has capacitance sized to resonate with the parasitic inductance at a resonant frequency substantially higher than a desired frequency of operation of the power amplifier cell.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have characterized the capacitor has capacitance sized to resonate with the parasitic inductance at a resonant frequency substantially higher than a desired frequency of operation of the power amplifier cell, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lehtola (US 9,923,523 B2) in view of Fraser et al. ( US 11,128,266 B1, hereinafter called Fraser).
Regarding claim 15:
Lehtola discloses the limitations as applied in claim 7 except for wherein the cascode transistor structure is fabricated of gallium nitride technology.
Fraser (Fig. 5) discloses an amplifier circuit comprising a cascode transistor 505 being connected to a transistor 510 and wherein the cascode transistor 505 and transistor 510 may be implemented using well-known gallium nitride (Col. 6, lines 45-49, he transistors 505 and 510 may be implemented using silicon, silicon-germanium, gallium nitride).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have implemented the cascode transistor and transistor as taught by Lehtola with the well-known gallium nitride as taught by Fraser in order to provide the benefits of improving gain (Col. 4, lines 24-25) and bandwidth, power efficiency and overall noise figure.
Claim(s) 16 & 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takenaka (US 10,411,653 B2) in view of Lehtola (US 9,923,523 B2) and further in view of Shigematsu (US 20030011436 A1, of record).
Regarding claim 16.
Takenaka discloses in Fig. 1 an amplifier or method comprising a driver stage 110 and final stage includes amplifier 111 and 112 except each amplifier includes a cascode transistor structure and a capacitor connected to the gate of the cascode transistor.
Lehtola discloses in Fig. 8 a well-known amplifier circuit comprising amplifier 207 and amplifier 208 where in each amplifier comprising a cascode transistor structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit of Takenaka to include well-known amplifiers 207 and 208 as taught by Lehtola in order to provide the benefits of improving gain and reduce loss (Col. 5, lines 21-24), hence improving the system stability and performance.
The combination (Takenaka in view of Lehtola) does not discloses an inductor connected in series with resistor and capacitor.
Shigematsu discloses a capacitor, a resistor Rgate and inductor lcg being connected to the gate terminal of Q2.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit of the combination to include resistor and inductor connected in series with capacitor as taught by Shigematsu in order to have imparted the advantageous benefit of preventing the oscillation and reducing the sensitivity of the unit circuit to frequencies in the high frequency range of the circuit (see par. [0041], lines 3-8), thereby suggesting the obviousness of such a modification.
Accordingly, as an obvious consequence combination above, the combination (Takenaka and Lehtola in view of Shigematsu) further discloses the of realizing enhanced lineup efficiency in an amplifier having a driver stage configured to drive a final stage, the method comprising: implementing a cascode transistor structure (see Fig. 8 of Lehtola) within each of a plurality of power amplifier cells (amplifiers 111 and 112) comprising the final stage; and
minimizing inductance (inductor lcg, Fig. 3 of Shigematsu) at a gate of each of a common gate transistor comprising the cascode transistor structure by coupling a bypass capacitor (see un-label capacitor or annotated capacitor C2 as shown in cascode structure, annotated Fig. 8 of Lehtola) [[[directly]]] between each gate and a fixed voltage node (ground node).
Regarding claim 18:
The combination (Takenaka and Lehtola in view of Shigematsu) discloses wherein the fixed voltage node is ground (ground).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination (Takenaka and Lehtola in view of Shigematsu).
Regarding claim 17:
The combination ((Takenaka and Lehtola in view of Shigematsu) discloses the limitations as applied in claim 16 except for sizing capacitance of the bypass capacitor to resonate with a parasitic inductance at a resonant frequency substantially higher than a desired frequency of operation of the amplifier.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have characterized sizing capacitance of the bypass capacitor to resonate with a parasitic inductance at a resonant frequency substantially higher than a desired frequency of operation of the amplifier, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over the combination (Takenaka , Lehtola and Shigematsu and further in view of Fraser et al. ( US 11128266 B1, hereinafter called Fraser).
Regarding claim 19:
The combination ((Takenaka and Lehtola in view of Shigematsu) discloses the limitations as applied in claim 16 except for wherein the cascode transistor structure is fabricated of gallium nitride technology.
Fraser (Fig. 5) discloses an amplifier circuit comprising a cascode transistor 505 being connected to a transistor 510 and wherein the cascode transistor 505 may be implemented using well-known gallium nitride (Col. 6, lines 45-49, he transistors 505 and 510 may be implemented using silicon, silicon-germanium, gallium nitride).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have implemented the cascode transistor as taught by the combination (Takenaka and Lehtola in view of Shigematsu) with the well-known gallium nitride as taught by Fraser in order to provide the benefits of improving gain (Col. 4, lines 24-25) and bandwidth, power efficiency and overall noise figure.
Claim(s) 20-22 & 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liang et al. (US 20100316164 A1, hereinafter, Liang) in view of Ding (US 20200313626 A1).
Regarding claim 20:
Liang disclose in Fig. 1,a wireless communication device comprising:
a baseband processor (102); transmit circuitry (e.g. form by frequency circuit 104 and amplifier PA and an antenna 108 being connected to the amplifier.
Liang does not disclose a transmit circuit include an amplifier that includes specific limitations as cited in claim 20.
Ding discloses in Fig. 1 an amplifier comprises:
a first transistor (Q1) having a first current terminal (emitter terminal) coupled to a fixed voltage node (ground node), a second current terminal (collector), and a first control terminal (base) configured to receive carrier signal;
a second transistor (Q2) having a third current terminal (emitter) coupled to the second current terminal (collector of Q1), a second control terminal (base), and a fourth current terminal (collector) configured to output an amplified version of the carrier signal; and
a capacitor (C2) having a first plate (tope plated) coupled [[directly]] to the second control terminal (base of Q2) and a second plate (bottom plate) coupled to the fixed voltage node (ground).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the generic amplifier PA as taught by Liang with the amplifier as taught by Ding in order to increase the reliability and stability of the power amplifier (see par. [0021], which would increase the reliability and stability of the power amplifier).
Regarding claims 21-22 & 26:
The combination (Liang in view of Ding) discloses further wherein there is no intervening inductor component coupled between the first plate and the second control terminal; and (Claim 22) wherein there is no intervening resistor component coupled between the first plate and the second control terminal (see Fig. 1 of Ding); and (Claim26) wherein the fixed voltage node is ground (ground).
Claim(s) 20 & 23-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liang et al. (US 20100316164 A1, hereinafter, Liang) in view of Shigematsu (US 20030011436 A1, of record).
Regarding claim 20:
Liang disclose in Fig. 1,a wireless communication device comprising:
a baseband processor (102); transmit circuitry (e.g. form by frequency circuit 104 and amplifier PA and an antenna 108 being connected to the amplifier.
Liang does not disclose a transmit circuit include an amplifier that includes specific limitations as cited in claim 20.
Shigematsu discloses in Fig. 2 an amplifier comprises:
a first transistor (Q1) having a first current terminal (source) coupled to a fixed voltage node (ground node), a second current terminal (drain), and a first control terminal (gate) configured to receive carrier signal;
a second transistor (Q2) having a third current terminal (source) coupled to the second current terminal (drain of T2), a second control terminal (gate), and a fourth current terminal (drain) configured to output an amplified version of the carrier signal; and
a capacitor (Cgate) having a first plate (tope plated) coupled [[directly]] to the second control terminal (gate of Q2) and a second plate (bottom plate) coupled to the fixed voltage node (ground).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the generic amplifier PA as taught by Liang with the amplifier as taught by Shigematsu in order to have imparted the advantageous benefit of preventing the oscillation and reducing the sensitivity of the unit circuit to frequencies in the high frequency range of the circuit (see par. [0041], lines 3-8), thereby suggesting the obviousness of such a modification.
Regarding claim 23:
The combination (Liang in view of Shigematsu) discloses wherein inductance between the first plate (top plate) and the second control terminal (gate of Q2) is parasitic inductance.
Regarding claim 24:
The combination (Liang in view of Shigematsu) discloses further comprising a power amplifier comprising a resistor (Rgate) coupled between the parasitic inductance and the first plate (top plate).
Regarding claim 26:
The combination (Liang in view of Shigematsu) discloses wherein the fixed voltage node is ground (ground).
Regarding claim 25:
The combination (Liang in view of Shigematsu) discloses the limitations as applied in claim 23 except for the capacitor has capacitance sized to resonate with the parasitic inductance at a resonant frequency substantially higher than a desired frequency of operation of the power amplifier cell.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have characterized the capacitor has capacitance sized to resonate with the parasitic inductance at a resonant frequency substantially higher than a desired frequency of operation of the power amplifier cell, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Conclusion
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
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