DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (2022/0310577, hereafter Lee) in view of Molzer et al. (2015/0084194, hereafter Molzer).
Regarding claim 1, Lee discloses a semiconductor device comprising: a first chiplet (300, Fig. 1B, par. 0042) and a second chiplet (200 right, Fig. 1B, par. 0038) present on a same level and laterally separated by an insulating region (410, Fig. 1B, par. 0077), wherein the first chiplet is present on a first lateral side of the insulating region and the second chiplet is present on an opposite second lateral side of the insulating region; and a through insulator via (350S left, Fig. 1B, par. 0073) disposed in the insulating region at a location laterally between the first chiplet and the second chiplet and extending vertically through the insulating region from a first face of the insulating region to an opposite second face of the insulating region (Fig. 1B).
Lee fails to disclose the through insulator via including a coaxial arrangement of a signal via having ground shielding about a perimeter of the signal via, wherein the ground shielding is continuous from the first face of the insulating region to the opposite second face of the insulating region.
However, Molzer teaches the through insulator via (22B, Fig. 2, par. 0028) including a coaxial arrangement of a signal via having ground shielding (22A, Fig. 2, par. 0028) about a perimeter of the signal via, wherein the ground shielding is continuous from the first face of the insulating region to the opposite second face of the insulating region (Fig. 3B).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee with Molzer by providing a through insulator via with a coaxial arrangement having a ground shielding in order to confine electromagnetic fields, minimizing crosstalk, enabling precise impedance matching, and reducing energy loss.
Regarding claim 2, Lee fails to disclose a semiconductor device wherein the signal via is separated from the ground shielding by a via insulating material.
However, Molzer teaches a semiconductor device wherein the signal via (22B, Fig. 2) is separated from the ground shielding (22A, Fig. 2) by a via insulating material (24B, Fig. 2, par. 0028).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee with Molzer by providing the signal via separated from the ground shielding by an insulating material in order to prevent electrical short circuiting while controlling capacitance to maintain impedance matching.
Regarding claim 3, Lee fails to disclose a semiconductor device wherein the insulating region has a first dielectric composition that is different from a second dielectric composition for the via insulating material.
However, Molzer teaches a semiconductor device wherein the insulating region (126, Fig. 12; 34A, Fig. 3A) has a first dielectric composition that is different from a second dielectric composition for the via insulating material (34B, Fig. 3A, par. 0029).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee with Molzer by providing insulating material that has a different dielectric composition than the insulating region in order to optimize signal speed and match impedance while absorbing mechanical thermal stress.
Regarding claim 4, Lee discloses a semiconductor device wherein the through insulator via (350S left, Fig. 1B) connected to a bridge chip (610, Fig. 1B, par. 0028) that is present on the first chiplet (300, Fig. 1B) and the second chiplet (200 right, Fig. 1B).
Regarding claim 5, Lee discloses a semiconductor device wherein the through insulator via (350S, Fig. 1B) is in electrical communication with a redistribution layer (120, Fig. 1B, par. 0028) on at least one of the firstface and the opposite second face of the insulating region (410, Fig. 1B), the redistribution layer being in electrical communication with at least one of the first chiplet (300, Fig. 1B) and the second chiplet (200 right, Fig. 1B).
Regarding claim 6, Lee discloses a semiconductor device further comprising a plurality of chiplets (610, 200, 300) present in two stacked levels (Fig. 1B), wherein the through insulator via is a skip via (350S, Fig. 1B).
Regarding claim 7, Lee discloses a semiconductor device further comprising a power via (350PG, Fig. 1B, par. 0074), wherein the power via does not include ground shielding (par. 0074) in the insulating region (410, Fig. 1B), and wherein the through insulator via (350S) is integrated with the power via (Fig. 1B).
Regarding claim 8, Lee discloses a semiconductor device comprising: a first chiplet (300, Fig. 1B, par. 0042) and a second chiplet (200 right, Fig. 1B, par. 0038) present on a same level and laterally separated by an insulating region (410, Fig. 1B, par. 0077), wherein the first chiplet is present on a first lateral side of the insulating region and the second chiplet is present on an opposite second lateral side of the insulating region; and a through insulator via (350S left, Fig. 1B, par. 0073) disposed in the insulating region at a location laterally between the first chiplet and the second chiplet and extending vertically through the insulating region from a first face of the insulating region to an opposite second face of the insulating region.
Lee fails to disclose the through insulator via including a coaxial arrangement of a signal via of a first metal composition having ground shielding of a second metal composition about a perimeter of the signal via, the first metal composition being different than the second metal composition, wherein the ground shielding is continuous from the first face of the insulating region to the opposite second face of the insulating region.
However, Molzer teaches the through insulator via including a coaxial arrangement of a signal via (22B, Fig. 2, par. 0028) of a first metal composition having ground shielding (22A, Fig. 2, par. 0028) of a second metal composition about a perimeter of the signal via, the first metal composition being different than the second metal composition (par. 0026), wherein the ground shielding is continuous from the first face of the insulating region to the opposite second face of the insulating region (Fig. 3B).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee with Molzer by providing a through insulator via with a coaxial arrangement having a ground shielding of a different metal composition than the signal via in order to confine electromagnetic fields, minimizing crosstalk, enabling precise impedance matching, and reducing energy loss and to optimize conductivity at the core while providing a barrier that withstands stress and prevents atomic migration into the dielectric.
Regarding claim 9, Lee fails to disclose a semiconductor device wherein the signal via is separated from the ground shielding by a via insulating material.
However, Molzer teaches a semiconductor device wherein the signal via (22B, Fig. 2) is separated from the ground shielding (22A, Fig. 2) by a via insulating material (24B, Fig. 2, par. 0028).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee with Molzer by providing the signal via separated from the ground shielding by an insulating material in order to prevent electrical short circuiting while controlling capacitance to maintain impedance matching.
Regarding claim 10, Lee fails to disclose a semiconductor device wherein the insulating region has a first dielectric composition that is different from a second dielectric composition for the via insulating material.
However, Molzer teaches a semiconductor device wherein the insulating region (126, Fig. 12; 34A, Fig. 3A) has a first dielectric composition that is different from a second dielectric composition for the via insulating material (34B, Fig. 3A, par. 0029).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee with Molzer by providing insulating material that has a different dielectric composition than the insulating region in order to optimize signal speed and match impedance while absorbing mechanical thermal stress.
Regarding claim 11, Lee discloses a semiconductor device wherein the through insulator via (350S left, Fig. 1B) connected to a bridge chip (610, Fig. 1B, par. 0028) that is present on the first chiplet (300, Fig. 1B) and the second chiplet (200 right, Fig. 1B).
Regarding claim 12, Lee discloses a semiconductor device wherein the through insulator via (350S, Fig. 1B) is in electrical communication with a redistribution layer (120, Fig. 1B, par. 0028) on at least one of the firstface and the opposite second face of the insulating region (410, Fig. 1B), the redistribution layer being in electrical communication with at least one of the first chiplet (300, Fig. 1B) and the second chiplet (200 right, Fig. 1B).
Regarding claim 13, Lee discloses a semiconductor device further comprising a plurality of chiplets (610, 200, 300) present in two stacked levels (Fig. 1B), wherein the through insulator via is a skip via (350S, Fig. 1B).
Regarding claim 14, Lee discloses a semiconductor device further comprising a power via (350PG, Fig. 1B, par. 0074), wherein the power via does not include ground shielding (par. 0074) in the insulating region (410, Fig. 1B), and wherein the through insulator via (350S) is integrated with the power via (Fig. 1B).
Regarding claim 15, Lee discloses semiconductor device comprising: a first chiplet (300, Fig. 1B, par. 0042) and a second chiplet (200 right, Fig. 1B, par. 0038) present on a same level and laterally separated by an insulating region (410, Fig. 1B, par. 0077), wherein the first chiplet is present on a first lateral side of the insulating region and the second chiplet is present on an opposite second lateral side of the insulating region; and a through insulator via (350S left, Fig. 1B, par. 0073) disposed in the insulating region at a location laterally between the first chiplet and the second chiplet and extending vertically through the insulating region from a first face of the insulating region to an opposite second face of the insulating region.
Lee fails to disclose the through insulator via including a coaxial arrangement of a signal via having ground shielding about a perimeter of the signal via, the signal via and the ground shielding each having a same metal composition, wherein the ground shielding is continuous from the first face of the insulating region to the opposite second face of the insulating region.
However, Molzer teaches the through insulator via including a coaxial arrangement of a signal via (22B, Fig. 2, par. 0028) having ground shielding (22A, Fig. 2, par. 0028) about a perimeter of the signal via, the signal via and the ground shielding each having a same metal composition (par. 0028, 0032), wherein the ground shielding is continuous from the first face of the insulating region to the opposite second face of the insulating region (Fig. 3B).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee with Molzer by providing a through insulator via with a coaxial arrangement having a ground shielding of a different metal composition than the signal via in order to confine electromagnetic fields, minimizing crosstalk, enabling precise impedance matching, and reducing energy loss and to simplify fabrication and ensure matched thermal expansion thus preventing mechanical stress and delamination.
Regarding claim 16, Lee fails to disclose a semiconductor device wherein the signal via is separated from the ground shielding by a via insulating material.
However, Molzer teaches a semiconductor device wherein the signal via (22B, Fig. 2) is separated from the ground shielding (22A, Fig. 2) by a via insulating material (24B, Fig. 2, par. 0028).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee with Molzer by providing the signal via separated from the ground shielding by an insulating material in order to prevent electrical short circuiting while controlling capacitance to maintain impedance matching.
Regarding claim 17, Lee fails to disclose a semiconductor device wherein the insulating region has a first dielectric composition that is different from a second dielectric composition for the via insulating material.
However, Molzer teaches a semiconductor device wherein the insulating region (126, Fig. 12; 34A, Fig. 3A) has a first dielectric composition that is different from a second dielectric composition for the via insulating material (34B, Fig. 3A, par. 0029).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Lee with Molzer by providing insulating material that has a different dielectric composition than the insulating region in order to optimize signal speed and match impedance while absorbing mechanical thermal stress.
Regarding claim 18, Lee discloses a semiconductor device wherein the through insulator via (350S left, Fig. 1B) connected to a bridge chip (610, Fig. 1B, par. 0028) that is present on the first chiplet (300, Fig. 1B) and the second chiplet (200 right, Fig. 1B).
Regarding claim 19, Lee discloses a semiconductor device wherein the through insulator via (350S, Fig. 1B) is in electrical communication with a redistribution layer (120, Fig. 1B, par. 0028) on at least one of the firstface and the opposite second face of the insulating region (410, Fig. 1B), the redistribution layer being in electrical communication with at least one of the first chiplet (300, Fig. 1B) and the second chiplet (200 right, Fig. 1B).
Regarding claim 20, Lee discloses a semiconductor device further comprising a plurality of chiplets (610, 200, 300) present in two stacked levels (Fig. 1B), wherein the through insulator via is a skip via (350S, Fig. 1B).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.M.B./ Examiner, Art Unit 2817 /ALI NARAGHI/Primary Examiner, Art Unit 2817
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