CTNF 18/400,458 CTNF 101794 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Drawings 06-22-06 AIA The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: label “53” in paragraph [0068], label “55” in [0072] probably aligns with “5” in Fig. 12 . Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1, 2, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo et al. (2017/0278806) in view of Lum et al. (2019/0027436) . Regarding claim 1 , Kuo et al. (hereafter Kuo) disclose a semiconductor device comprising: at least two chiplets (6 and 8, Fig. 1); and a through insulator via (TIV) extending through the insulating region (Fig. 6B), the through insulator via (TIV) including a coaxial arrangement of a signal via having ground shielding (112) about a perimeter of the signal via (par. 0035), wherein the ground shielding is continuous from a first face of the insulating region to a second face of the insulating region (Fig. 6B). Kuo fails to disclose the at least two chiplets separated by an insulating region. However, Lum et al. (hereafter Lum) disclose a semiconductor device comprising: at least two chiplets (104 and 108, Fig. 1) separated by an insulating region (112, Fig. 1) (par. 0024). It would have been obvious to one of ordinary skill in the art at the time the invention was filed, to modify Kuo with the teachings of Lum because doing so would provide communication through the isolation region with noise prevention. Regarding claim 2 , Kuo discloses a semiconductor wherein the signal via (174a, Fig. 6B) is separated from the ground shielding by a via insulating material (110, Fig. 6B) (par. 0035). Regarding claim 6 , Kuo discloses a semiconductor device wherein the at least two chiplets includes two stacked levels of chiplets (50, Fig. 2) and the through insulator via is a skip via (70, Fig. 2) (par. 0024) . 07-22-aia AIA Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kuo et al. (2017/0278806) in view of Lum et al. (2019/0027436) as applied to claim 1 above, and further in view of Palanduz et al. (7081650) . Regarding claim 3 , Kuo and Lum are discussed above. Kuo and Lum fail to disclo se the insulating region having a first dielectric composition that is different from a second dielectric composition for the via insulating material. However, Palanduz et al. (hereafter Palanduz) disclose a semiconductor device of claim 2, wherein the insulating region has a first dielectric composition (Col. 5, lines 19-21) that is different from a second dielectric composition for the via insulating material (Col. 8, lines 31-40). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Kuo with Palanduz in order to optimize for cost and communication speed of the material . 07-22-aia AIA Claim s 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo et al. (2017/0278806) in view of Lum et al. (2019/0027436) as applied to claim 1 above, and further in view of Lee et al. (2023/0115073) . Regarding claim 4 , Kuo and Lum are discussed above. Neither dis close that the through insulator via (TIV) is connected to a bridge chip that is present on the at least two chiplets. However, Lee et al. (hereafter Lee) disclose a semiconductor device wherein the through insulator via (TIV) (127, Fig. 6, par. 0071) is connected to a bridge chip (120, Fig. 6, par. 0071) that is present on the at least two chiplets (210 and 220, Fig. 2, par. 0031). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Kuo with Lee in order to combine the chiplets in a single package. Regarding claim 5 , Kuo and Lum are discussed above. Neither disclose that the through insulator via is in electrical communication with a redistribution layer on at least one of the first and second face of the insulating region, the redistribution layer being in electrical communication with one of the at least two chiplets. However, Lee discloses a semiconductor device wherein the through insulator via (163, par. 0044) is in electrical communication with a redistribution layer on at least one of the first and second face of the insulating region (165, par. 0044), the redistribution layer being in electrical communication with one of the at least two chiplets (210 and 220, par. 0047). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Kuo with Lee in order to connect the TIV to the chiplets . 07-22-aia AIA Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kuo et al. (2017/0278806) in view of Lum et al. (2019/0027436) as applied to claim 1 above, and further in view of Kim et al. (2024/0145345) . Regarding claim 7 , Kuo and Lum are discussed above. Neither disclose that the through insulator via having the coaxial arrangement of the signal via having ground shielding about the perimeter of the signal via may be integrated with a power via that does not include ground shielding in the insulating region. However, Kim et al. (hereafter Kim) disclose a semiconductor device wherein the through insulator via having the coaxial arrangement of the signal via having ground shielding about the perimeter of the signal via may be integrated with a power via (par. 0058). Kim further teaches that such a power via should be in direct contact with the signal via (par. 0005). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Kuo with Kim in order to improve reliability and optimize space around the via . 07-21-aia AIA Claim s 8, 9, 13, 15, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo et al. (2017/0278806) in view of Lum et al. (2019/0027436) and Molzer et al. (2015/0084194) . Regarding claim 8 , Kuo discloses a semiconductor device comprising: at least two chiplets (6 and 8, Fig. 1); and a through insulator via (TIV) extending through the insulating region (Fig. 6B), the through insulator via (TIV) including a coaxial arrangement of a signal via having ground shielding (112) about a perimeter of the signal via (par. 0035), wherein the ground shielding is continuous from a first face of the insulating region to a second face of the insulating region (Fig. 6B). Kuo fails to disclose the at least two chiplets separated by an insulating region. However, Lum discloses a semiconductor device comprising: at least two chiplets (104 and 108, Fig. 1) separated by an insulating region (112, Fig. 1) (par. 0024). It would have been obvious to one of ordinary skill in the art at the time the invention was filed, to modify Kuo with the teachings of Lum because doing so would provide communication through the isolation region with noise prevention. Kuo further fails to disclose a signal via of a first metal composition having ground shielding of a second metal composition about a perimeter of the signal via, the first metal composition being different than the second metal composition. However, Molzer et al. (hereafter Molzer) disclose a signal via of a first metal composition (22B, Fig. 2, par. 0028) having a ground shielding of a second metal composition about the perimeter of the signal via (22A, Fig. 2, par. 0028), the first metal composition (32A, Fig. 3A, par. 0032) being different than the second metal composition (32B, Fig. 3A, par. 0032). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Kuo with the teachings of Molzer in order to allow for high frequency signal propagation. Regarding claim 9 , Kuo discloses a semiconductor wherein the signal via (174a, Fig. 6B) is separated from the ground shielding by a via insulating material (110, Fig. 6B) (par. 0035). Regarding claim 13 , Kuo discloses a semiconductor device wherein the at least two chiplets includes two stacked levels of chiplets (50, Fig. 2) and the through insulator via is a skip via (70, Fig. 2) (par. 0024). Regarding claim 15 , Kuo discloses a semiconductor device comprising: at least two chiplets (6 and 8, Fig. 1); and a through insulator via (TIV) extending through the insulating region (Fig. 6B), the through insulator via (TIV) including a coaxial arrangement of a signal via having ground shielding (112) about a perimeter of the signal via (par. 0035), the signal via and the ground shield each having a same metal composition (par. 0028), wherein the ground shielding is continuous from a first face of the insulating region to a second face of the insulating region (Fig. 6B). Kuo fails to disclose the at least two chiplets separated by an insulating region. However, Lum discloses a semiconductor device comprising: at least two chiplets (104 and 108, Fig. 1) separated by an insulating region (112, Fig. 1) (par. 0024). It would have been obvious to one of ordinary skill in the art at the time the invention was filed, to modify Kuo with the teachings of Lum because doing so would provide communication with noise prevention. Regarding claim 16 , Kuo discloses a semiconductor wherein the signal via (174a, Fig. 6B) is separated from the ground shielding by a via insulating material (110, Fig. 6B) (par. 0035). Regarding claim 20 , Kuo discloses a semiconductor device wherein the at least two chiplets includes two stacked levels of chiplets (50, Fig. 2) and the through insulator via is a skip via (70, Fig. 2) (par. 0024) . 07-22-aia AIA Claim s 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo et al. (2017/0278806) in view of Lum et al. (2019/0027436) and Molzer et al. (2015/0084194) as applied to claim s 8 and 15 above, and further in view of Palanduz et al. (7081650) . Regarding claim 10 , Kuo, Lum, and Molzer are discussed. Neither disclo se the insulating region having a first dielectric composition that is different from a second dielectric composition for the via insulating material. However, Palanduz discloses the insulating region having a first dielectric composition (Col. 5, lines 19-21) that is different from a second dielectric composition for the via insulating material (Col. 8, lines 31-40). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Kuo with Palanduz in order to optimize for cost and communication speed of the material. Regarding claim 17 , Kuo, Lum, and Molzer discussed above do not disclo se the insulating region having a first dielectric composition that is different from a second dielectric composition for the via insulating material. However, Palanduz discloses the insulating region having a first dielectric composition (Col. 5, lines 19-21) that is different from a second dielectric composition for the via insulating material (Col. 8, lines 31-40). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Kuo with Palanduz in order to optimize for cost and communication speed of the material . 07-22-aia AIA Claim s 11, 12, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo et al. (2017/0278806) in view of Lum et al. (2019/0027436) and Molzer et al. (2015/0084194) as applied to claim s 8 and 15 above, and further in view of Lee et al. (2023/0115073) . Regarding claim 11 , Kuo, Lum, and Molzer discussed above do not dis close that the through insulator via (TIV) is connected to a bridge chip that is present on the at least two chiplets. However, Lee discloses a semiconductor device wherein the through insulator via (TIV) (127, Fig. 6, par. 0071) is connected to a bridge chip (120, Fig. 6, par. 0071) that is present on the at least two chiplets (210 and 220, Fig. 2, par. 0031). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Kuo with Lee in order to combine the chiplets in a single package. Regarding claim 12 , Kuo, Lum, and Molzer discussed above do not disclose that the through insulator via is in electrical communication with a redistribution layer on at least one of the first and second face of the insulating region, the redistribution layer being in electrical communication with one of the at least two chiplets. However, Lee discloses a semiconductor device wherein the through insulator via (163, par. 0044) is in electrical communication with a redistribution layer on at least one of the first and second face of the insulating region (165, par. 0044), the redistribution layer being in electrical communication with one of the at least two chiplets (210 and 220, par. 0047). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Kuo with Lee in order to connect the TIV to the chiplets. Regarding claim 18 , Kuo, Lum, and Molzer discussed above do not dis close that the through insulator via (TIV) is connected to a bridge chip that is present on the at least two chiplets. However, Lee discloses a semiconductor device wherein the through insulator via (TIV) (127, Fig. 6, par. 0071) is connected to a bridge chip (120, Fig. 6, par. 0071) that is present on the at least two chiplets (210 and 220, Fig. 2, par. 0031). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Kuo with Lee in order to combine the chiplets in a single package. Regarding claim 19 , Kuo, Lum, and Molzer discussed above do not disclose that the through insulator via is in electrical communication with a redistribution layer on at least one of the first and second face of the insulating region, the redistribution layer being in electrical communication with one of the at least two chiplets. However, Lee discloses a semiconductor device wherein the through insulator via (163, par. 0044) is in electrical communication with a redistribution layer on at least one of the first and second face of the insulating region (165, par. 0044), the redistribution layer being in electrical communication with one of the at least two chiplets (210 and 220, par. 0047). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Kuo with Lee in order to connect the TIV to the chiplets . 07-22-aia AIA Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kuo et al. (2017/0278806) in view of Lum et al. (2019/0027436) and Molzer et al. (2015/0084194) as applied to claim 8 above, and further in view of Kim et al. (2024/0145345) . Regarding claim 14 , Kuo, Lum, and Molzer do not disclose that the through insulator via having the coaxial arrangement of the signal via having ground shielding about the perimeter of the signal via may be integrated with a power via that does not include ground shielding in the insulating region. However, Kim discloses a semiconductor device wherein the through insulator via having the coaxial arrangement of the signal via having ground shielding about the perimeter of the signal via may be integrated with a power via (par. 0058). Kim further teaches that such a power via should be in direct contact with the signal via (par. 0005). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Kuo with Kim in order to improve reliability and optimize space around the via. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M BRECHT whose telephone number is (571)272-9634. The examiner can normally be reached Mon-Fri: 7:30am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (572) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.M.B./Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817 Application/Control Number: 18/400,458 Page 2 Art Unit: 2817 Application/Control Number: 18/400,458 Page 3 Art Unit: 2817 Application/Control Number: 18/400,458 Page 4 Art Unit: 2817 Application/Control Number: 18/400,458 Page 5 Art Unit: 2817 Application/Control Number: 18/400,458 Page 6 Art Unit: 2817 Application/Control Number: 18/400,458 Page 7 Art Unit: 2817 Application/Control Number: 18/400,458 Page 8 Art Unit: 2817 Application/Control Number: 18/400,458 Page 9 Art Unit: 2817 Application/Control Number: 18/400,458 Page 10 Art Unit: 2817 Application/Control Number: 18/400,458 Page 11 Art Unit: 2817 Application/Control Number: 18/400,458 Page 12 Art Unit: 2817