DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-9, 11-14, and 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (US PG Pub 2022/0328647, hereinafter Liu).
Regarding claim 1, figures 43-44 of Liu disclose a semiconductor device comprising:
a gate structure (230) on a stack of channel layers (206);
a source/drain region (224) adjacent to the stack of channel layers;
an inner airgap spacer (580) positioned between channels in the stack of channel layers, wherein the inner airgap spacer separates the gate structure (230) from the source/drain region (224),
wherein the inner airgap spacer has a first side that is in contact (thermally) with the gate structure, and a second side that is in contact with the source/drain region; and
a backside interface layer (202) across a base of the inner airgap spacer.
Regarding claim 2, figures 43-44 of Liu disclose the gate structure (230) is a gate all around gate structure (¶ 46).
Regarding claim 3, figures 43-44 of Liu disclose a first side of the inner airgap spacer (580) is in contact with the gate structure (230), and a second side of the inner airgap spacer is in contact with the source/drain region (224).
Regarding claim 4, figures 43-44 of Liu disclose the source/drain region (224) is contacted by a frontside contact (290).
Regarding claim 6, figures 43-44 of Liu disclose a semiconductor device comprising:
a gate structure (230) on a stack of channel layers (206);
a source/drain region (224) adjacent to the stack of channel layers;
an inner airgap spacer (580, lowermost) positioned between channels in the stack of channel layers, wherein the inner airgap spacer separates the gate structure (230) from the source/drain region (224);
wherein the inner airgap spacer has a first side that is in contact (thermally) with the gate structure, and a second side that is in contact with the source/drain region;
a backside interface layer (202) across a base of the inner airgap spacer; and
a gate sidewall airgap spacer (580, uppermost) present on a sidewall of the gate structure (230) that is overlying the inner airgap spacer.
Regarding claim 7, figures 43-44 of Liu disclose the gate structure (230) is a gate all around gate structure (¶ 46).
Regarding claim 8, figures 43-44 of Liu disclose a first side of the inner airgap spacer (580) is in contact with the gate structure (230), and a second side of the inner airgap spacer is in contact with the source/drain region (224).
Regarding claim 9, figures 43-44 of Liu disclose the source/drain region (224) is contacted by a frontside contact (290).
Regarding claim 11, figures 43-44 of Liu disclose a semiconductor device comprising:
a gate structure (230) on a stack of channel layers (206);
a source/drain region (224) adjacent to the stack of channel layers;
an inner airgap spacer (580, lowermost) positioned between channels in the stack of channel layers, wherein the inner airgap spacer separates the gate structure (230) from the source/drain region (224);
wherein the inner airgap spacer has a first side that is in contact (thermally) with the gate structure, and a second side that is in contact with the source/drain region; and
a backside interface layer (202) across a base of the inner airgap spacer; and
a source/drain airgap spacer (550, second from bottom) present on a face of the source/drain region (224).
Regarding claim 12, figures 43-44 of Liu disclose the gate structure (230) is a gate all around gate structure (¶ 46).
Regarding claim 13, figures 43-44 of Liu disclose a first side of the inner airgap spacer (580) is in contact with the gate structure (230), and a second side of the inner airgap spacer is in contact with the source/drain region (224).
Regarding claim 14, figures 43-44 of Liu disclose the source/drain region (224) has a frontside contact (290).
Regarding claim 16, figures 43-44 of Liu disclose a semiconductor device comprising:
a gate structure (230) on a stack of channel layers (206);
a source/drain region (224) adjacent to the stack of channel layers;
an inner airgap spacer (580, lowermost) positioned between channels in the stack of channel layers, wherein the inner airgap spacer separates the gate structure (230) from the source/drain region (224);
wherein the inner airgap spacer has a first side that is in contact (thermally) with the gate structure, and a second side that is in contact with the source/drain region; and
a backside interface layer (202) extending from a base surface of the stack of channel layers (206) to a base surface of the source/drain region (224) to encapsulate the inner airgap spacer.
Regarding claim 17, figures 43-44 of Liu disclose the gate structure (230) is a gate all around gate structure (¶ 46).
Regarding claim 18, figures 43-44 of Liu disclose a gate sidewall airgap spacer (580, uppermost) is present on a sidewall of the gate structure (230) that is overlying the inner airgap spacer (580, lowermost).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 10, 15, and 19-25 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Xie et al. (US PG Pub 2023/0411466, hereinafter Xie).
Regarding claim 5, Liu does not explicitly disclose the source drain/region (224) is contacted a backside contact to a backside power distribution network.
In the same field of endeavor, figures 42-43 of Xie disclose a source drain/region (144) is contacted a backside contact (173) to a backside power distribution network (¶ 33).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a backside contact to contact the source/drain regions to a backside power distribution network as taught by Xie for the purpose of backside power delivery to operate the device (¶ 133).
Regarding claim 10, Liu does not explicitly disclose the source drain/region (224) is contacted by a backside contact to a backside power distribution network.
In the same field of endeavor, figures 42-43 of Xie disclose a source drain/region (144) is contacted by a backside contact (173) to a backside power distribution network (¶ 33).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a backside contact to contact the source/drain regions to a backside power distribution network as taught by Xie for the purpose of backside power delivery to operate the device (¶ 133).
Regarding claim 15, Liu does not explicitly disclose the source drain/region (224) has a backside contact to a backside power distribution network.
In the same field of endeavor, figures 42-43 of Xie disclose a source drain/region (144) has a backside contact (173) to a backside power distribution network (¶ 33).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a backside contact to contact the source/drain regions to a backside power distribution network as taught by Xie for the purpose of backside power delivery to operate the device (¶ 133).
Regarding claim 19, Liu does not explicitly disclose the source drain/region (224) has a backside contact to a backside power distribution network.
In the same field of endeavor, figures 42-43 of Xie disclose a source drain/region (144) has a backside contact (173) to a backside power distribution network (¶ 33).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a backside contact to contact the source/drain regions to a backside power distribution network as taught by Xie for the purpose of backside power delivery to operate the device (¶ 133).
Regarding claim 20, figures 43-44 of Liu disclose a semiconductor device comprising:
a gate structure (230) on a stack of channel layers (206);
source/drain regions (224) on opposing sides of the stack of channel layers;
inner airgap spacers (580, lowermost) positioned between channels in the stack of channel layers, wherein the inner airgap spacers separates the gate structure (230) from the source/drain regions (224);
a backside interface layer (202) extending from the stack of channel layers (206) to a first of the source/drain regions (224) across a base of the inner airgap spacers,
wherein the inner airgap spacer has a first side that is in contact (thermally) with the gate structure, and a second side that is in contact with the source/drain region.
Liu does not explicitly disclose a backside contact to a second of the source/drain regions.
In the same field of endeavor, figures 42-43 of Xie disclose a backside contact (173) to a second source/drain region (144).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a backside contact to a second of the source/drain regions as taught by Xie for the purpose of backside power delivery to operate the device (¶ 133).
Regarding claim 21, figures 43-44 of Liu disclose the gate structure (230) is a gate all around gate structure (¶ 46).
Regarding claim 22, figures 43-44 of Liu disclose a gate sidewall airgap spacer (580, uppermost) is present on a sidewall of the gate structure (230) that is overlying the inner airgap spacer (580, lowermost).
Regarding claim 23, figures 43-44 of Liu disclose a source/drain airgap spacer (580, middle) is present on a face of the source/drain regions (224).
Regarding claim 24, figures 43-44 of Liu disclose the source/drain region (224) has a frontside contact (290).
Regarding claim 25, Xie discloses the backside contact (173) is in contact with a backside power distribution network (¶ 33).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 6, 11, 16, and 20 have been considered but are moot in light of the new grounds of rejection set forth above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YU-HSI D SUN/Primary Examiner, Art Unit 2817
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