Prosecution Insights
Last updated: July 17, 2026
Application No. 18/400,682

Inductors Including Magnetic Films with Trenches

Non-Final OA §102§103
Filed
Dec 29, 2023
Examiner
CAMPBELL, SHAUN M
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Apple Inc.
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
760 granted / 1044 resolved
+4.8% vs TC avg
Moderate +8% lift
Without
With
+8.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
28 currently pending
Career history
1086
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
88.3%
+48.3% vs TC avg
§102
7.0%
-33.0% vs TC avg
§112
2.3%
-37.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1044 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Preliminary amendment, received 11/18/2025, has been entered. Claims 1-20 are presented for examination. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-5 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US Pub. No. 2004/0164836 A1), hereafter referred to as Wang. As to claim 1, Wang discloses an inductor for an IC (fig 3, 500; [0029]), comprising: a conductive trace (502); and one or more magnetic films (504; [0029]) surrounding a top, a bottom, and sides of the conductive trace (502), the one or more magnetic films including one or more trenches along a first path directly above a length of the conductive trace, and one or more trenches along a second path directly above a width of the conductive trace, to form a plurality of sections (see annotated fig 3 below). PNG media_image1.png 665 1062 media_image1.png Greyscale As to claim 2, Wang discloses the inductor of claim 1 (paragraphs above), wherein trenches of the one or more magnetic films pass completely through the one or more magnetic films between sections of the plurality of sections (fig 3, sections of magnetic film 504 are completely separated by the trenches). As to claim 3, Wang discloses the inductor of claim 1 (paragraphs above), wherein the one or more magnetic films include one or more trenches along a third path directly below the width of the conductive trace (fig 3, trench directly below conductive trace 502 shown along the 1st path shown in annotated figure 3 above), and one or more trenches along a fourth path directly below the length of the conductive trace (fig 3, trench directly below the length of conductive trace 502 shown along the 2nd path shown in annotated figure 3 above). As to claim 4, Wang discloses the inductor of claim 3 (paragraphs above), wherein the one or more trenches along the first path are aligned with the one or more trenches along the third path (1st path and third path thereunder are aligned), and wherein the one or more trenches along the second path are aligned with the one or more trenches along the fourth path (2nd path and fourth path thereunder are aligned). As to claim 5, Wang discloses the inductor of claim 3 (paragraphs above), wherein the one or more magnetic films include one or more trenches along a fifth path directly across a thickness of the conductive trace (fig 3, trench between sections 504 directly across the thickness of trace 502). As to claim 15, Wang discloses the inductor of claim 1 (paragraphs above), a second region of the conductive trace (fig 3, adjacent region of trace 502), wherein the one or more magnetic films (504) further include one or more trenches to form a second plurality of sections surrounding the second region (sections of 504 surrounding the second region of trace 502). Claim(s) 16-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Korman et al. (US Patent No. 5,609,946), hereafter referred to as Korman. As to claim 16, Korman discloses an inductor for an IC (figs 4-5A/B), comprising: a conductive trace (16); and one or more multi-layer stacks (12/14) surrounding a top, a bottom, and sides of the conductive trace (16), the one or more multi-layer stacks including layers of magnetic film separated from one another by layers of dielectric (18/20), the one or more multi-layer stacks further including one or more trenches along a path directly above at least one of a length or a width of the conductive trace to form a plurality of sections (fig 5A/B trenches 30 along length of trace 16). As to claim 17, Korman discloses the inductor of claim 16 (paragraphs above), wherein trenches of the one or more multi-layer stacks pass completely through the one or more multi-layer stacks between sections of the plurality of sections (fig 4, trenches 30). As to claim 18, Korman discloses the inductor of claim 16 (paragraphs above), wherein the one or more multi-layer stacks include one or more trenches along a path directly below at least one of the length or the width of the conductive trace (fig 4, trenches 30). As to claim 19, Korman discloses the inductor of claim 18 (paragraphs above), wherein the one or more trenches along the path directly above the conductive trace are aligned with the one or more trenches along the path directly below the conductive trace (fig 4, trenches 30). As to claim 20, Korman discloses the inductor of claim 18 (paragraphs above), wherein the one or more multi-layer stacks include one or more trenches along a fifth path directly across a thickness of the conductive trace (trenches along the path where 12 and 14 are connected). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 6-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Korman. As to claim 6, Wang discloses the inductor of claim 1 (paragraphs above), Wang does not disclose wherein a plurality of magnetic films surround the conductive trace. Nonetheless, Korman discloses an inductor device wherein either a single layer of magnetic film surrounds a conductive trace or a plurality of magnetic films surround the conductive trace (fig 1A for single layer and fig 4 for magnetic layers 12/14 surrounding conductive trace 16). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include a plurality of the magnetic films of Wang as taught by Korman since this will allow for more precise control of the inductance value of the component. As to claim 7, Wang in view of Korman disclose the inductor of claim 6 (paragraphs above). Korman further discloses wherein the plurality of magnetic films includes at least three layers of magnetic film (fig 4, three layers of 12/14). As to claim 8, Wang in view of Korman disclose the inductor of claim 6 (paragraphs above). Wang in view of Korman do not explicitly disclose wherein a first distance between layers of the plurality of magnetic films is less than a second distance between the plurality of magnetic films and the conductive trace. However, Korman shows that the first distance between layers of the plurality of magnetic films is less than a second distance between the plurality of magnetic films and the conductive trace in figure 4. It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the distances between the layers as shown in the figure of Korman since this will optimize the shielding of the conductive trace while preventing short circuit effects during manufacture. As to claim 9, Wang in view of Korman disclose the inductor of claim 6 (paragraphs above). Korman further discloses wherein trenches of the plurality of magnetic films pass completely through the plurality of magnetic films between sections of the plurality of sections (fig 4, trenches 30). As to claim 10, Wang in view of Korman disclose the inductor of claim 6 (paragraphs above). Korman further discloses wherein the plurality of magnetic films is under the bottom of the conductive trace, and further comprising: a second plurality of magnetic films wrapped around a side and the top the conductive trace (fig 4, 12 and 14). Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Sturcken et al. (US Pub. No. 2018/0302986 A1), hereafter referred to as Sturcken. As to claim 11, Wang discloses the inductor of claim 1 (paragraphs above), Wang does not disclose wherein the conductive trace and the one or more magnetic films are formed in a back-end-of-the-line (BEOL) build-up structure over a semiconductor substrate. Nonetheless, Sturcken discloses wherein a similar inductor is formed in a BEOL build-up structure over a semiconductor substrate (fig 3A, [0053]). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the thin film inductor structure of Wang in the BEOL build-up structure of Sturcken since forming the inductor by incorporation of the BEOL processes simplifies manufacture and improves integration of the inductor. Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Zhang et al. (US Pub. No. 2004/0178472 A1), hereafter referred to as Zhang. As to claim 12, Wang discloses the inductor of claim 1 (paragraphs above), Wang does not disclose wherein the conductive trace and the one or more magnetic films are formed in a die level redistribution layer (RDL). Nonetheless, Zhang discloses wherein a similar thin film inductor is formed in a die level RDL (figs 5A-B, [0052]). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the thin film inductor structure of Wang in the die level RDL of Zhang since this will allow for the size and shape of the inductor to be optimized. Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Tseng et al. (US Pub. No. 2024/0072023 A1), hereafter referred to as Tseng. As to claim 13, Wang discloses the inductor of claim 1 (paragraphs above), Wang does not disclose wherein the conductive trace and the one or more magnetic films are formed in a package level RDL coupled to a die. Nonetheless, Tseng discloses wherein a similar thin film inductor is formed in a package level RDL coupled to a die (fig 7D, thin film inductor 740, package level RDL with Die 760). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the thin film inductor structure of Wang in the package level RDL of Tseng since this will allow for the size and shape of the inductor to be optimized. Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Smeys et al. (US Pub. No. 2010/0213601 A1), hereafter referred to as Smeys. As to claim 14, Wang discloses the inductor of claim 1 (paragraphs above), Wang does not disclose wherein the conductive trace and the one or more magnetic films comprise a discrete integrated passive device (IPD) coupled to a discrete die. Nonetheless, Smeys discloses wherein a similar inductor comprises a discrete integrated passive device (IPD) coupled to a discrete die (fig 1, [0024]). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the thin film inductor structure of Wang in the discrete integrated passive device coupled to the discrete die as taught by Smeys since this allows for inductor to be placed in almost any position of the package. Pertinent Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent No. 11,430,606B2. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 6/16/2026
Read full office action

Prosecution Timeline

Dec 29, 2023
Application Filed
Jun 22, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
81%
With Interview (+8.2%)
2y 6m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1044 resolved cases by this examiner. Grant probability derived from career allowance rate.

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