DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 6.5.2026 and 9.17.2026 are being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) or 35 U.S.C. 102(a)(2) as being anticipated by Chiang et al. (of record, US 20210265508 A1).
Regarding claim 1, Chiang discloses an integrated circuit structure, comprising:
a first fin (106A4) laterally spaced apart from a second fin (106B1, Fig. 2N);
a dielectric anchor (120+122) laterally between and spaced apart (due to, at least, 118) from the first fin and the second fin (Fig. 2N);
a gate structure (136+138+144) over the first fin, over the second fin, and over the dielectric anchor (Fig. 2N), wherein the gate structure has a bottommost surface (of 136) above a bottommost surface (of 120; note dip in 120 in Fig. 2N) of the dielectric anchor, and wherein the bottommost surface of the gate structure is below an uppermost surface (of 122) of the dielectric anchor (Fig. 2N);
a first epitaxial source or drain structure (306) on the first fin (per Fig. 1C) at a side (per Fig. 1C) of the gate structure (Fig. 3D); and
a second epitaxial source or drain structure (another 306) on the second fin (per Fig. 1C) at the side (per Fig. 1C) of the gate structure (Fig. 3D), the second epitaxial source or drain structure laterally spaced apart from the first epitaxial source or drain structure, wherein the dielectric anchor (as 120 in Fig. 3D) is laterally between and spaced apart (due to 118) from the first epitaxial source or drain structure and the second epitaxial source or drain structure without an additional epitaxial source or drain structure intervening between the dielectric anchor (as 120 in Fig. 3D) and the first epitaxial source or drain structure or intervening between the dielectric anchor and the second epitaxial source or drain structure (Fig. 3D), and wherein a top (at 120) of the dielectric anchor is below a top (tip of 306) of the first epitaxial source or drain structure and a top of the second epitaxial source or drain structure.
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Regarding claim 2, Chiang discloses the integrated circuit structure of claim 1, further comprising: a gate cut plug (154) on the dielectric anchor (Fig. 2Q).
Regarding claim 3, Chiang discloses the integrated circuit structure of claim 1, wherein the dielectric anchor (120+122) has a top surface (topmost of 120) below a top(most) of the first fin and a top(most) of the second fin (Fig. 2N).
Regarding claim 4, Chiang discloses the integrated circuit structure of claim 1, wherein the dielectric anchor (120+122) has a top surface (top of 120) at a same level as a top (not topmost) of the first fin and a top (not topmost) of the second fin (Fig. 2Q).
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Regarding claim 5, Chiang discloses the integrated circuit structure of claim 1, wherein the dielectric anchor (120+122) has a top(most) surface (of 122) above a top (not most) of the first fin and a top (not most) of the second fin (Fig. 2N).
Regarding claim 6, Chiang discloses the integrated circuit structure of claim 1, wherein the first fin is above a first sub-fin (101), and the second fin is above a second sub-fin (another 101, Fig. 2N).
Regarding claim 7, Chiang discloses the integrated circuit structure of claim 1, wherein the dielectric anchor (120+122) is over a trench isolation structure (108+110, Fig. 2N).
Regarding claim 8, Chiang discloses an integrated circuit structure (Figs. 1C, 2N, 2Q and 3D; see annotations above), comprising:
a first semiconductor fin (106A4) laterally spaced apart from a second semiconductor fin (106B1);
a dielectric structure (120+122) laterally between and spaced apart (in part due to 118) from the first semiconductor fin and the second semiconductor fin;
a gate electrode (136+138+144) over the first semiconductor fin, over the second semiconductor fin, and over the dielectric structure (Fig. 2N), wherein the gate electrode has a bottommost surface (at 136) above a bottommost surface (at 120; note dip in 120, Fig. 2N) of the dielectric structure, and wherein the bottommost surface of the gate electrode is below an uppermost surface (at 122) of the dielectric structure (Fig. 2D);
a first source or drain structure (one 306) on the first semiconductor fin at a side of the gate electrode (Figs. 1C and 3D); and
a second source or drain structure (another 306) on the second semiconductor fin at the side of the gate electrode (Figs. 1C and 3D), the second source or drain structure laterally spaced apart from the first source or drain structure, wherein the dielectric structure (as 120 in Fig. 3D) is laterally between and spaced apart (due to 118) from the first source or drain structure and the second source or drain structure without an additional source or drain structure intervening between the dielectric anchor and the first source or drain structure or intervening between the dielectric anchor and the second source or drain structure, and wherein a top (at 120) of the dielectric structure is below a top (tips of 306) of the first source or drain structure and a top of the second source or drain structure (Fig. 3D).
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Regarding claim 9, Chiang discloses the integrated circuit structure of claim 8, further comprising: a gate cut plug (154) on the dielectric structure (Fig. 2Q).
Regarding claim 10, Chiang discloses the integrated circuit structure of claim 8, wherein the dielectric structure has a top surface (of 120) below a top(most) of the first semiconductor fin and a top(most) of the second semiconductor fin (Fig. 2N).
Regarding claim 11, Chiang discloses the integrated circuit structure of claim 8, wherein the dielectric structure has a top surface (of 120) at a same level as a top (not topmost) of the first semiconductor fin and a top (not topmost) of the second semiconductor fin.
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Regarding claim 12, Chiang discloses the integrated circuit structure of claim 8, wherein the first semiconductor fin is above a first sub-fin (one 101), and the second semiconductor fin is above a second sub-fin (another 101, Fig. 2N).
Regarding claim 13, Chiang discloses the integrated circuit structure of claim 8, wherein the dielectric structure is over a trench isolation structure (108/110, Fig. 2N).
Regarding claim 14, Chiang discloses (Figs. 1C, 2N, 2Q and 3D) an integrated circuit structure, comprising:
a first stack of nanowires (104x/106A4) laterally spaced apart from a second stack of nanowires (104x/106B1);
a dielectric anchor (120+122) laterally between and spaced apart (in part due to 118) from the first stack of nanowires and the second stack of nanowires;
a gate structure (136/138/144) over the first stack of nanowires, over the second stack of nanowires, and over the dielectric anchor (Fig. 2N), wherein the gate structure has a bottommost surface (at 136) above a bottommost surface (at 120; note dip in 120, Fig. 2N) of the dielectric anchor, and wherein the bottommost surface of the gate structure is below an uppermost surface (at 122) of the dielectric anchor (Fig. 2N);
a first epitaxial source or drain structure (one 306) on the first stack of nanowires at a side of the gate structure (Figs. 1C and 3D); and
a second epitaxial source or drain structure (another 306) on the second stack of nanowires at the side of the gate structure (Figs. 1C and 3D), the second epitaxial source or drain structure laterally spaced apart from the first epitaxial source or drain structure, wherein the dielectric anchor (as 120 in Fig. 3D) is laterally between and spaced apart from (due to 118) the first epitaxial source or drain structure and the second epitaxial source or drain structure (Fig. 3D) without an additional epitaxial source or drain structure intervening between the dielectric anchor and the first epitaxial source or drain structure or intervening between the dielectric anchor and the second epitaxial source or drain structure (Fig. 2N), and wherein a top of the dielectric anchor (as 120 in Fig. 3D) is below a top (tips) of the first epitaxial source or drain structure and a top of the second epitaxial source or drain structure (Fig. 3D).
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Regarding claim 15, Chiang discloses 6he integrated circuit structure of claim 14, further comprising: a gate cut plug (154) on the dielectric anchor (Fig. 2Q).
Regarding claim 16, Chiang discloses the integrated circuit structure of claim 14, wherein the dielectric anchor (120+122) has a top surface (at 120) below a top (most) of the first stack of nanowires and a top (most) of the second stack of nanowires (Fig. 2N).
Regarding claim 17, Chiang discloses the integrated circuit structure of claim 14, wherein the dielectric anchor has a top surface (at 120) at a same level as a top (not topmost) of the first stack of nanowires and a top (not topmost) of the second stack of nanowires.
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Regarding claim 18, Chiang discloses the integrated circuit structure of claim 14, wherein the dielectric anchor has a top surface (at 122) above a top of the first stack of nanowires and a top of the second stack of nanowires (Fig. 2N).
Regarding claim 19, Chiang discloses the integrated circuit structure of claim 14, wherein the first stack of nanowires is above a first sub-fin (one 101), and the second stack of nanowires is above a second sub-fin (another 101, Fig. 2Q).
Regarding claim 20, Chiang discloses the integrated circuit structure of claim 14, wherein the dielectric anchor is over a trench isolation structure (108/110).
Response to Arguments
Applicant's arguments filed 9.4.2026 have been fully considered but they are not persuasive.
Applicant alleges that the prior art of record fails to disclose or suggest “without an additional epitaxial source or drain structure intervening between the dielectric anchor and the first epitaxial source or drain structure or intervening between the dielectric anchor and the second epitaxial source or drain structure” as recited in claims 1, 8 and 14.
The examiner disagrees as the first and second fins/nanowires are now 106A4 and 106B1 such that there is no intervening epitaxial layer as claimed; also, the anchor/dielectric structure is now 120+122. See Figs. 2N and 3D annotated above multiple times.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/Primary Examiner, Art Unit 2818
