DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The 5/7/2026 "Reply" elects with traverse Species 4 and identifies as reading on claims 1-3, 21-22, and 24-26.
In the restriction requirement Examiner has set forth why the restriction requirement is proper. Applicant has not provided a basis for why the restriction is improper. Accordingly, the restriction requirement is maintained and Examiner has withdrawn claims 4-14 and 18 from further consideration as being drawn to a non-elected invention. See, for example, 37 CFR § 1.142(b).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 21-22, and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ker (US Pub. No. 2002/0122280).
Regarding claim 1, in FIG. 17, Ker discloses a device comprising: a first clamp circuit (PSCR_1) electrically connected between a first node (VDD) and a second node (Input PAD); and a second clamp circuit (NSCR_1) electrically connected between the second node and a third node (VSS), wherein the first clamp circuit comprises: a first silicon controlled rectifier (SCR) comprising a first region (P) of a first conductivity type (p-type) electrically connected to the first node, a second region (N-well) of a second conductivity type (n-type), a third region (P+/P-well) of the first conductivity type, and a fourth region (N) of the second conductivity type electrically connected to the second node; and a first gate electrode (VGP) over a channel region, wherein the channel region comprises a junction of the second region and the third region between the first region and the fourth region.
Regarding claim 2, in FIG. 17, Ker discloses a first resistor (Rp) electrically connected to the first gate electrode; and a first capacitor (Cp) electrically connected to the first gate electrode.
Regarding claim 3, in FIG. 17, Ker discloses that the second clamp circuit (NSCR_1) comprises a second SCR and a second gate electrode (VGN), wherein the first resistor is electrically connected between the first gate electrode and the first node, wherein the first capacitor is electrically connected between the first gate electrode and the second node, and wherein the device further comprises: a second capacitor (Cn) electrically connected between the second gate electrode and the second node; and a second resistor (Rn) electrically connected between the second gate electrode and the third node.
Regarding claim 21, in FIG. 17, Ker discloses a device comprising: a first clamp circuit (PSCR_1) electrically connected between a first node (VDD) and a second node (Input PAD); and a second clamp circuit (NSCR_1) electrically connected between the second node and a third node (VSS), wherein the first clamp circuit comprises: a first silicon controlled rectifier (SCR) comprising a first region (P) of a first conductivity type (p-type) electrically connected to the first node, a second region (N-well) of a second conductivity type (n-type), a third region (P+/P-well) of the first conductivity type, and a fourth region (N) of the second conductivity type electrically connected to the second node; and a first gate electrode (VGP) configured to form a channel in one of the second region and the third region according to an applied voltage in a channel region between the second region and the third region.
Regarding claim 22, in FIG. 17, Ker discloses a first resistor (Rp) electrically connected to the first gate electrode; and a first capacitor (Cp) electrically connected to the first gate electrode.
Regarding claim 26, in FIG. 4b, Ker discloses a device comprising: a first well (42) having a first conductivity type (n-type); a second well (40) configured to form a first junction with the first well and having a second conductivity type (p-type); a first region (52) in the first well and having the second conductivity type; a second region (46) in the second well and having the first conductivity type; and a gate electrode (VGP) over a channel region comprising the first junction between the first region and the second region (channel exists between anode and cathode).
Allowable Subject Matter
Claims 24-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 24, in FIGs. 4b and 17, Ker discloses that the second region (N-well/42) is a first well in a substrate (30), wherein the third region (P+) is a second well in the substrate, wherein the first region (P/52) is in the first well.
However the prior art failed to disclose or reasonably suggest the claimed device particularly characterized by the fourth region (N) being in the second well.
Regarding claim 25, in FIGs. 4b and 17, Ker discloses that the second region (N-well/42) is a first well in a deep well in a substrate (30), wherein the third region (P+) is a second well in the deep well, wherein the first region (P/52) is in the first well.
However the prior art failed to disclose or reasonably suggest the claimed device particularly characterized by the fourth region (N) being in the second well.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUCKER J WRIGHT/ Primary Examiner, Art Unit 2891
Prosecution Insights