DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The new title submitted 6/24/2026 is acknowledged and accepted by the Office.
Claim Objections
Claim 9 has been amended to overcome its objection of the last Office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "connected to both sides" in line 11. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, "connected to both sides" in line 11 will be interpreted to read as "connected to first and second sides". The rejection may be overcome by amending claim 1 as suggested or in similar fashion.
In Re claim 2-20, they are rejected due to their dependence from claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6, 10-13 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over ABE et al (US 2020/0243620 A1-of record, hereafter Abe) in view of Oda et al (US 2012/0147286 A1-of record, hereafter Oda) and Yoshii et al (US 2019/0278968 A1, hereafter Yoshii) and WANG et al (US 2015/0364527 A1, hereafter Wang).
Re claim 1, Abe discloses in FIG. 4 (with references to FIG. 2) a display panel, comprising:
a substrate (10; [0069]) including a first area (region comprising Rp/Gp/Bp/24i; [0055]) and a second area (region comprising LS; [0055]);
at least one light-emitting element (subpixels Rp/Gp/Bp; [0055]) disposed in the first area (region comprising Gp/Bp/Rp/24i) and configured (formed) to emit light (red/green/blue/infrared; [0041]); and
at least one light-sensing element (LS; [0055]) disposed in the second area (region comprising LS) and configured (formed) to sense (detect; [0055]) an infrared signal (infrared light; [0055]),
wherein the at least one light-sensing element (LS) comprises ([0034]):
a first pattern (portion of 13 directly contacting E1 and M; [0032] and [0034]) including a strain inducing material (inorganic SiOx and/or SiNx; [0037]) patterned (formed) into a non-flat shape (stepped portions) on the substrate (10);
a thin-film semiconductor (silicon or oxide semiconductor M; [0034]-[0035]) disposed on the first pattern (portion of 13 directly contacting E1 and M); and
a first connection electrode (E2; [0032]) and a second connection electrode (E3; [0032]) connected to first (left) and second (right) sides (ends) of the thin-film semiconductor (silicon or oxide semiconductor M), respectively.
Abe fails to disclose wherein the thin-film semiconductor (silicon or oxide semiconductor M) completely covers the non-flat shape (stepped portions) of the first pattern (portion of 13 directly contacting E1 and M), and wherein the first (E2) and second (E3) connection electrodes are disposed on the same layer as a pixel electrode of the at least one light-emitting element (subpixels Rp/Gp/Bp).
However,
A. Oda discloses in FIGS. 1-2 a display panel component comprising: at least one light-sensing element (132; [0045]) comprises: a first pattern (section II; [0052]) including a strain inducing material (inorganic SiOx and/or SiNx 103; [0045]; [0052] and [0063]) patterned into a non-flat shape (surface asperities; [0052]) on a substrate (101; [0045]); and a thin-film semiconductor (polysilicon 131; [0046] and [0068]) disposed on the first pattern.
And,
B. Yoshii discloses in FIG. 3 a display panel, comprising: wherein the thin-film semiconductor (silicon or oxide semiconductor 311; [0058] and [0060]) completely covers the non-flat shape (stepped portions) of the first pattern (portion of 451 directly contacting 331 and 311; [0062]) including a strain inducing material (inorganic silicon nitride or silicon oxide 451; [0064]).
And,
C. Wang discloses in FIG. 2 a display panel, comprising: wherein the first (173c; [0074]) and second (175c; [0074]) connection electrodes are disposed on the same layer (coplanar; [0080]) as a pixel electrode (190; [0080]) of the at least one light-emitting element (green pixel PXG; [0050]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Abe by, firstly, applying the asperities and thicknesses of the light-sensing element of Oda to the at least one light-sensing element of Abe, consequently, more light is absorbed in the thin-film semiconductor layer. As a result, light use efficiency is improved and thus the light detection sensitivity of the light-sensing element is improved (Oda; [0052]). And secondly, applying the concept of Yoshii of the thin-film semiconductor completely covering the non-flat shape of the first pattern, for increasing the detection area of the light-sensing element. And lastly, configuring the light-sensing element wherein the first and second connection electrodes are disposed on the same layer as a pixel electrode of the at least one light-emitting element, as disclosed by Wang, for thinner display panels and shorter detection paths between the light-emitting element and the light-sensing element.
Re claim 2, Abe discloses the display panel of claim 1, wherein the second area (region comprising LS) is a non-light emitting area (no Rp/Gp/Bp subpixels or 24i).
Re claim 3, Abe discloses the display panel of claim 1, further comprising: at least one redundant light-emitting element (repeated subpixels Rp/Gp/Bp) disposed in a corresponding manner (1x3 layout) to the at least one light-emitting element (subpixels Rp/Gp/Bp).
Re claim 4, Abe discloses the display panel of claim 1, wherein the first pattern (portion of 13 directly contacting E1 and M) includes an inorganic film inorganic SiOx and/or SiNx 103) or an organic film.
Re claims 5, Abe discloses the display panel of claim 1, wherein the first pattern (portion of 13 directly contacting E1 and M) has a convex shape (stepped upward) or a concave shape.
Re claim 6, Abe and Oda disclose the display panel of claim 1, wherein the first pattern (Oda: asperities) is one of a hemisphere shape, a cone shape (FIG. 2), and a pyramid shape (FIG. 2), as part of the improved light absorption of Oda discussed for claim 1.
Re claims 10-11, Abe discloses the display panel of claim 1, further comprising: an infrared ray emitter (24i; [0041]) emitting an infrared signal (700-1400 nm light; [0041]), wherein the at least one light-sensing element (LS) senses the emitted infrared signal (700-1400 nm light) reflected from an object (finger Fg; [0057]); and wherein the infrared signal (700-1400 nm light) has a wavelength of 1,100 nanometers or greater (1100-1400 nm light; [0041]).
Re claim 12, Abe and Oda disclose the display panel of claim 1, wherein the thin-film semiconductor (Oda: 131) has a thickness of 1 to 50 nanometers (Oda; [0065]), as part of the improved light absorption of Oda discussed for claim 1.
Re claim 13, Abe discloses the display panel of claim 1, wherein the thin-film semiconductor (M) includes silicon (amorphous or LTPS; [0035]).
Re claim 15, Abe discloses the display panel of claim 1, wherein each of the at least one light-emitting element (subpixels Rp/Gp/Bp) includes an organic light-emitting diode (OLED; [0041]).
Re claim 16, Abe discloses the display panel of claim 1, further comprising: a transistor (PT; [0033]) formed on the substrate (10) and configured to control an emission (visible light; [0041]) of the at least one light-emitting element (subpixels Rp/Gp/Bp); a first insulation layer (16; [0032]) formed on the substrate (10) and covering the transistor (PT); and a second insulation layer (18; [0032]) formed on the first insulation layer (16), wherein the at least one light-emitting element (subpixels Rp/Gp/Bp) comprises: a light-emitting pixel (OLEDs of subpixels Rp/Gp/Bp; [0041]) formed on the first insulation layer (16); and the pixel electrode (22; [0041]) connecting the light-emitting pixel (OLEDs of subpixels Rp/Gp/Bp) to the transistor (PT).
Re claim 17, Abe discloses the display panel of claim 16, wherein the at least one light-sensing element (LS) is formed on the substrate (10) and the first insulation layer (16) covers the at least one light-sensing element (LS), and wherein the first connection electrode (E2) passing through the first and second insulation layers (16/18) and connecting to a first side (left end) of the thin-film semiconductor (M) disposed on the first pattern (portion of 13 directly contacting E1 and M); and wherein the second connection electrode (E3) passing through the first and second insulation layers (16/18) and connecting to a second side (right end) of the thin-film semiconductor (M) disposed on the first pattern (portion of 13 directly contacting E1 and M).
Re claim 18, Abe discloses yhe display panel of claim 16, wherein the at least one light-sensing element (LS) is formed on (the lower surface) the first insulation layer (16), and the second insulation layer (18) covers (overlays) the at least one light-sensing element (LS), and wherein first connection electrode (E2) passing through the second insulation layer (18) and connecting to a first side (left end) of the thin-film semiconductor (M) disposed on the first pattern (portion of 13 directly contacting E1 and M); and wherein the second connection electrode (E3) passing through the second insulation layer (18) and connecting to a second side (right end) of the thin-film semiconductor (M) disposed on the first pattern (portion of 13 directly contacting E1 and M).
Re claims 19-20, Abe discloses the display panel of claim 1.
But, fails to explicitly disclose wherein the at least one light-emitting element (subpixels Rp/Gp/Bp) comprises first and second light-emitting elements arranged on the substrate (10) with one light-sensing element (LS) arranged between the first and second light-emitting elements; and wherein at least one redundant light-emitting element is further disposed between the first and second light-emitting elements.
However,
Abe discloses in the embodiment of FIG. 11 wherein the at least one light-emitting element (left/right subpixels Rp/Gp/Bp) comprises first and second light-emitting elements (left Bp and right Rp) arranged on the substrate (10) with one light-sensing element (LS) arranged between the first and second light-emitting elements (left Bp and right Rp); and wherein at least one redundant light-emitting element (middle Bp/Gp/Rp) is further disposed between the first and second light-emitting elements (left Bp and right Rp).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use the FIG. 11 configuration of Abe, wherein the at least one light-emitting element (subpixels Rp/Gp/Bp) comprises first and second light-emitting elements arranged on the substrate (10) with one light-sensing element (LS) arranged between the first and second light-emitting elements; and wherein at least one redundant light-emitting element is further disposed between the first and second light-emitting elements, which allows the light emission of visible light from the light-emitting emitting elements and the emission of infrared light from the infrared ray emitter to be controlled separately, which can reduce power consumption (Abe; [0072]).
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Abe and Oda and Yoshii and Wang as applied to claim 1 above, and further in view of MAITI et al (US 2022/0373751 A1-of record, hereafter Maiti).
Re claims 7, Abe discloses the display panel of claim 1.
But, fails to disclose wherein the non-flat shape (stepped portions) of the first pattern (portion of 13 directly contacting E1 and M) has a ratio of a height and a width in a range of 0.3 to 1 or 1 to 3.
However,
Maiti discloses in FIG. 3B a first pattern (320; [0035]) including a strain inducing material (Si) patterned into a non-flat shape (non-planarized; [0035]) on a substrate (301; [0029]); and a thin-film semiconductor (350; [0032] and [0035]) disposed on the first pattern (320), wherein the non-flat shape (non-planarized) of the first pattern (320) has a ratio of a height and a width in a range of 0.3 to 1 or 1 to 3 (0.44; [0035]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Abe by applying the concept of Maiti of a first pattern including a strain inducing material patterned into a non-flat shape (non-planarized) on a substrate, a thin-film semiconductor disposed on the first pattern, wherein the non-flat shape (non-planarized) of the first pattern (320) has a ratio of a height and a width in a range of 0.3 to 1 or 1 to 3, for inducing a tailorable strain in the thin-film semiconductor, lowering its bandgap for wavelengths of interest (Maiti; [0033]) and expanding the response of the at least one light-sensing element (Maiti; [0043]).
Re claims 8-9, Abe discloses the display panel of claim 1.
But, fails to disclose wherein the strain inducing material (inorganic SiOx and/or SiNx) of the first pattern (portion of 13 directly contacting E1 and M) induces a stress of 1% to 3%; and wherein the strain inducing material of the first pattern induces a stress in a uniaxial or biaxial manner.
However, Maiti would render these limitations obvious by its disclosure of uniaxial strains of greater than 10 percent ([0033] and [0045]), where an appropriate amount strain results in the bandgap reduction discussed for claim 1, through routine experimentation (MPEP § 2144.05), produced by an induced stress of 1% to 3% of the strain inducing material.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Abe and Oda and Yoshii and Wang as applied to claim 1 above, and further in view of CAI et al (US 2024/0386863 A1-of record, hereafter Cai).
Re claim 14, Abe discloses the display panel of claim 1, wherein each of the at least one light-emitting element includes a light-emitting diode (inorganic light-emitting diode; [0046]).
But, fails to disclose wherein each of the at least one light-emitting element includes a micro light-emitting diode chip.
However,
Cai discloses in FIG. 3b a display panel comprising: a non-visible light sensor (210; [0058]) comprising a P-I-N photosensitive diode chip (2102; [0058]) below a micro LED-based ([0095]) display module (10; [0095]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use the micro LED-based display of Cai, the light-emitting elements configured as diode chips, for the inorganic LEDs of Abe, as an equivalent source (MPEP § 2144.06) for producing visible light used for infrared light-sensing applications.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection relies on a reference combination not applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 10890761 B2; US 10861996 B2 and US 10488962 B2 disclose non-visible light sensor configurable in display panels without the ability to disclose alone or in combination the limitations of wherein the thin-film semiconductor completely covers the non-flat shape of the first pattern, and wherein the first and second connection electrodes are disposed on the same layer as a pixel electrode of the at least one light-emitting element as required for claim 1, as part of display panels with biometric recognition using a SWIR (Short-Wave Infrared Ray) signal which has less noise compared to an image using light of a visible-light ray or near infrared ray (NIR) wavelength.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC W JONES/Primary Examiner, Art Unit 2892
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