DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of species A, fig. 5, claims 1-20 in the reply filed on 4/23/26 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 15, 16 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai, US Publication No. 2009/0219669 A1.
In a first interpretation-
15. A semiconductor device, comprising (see figs. 6-7 and fig. 8 annotated below):
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a first electrode structure (601) on a substrate and including a first connection portion extending in a first direction (e.g. 601 is three-dimensional), parallel to an upper surface of the substrate, and first finger portions (e.g. first fingers annotated) extending from the first connection portion in a second direction, perpendicular to the first direction;
a second electrode structure (602) on the substrate and including a second connection portion extending in the first direction (e.g. 602 is three-dimensional), and second finger portions (e.g. second fingers annotated) extending from the second connection portion in the second direction and alternately arranged with the first finger portions; and
an insulating layer (e.g. insulating layer annotated; dielectric of MIM capacitor, para. [0042], [0044]) between the first electrode structure and the second electrode structure,
wherein the first electrode (601) structure includes first lines and first contacts (e.g. lines and contacts annotated) alternately stacked on each other in a third direction, perpendicular to the upper surface of the substrate,
the second electrode structure (602) includes second lines and second contacts (e.g. lines and contacts annotated) alternately stacked on each other in the third direction, and
the first and second lines and the first and second contacts are arranged at a first pitch on N levels among a plurality of levels in the third direction, and are arranged at a second pitch greater than the first pitch on M levels of the plurality of levels, wherein N is 3 or more, and M is less than N (e.g. first pitch and second pitch annotated). See Lai at para. [0001] – [0053], figs. 1-7.
16. The semiconductor device of claim 15, wherein the second pitch is twice or more than the first pitch (e.g. first pitch and second pitch annotated in fig. 8; also see fig. 3, para. [0036] – [0038]).
18. The semiconductor device of claim 15, wherein a lower surface of at least one of the second lines is covered with the insulating layer so that the at least one of the second lines is not connected to the second contacts (e.g. In fig. 8, where a contact is removed, the lower surface of the metal lines is covered with the insulating layer.)
Claim(s) 15-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai, US Publication No. 2009/0219669 A1.
In a second interpretation-
15. A semiconductor device, comprising (see figs. 6-7 and see fig. 8 annotated below):
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a first electrode structure (601) on a substrate and including a first connection portion extending in a first direction (e.g. 601 is three-dimensional), parallel to an upper surface of the substrate, and first finger portions (e.g. first fingers annotated) extending from the first connection portion in a second direction, perpendicular to the first direction;
a second electrode structure (602) on the substrate and including a second connection portion extending in the first direction (e.g. 602 is three-dimensional), and second finger portions (e.g. second fingers annotated) extending from the second connection portion in the second direction and alternately arranged with the first finger portions; and
an insulating layer (e.g. insulating layer annotated; dielectric of MIM capacitor, para. [0042], [0044]) between the first electrode structure and the second electrode structure,
wherein the first electrode (601) structure includes first lines and first contacts (e.g. lines and contacts annotated) alternately stacked on each other in a third direction, perpendicular to the upper surface of the substrate,
the second electrode structure (602) includes second lines and second contacts (e.g. lines and contacts annotated) alternately stacked on each other in the third direction, and
the first and second lines and the first and second contacts are arranged at a first pitch on N levels among a plurality of levels in the third direction, and are arranged at a second pitch greater than the first pitch on M levels of the plurality of levels, wherein N is 3 or more, and M is less than N (e.g. first pitch and second pitch annotated). See Lai at para. [0001] – [0053], figs. 1-7.
16. The semiconductor device of claim 15, wherein the second pitch is twice or more than the first pitch (e.g. first pitch and second pitch annotated in fig. 8; also see fig. 3, para. [0036] – [0038]).
17. The semiconductor device of claim 15, wherein a lower surface of at least one of the second contacts is covered with the insulating layer so that the at least one of the second contacts is not connected to the second lines (e.g. In fig. 8, where a line is removed, the lower surface of the contact is covered with the insulating layer.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-14 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai, US Publication No. 2009/0219669 A1 in view of Lee, KR 20220092822 A (see attached English machine translation).
Regarding claim 1:
Lai teaches the limitations as applied to claim 15 above.
Lai further teaches:
in the second finger portions, a lower surface of at least one of the second contacts is covered with an insulating layer so that the at least one of the second contacts is not connected to the second lines (e.g. In fig. 8, where a line is removed, the lower surface of the contact is covered with the insulating layer.)
Lai does not expressly teach:
1. A semiconductor device, comprising:
a first semiconductor structure including a substrate, circuit elements on the substrate, and a capacitor structure on the circuit elements; and
a second semiconductor structure including a plate layer on the first semiconductor structure, gate electrodes stacked to be spaced apart from each other in a first direction, perpendicular to an upper surface of the plate layer and sequentially stacked on the plate layer, and channel structures penetrating through the gate electrodes and extending in the first direction,
In an analogous art, Lee teaches:
1. A semiconductor device, comprising (see figs. 1-3):
a first semiconductor structure (PER) including a substrate (201), circuit elements (220) on the substrate, and a capacitor structure (e.g. capacitor electrodes 262, 263, 264, 265, 266) on the circuit elements; and
a second semiconductor structure (CELL) including a plate layer (101) on the first semiconductor structure, gate electrodes (130) stacked to be spaced apart from each other in a first direction, perpendicular to an upper surface of the plate layer and sequentially stacked on the plate layer, and channel structures (CH) penetrating through the gate electrodes and extending in the first direction, See Lee at pages 2-13.
Lai further teaches:
2. The semiconductor device of claim 1, wherein in the first finger portions, the first lines include first lower lines (e.g. bottom, first row), first intermediate lines (e.g. second row and/or third row), and first upper lines (e.g. fifth row), sequentially stacked on the substrate, and in the second finger portions, the second lines (e.g. fourth row) are on levels different from a level of the first intermediate lines (e.g. second row and/or third row), fig. 8.
3. The semiconductor device of claim 2, wherein in the second finger portions, the second lines include only second lower lines on the same level as a level of the first lower lines (e.g. In fig. 8, the bottom row comprises all lines or all contacts.) and second upper lines on the same level as a level of the first upper lines (e.g. In fig. 8, the top row comprises all lines or all contacts.)
4. The semiconductor device of claim 3, wherein in the first finger portions, the first contacts include first lower contacts connecting the first lower lines to the first intermediate lines, and first upper contacts connecting the first intermediate lines to the first upper lines, and in the second finger portions, the second contacts include second lower contacts connected to the second lower lines and second upper contacts connected to the second upper lines (In fig. 8, the first finger portions and the second finger portions comprise alternating lines and contacts.)
5. The semiconductor device of claim 4, wherein in the second finger portions, the insulating layer is between upper surfaces of the second lower contacts and lower surfaces of the second upper contacts (e.g. In fig. 8, where a line is removed, the insulating layer is between upper surfaces of the second lower contacts and lower surfaces of the second upper contacts.)
6. The semiconductor device of claim 2, wherein in the second connection portion, the second lines include second lower lines on the same level as a level of the first lower lines (e.g. bottom, first row), second intermediate lines on the same level as a level of the first intermediate lines (e.g. second row and/or third row), and second upper lines on the same level as a level of the first upper lines (e.g. top, fifth row), fig. 8.
Regarding claim 7:
In fig. 8, Lai teaches the first intermediate lines (e.g. second row and/or third row) are arranged at a second pitch where the line is removed.
Lai does not expressly teach “except for the first intermediate lines”.
However, it would have been obvious to one of ordinary skill in the art to form “wherein the first and second lines except for the first intermediate lines are arranged at a first pitch in the second direction, and the first and second contacts are arranged at the first pitch in the second direction” because in fig. 8:
The first lines and second lines comprise a first pitch in the second direction where the line is not removed (even though they may also comprise a second pitch);
The first and second contacts comprise the first pitch in the second direction where the contact is not removed (even though they may also comprise a second pitch); and
In fig. 5, there are plurality of rows that comprise a first pitch and no second pitch.
Regarding claim 8:
Lai is silent wherein the first pitch ranges from about 140 nm to about 240 nm.
However, Lai teaches the pitch is a result effective variable in fig. 3 to achieve the desired capacitance. See Lai at para. [0036] – [0038].
It would have been obvious to one having ordinary skill in the art to form wherein the first pitch ranges from about 140 nm to about 240 nm, since where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP § 2144.05, Obviousness of Ranges and Optimization of Ranges. (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
9. The semiconductor device of claim 7, wherein the first intermediate lines (e.g. second row and/or third row) are arranged at a second pitch greater than the first pitch (e.g. In fig. 8, where a line is removed the pitch is greater. Also see second pitch annotated in fig. 8)
10. The semiconductor device of claim 1, wherein each of the first contacts is on each of the first finger portions and each of the second contacts is on each of the second finger portions (e.g. In fig. 8, each of the first finger portions and the second finger portions comprise the contacts.), and the first and second contacts have a line shape extending in the third direction (e.g. In fig. 6, the contacts are three-dimensional quadrilateral shapes.)
11. The semiconductor device of claim 1, wherein in the first finger portions, the first lines include first lower lines (e.g. bottom, first row), first intermediate lines (e.g. second row and/or third row), and first upper lines (e.g. top, fifth row), sequentially stacked on the substrate,
in the second finger portions, the second lines include second lower lines (e.g. bottom, first row) on the same level as a level of the first lower lines, second intermediate lines (e.g. second row and/or third row) on the same level as a level of the first intermediate lines, and second upper lines (e.g. top, fifth row) on the same level as a level of the first upper lines, and
the first intermediate lines are only in some of the first finger portions, and the second intermediate lines are only in some of the second finger portions (e.g. In fig. 8, this occurs when some of the lines are removed.)
12. The semiconductor device of claim 1, wherein the capacitor structure further includes a dielectric layer (e.g. insulating layer annotated in fig. 8) between the first electrode structure and the second electrode structure.
13. The semiconductor device of claim 1, wherein the first electrode structure and the second electrode structure include a metal material (e.g. The electrodes form metal-insulator-metal capacitor, MIM at para. [0005].)
Regarding claim 14:
Lee further teaches:
14. The semiconductor device of claim 1, wherein (see fig. 1) the first semiconductor structure (PER) further includes an interconnection structure (290) horizontally spaced apart from the capacitor structure (e.g. capacitor electrodes 262, 263, 264, 265, 266) on the circuit elements (220) and including circuit interconnection lines (282, 284) and circuit contact plugs (274), and
at least some of the circuit interconnection lines (282, 284) are on the same level as a level of the first and second lines (e.g. of the capacitor 262, 264), and at least some of the circuit contact plugs are on the same level as a level of the first and second contacts (e.g. of the capacitor 263, 265), See Lee at pages 3 and 13.
Regarding claim 19:
Lai teaches this limitation as applied to claim 15 above.
Lai further teaches the added limitation:
some of the second lines and the second contacts (e.g. lines and contacts annotated) are vertically spaced apart from each other in the second finger portions (e.g. See fig. 8 annotated above, where a line and/or contact is removed they are vertically spaced apart from each other. See para. [0042] teaching that the lines and contacts can be removed in disclosure “If the number of metal layers and vias included in the first or second conductor bar is decreased (for example, removing metal layer 404), the thickness of the dielectric layer 405 is increased; and if the number of metal layers and vias included in the first or second conductor bar is increased (for example, adding metal layer and/or via layer connected to the first or second conductor bar), the thickness of the dielectric layer 405 is decreased.).)
Lai does not expressly teach:
19. A data storage system, comprising:
a semiconductor storage device including circuit elements on a substrate, memory cells, a capacitor structure, and an input/output pad; and
a controller electrically connected to the semiconductor storage device through the input/output pad and configured to control the semiconductor storage device,
In an analogous art, Lee teaches:
19. A data storage system, comprising (see figs. 1-3 and 12):
a semiconductor storage device including circuit elements (220) on a substrate, memory cells (CELL), a capacitor structure (e.g. capacitor electrodes 262, 263, 264, 265, 266), and an input/output pad (1110); and
a controller (1220) electrically connected to the semiconductor storage device through the input/output pad and configured to control the semiconductor storage device. See Lee at pages 2-13 and 24-26.
Lai further teaches:
20. The data storage system of claim 19, wherein the first and second lines and the first and second contacts are arranged at a first pitch on three levels of first to fourth levels in the third direction, and are arranged at a second pitch greater than the first pitch on one level of the first to fourth levels (e.g. first pitch and second pitch annotated in fig. 8; also see fig. 3, para. [0036] – [0038]).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Lai with the teachings of Lee (i) “…to provide a semiconductor device with the improved electrical characteristics and mass production” (e.g. :Lee at Abstract); and (ii) “In an electronic system that requires data storage, a semiconductor device capable of storing high-capacity data is in demand. Accordingly, a method for increasing the data storage capacity of a semiconductor device is being studied. For example, as a method for increasing the data storage capacity of a semiconductor device, a semiconductor device including memory cells arranged three-dimensionally instead of two-dimensionally arranged memory cells has been proposed.” (e.g. Lee at page 1).
Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Booth, US 8378450 B2. In figs. 1-5, Booth teaches interlevel metallization forming a capacitor.
Conclusion
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/Michele Fan/
Primary Examiner, Art Unit 2818 9 July 2026
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