Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species III, FIG. 3, claims 1-8, 10, and 12-23 in the reply filed on 06/24/2026 is acknowledged. The traversal is on the ground(s) that “Applicant traverses for the reason that no serious search and/or examination burden has been established. MPEP § 808.01(a) states in part, "A requirement for restriction is permissible if there is a patentable difference between the species as claimed and there would be a serious search and/or examination burden on the examiner if restriction is not required. See § MPEP 803 and § 808.02." MPEP § 808.01(a). The Restriction Requirement asserts that the application contains claims directed to patentably distinct species and lists each in the format of "Specie [Number]: FIG. [Number] schematically illustrates an example semiconductor device assembly according to [Number] embodiments." Restriction Requirement, p. 2. It subsequently asserts that the "species are independent or distinct because the reasons as listed above." Id. However, no such reasons are provided. The Restriction Requirement additionally asserts "[t]here is a search and/or examination burden for the patentably distinct species as set forth above." Id. at p. 3. Applicant respectfully disagrees. No reasons were provided and thus it was not established that there would be a serious search and/or examination burden on the examiner if restriction is not required. Thus, Applicant traverses this restriction requirement.”
This is not found persuasive because for example FIG. 3 is clearly different from FIG. 1-2, therefore, the serious search and/or examination burden is undue.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8, 10 and 12-23 is/are rejected under 35 U.S.C. 102(a)(1)/(2) as being anticipated by Chien (Pub. No.: US 2021/0296258).
Re claim 1, Chien, Figs. 24-25 teaches an electronic assembly comprising:
a base element comprising a base substrate (110) having a frontside (top) with active circuitry (106, ¶ [0035]) and a backside (bottom) opposite the frontside, a first bonding layer (126) disposed on the frontside of the base substrate and including a signal pad (top far left 906) to convey an electrical signal to the active circuitry on the frontside of the base substrate; and
a first functional element (104, Fig. 3A) comprising a first semiconductor substrate (114) having a frontside (bottom) with active circuitry and a backside (top) opposite the frontside, a second bonding layer (120) disposed on the frontside of the first semiconductor substrate (114), and a back surface of the first functional element having a first contact feature (112fs, Fig. 3A) to connect to power or ground, wherein the first bonding layer (126) is hybrid bonded to the second bonding layer (120).
PNG
media_image1.png
670
1188
media_image1.png
Greyscale
Re claim 2, Chien, Fig. 25 [as shown above] teaches the electronic assembly of Claim 1, further comprising an insulating material [IL] disposed along a side surface of the first functional element (104) and on the first bonding layer (126).
Re claim 3, Chien, Figs. 24-25 teaches the electronic assembly of Claim 2, wherein the insulating material comprises an inorganic dielectric (note that [IL] comprises 904 with silicon oxide material, [0052]).
Re claim 4, Chien, Fig. 25 [as shown above] teaches the electronic assembly of Claim 1, further comprising an interconnect structure (116/114) disposed on the back surface of the first functional element (104) and electrically connected to the first contact feature (112fs).
Re claim 5, Chien, Fig. 25 [as shown above] teaches the electronic assembly of Claim 4, wherein the interconnect structure comprises an intermediate interconnect layer and a global interconnect layer (116),
wherein the intermediate interconnect layer (114) is disposed near a back surface of the interconnect structure,
wherein the global interconnect layer (116) is disposed on the intermediate interconnect layer nearer to a front surface of the interconnect structure than the intermediate interconnect layer, and
wherein the intermediate interconnect layer is in electrical communication with the global interconnect layer.
Re claim 6, Chien, Fig. 25 [as shown above] teaches he electronic assembly of Claim 5, wherein the interconnect structure further comprises an input/output (IO) pad (112, [0052]) disposed near the front surface of the interconnect structure,
wherein the IO pad is in electrical communication with the global interconnect layer (116/114), and
wherein the IO pad (112) is exposed at the front surface of the interconnect structure.
Re claim 7, Chien, Fig. 25 [as shown above] teaches the electronic assembly of Claim 1, further comprising a second functional element (108 on the far right/[SFE]) comprising a second semiconductor substrate (114) having a frontside with active circuitry (bottom) and a backside opposite the frontside (top).
Re claim 8, Chien, Fig. 25 [as shown above] teaches the electronic assembly of Claim 7, wherein the second functional element [SFE] comprises a third bonding layer disposed on the frontside of the second semiconductor substrate (114), wherein the third bonding layer (120/118) is hybrid bonded to the first bonding layer (126).
Re claim 10, Chien, Fig. 25 [as shown above] teaches an electronic assembly comprising:
a base element comprising a base substrate (110) having a frontside (top) and a backside (bottom) opposite the frontside, a first bonding layer (126) disposed on the frontside of the base substrate;
a first functional element (104) comprising a first semiconductor substrate (114) having a frontside with active circuitry and a backside opposite the frontside, a second bonding layer (120) disposed on the frontside of the first semiconductor substrate, and a back surface of the first functional element comprising a first contact feature (112fs) to connect to power or ground; and
a second functional element [SFE] comprising a second semiconductor substrate (114) having a frontside with active circuitry and a backside opposite the frontside,
wherein the first bonding layer (126) is hybrid bonded to the second bonding layer (120) and the second semiconductor element (122/124) is hybrid bonded to the base element.
Re claim 12, Chien, Fig. 25 [as shown above] teaches the electronic assembly of Claim 10, wherein the frontside of the second functional element [SFE] is hybrid bonded to a front surface of the base substrate, and wherein a back surface of the second functional element [SFE] comprises a second contact feature (112bs) to connect to power or ground.
Re claim 13, Chien, Fig. 25 [as shown above] teaches the electronic assembly of Claim 10, further comprising an insulating material [SIL] disposed along a side surface of the first functional element (104) and on the first bonding layer.
Re claim 14, Chien, Fig. 25 [as shown above] teaches the electronic assembly of Claim 10, further comprising an interconnect structure (interconnect pads form within 116/114) disposed on the backside of the first semiconductor substrate (114) and electrically connected to the first contact feature (904).
Re claim 15, Chien, Fig. 25 [as shown above] teaches an electronic assembly comprising: an interconnect structure having one or more input/output (IO) pads;
a first functional element (104) comprising a first semiconductor substrate (114) having a frontside with active circuitry and a backside opposite the frontside, and a front surface of the first functional element having a first contact feature connected to the one or more IO pads (top 906); and
a second functional element [SFE] comprising a second semiconductor substrate (114) having a frontside with active circuitry and a backside opposite the frontside, and a back surface of the second functional element having a second contact feature connected to the one or more IO pads (bottom 906).
Re claim 16, Chien, Fig. 25 [as shown above] teaches the electronic assembly of Claim 15, further comprising a base element (910), wherein the first functional element (104) and the second functional element [SFE] are disposed on the base element.
Re claim 17, Chien, Fig. 25 [as shown above] teaches the electronic assembly of Claim 16, wherein the base element (110) further comprises a base substrate having a frontside with active circuitry and a backside opposite the frontside, a first bonding layer (126) disposed on the frontside of the base substrate and a signal pad (906) to convey an electrical signal to the active circuitry on the frontside of the base substrate.
Re claim 18, Chien, Fig. 25 [as shown above] teaches the electronic assembly of Claim 17, further comprising a second bonding layer (120) disposed on the frontside of the first semiconductor substrate, and a third bonding layer (126/124) disposed on the frontside of the second semiconductor substrate (122), wherein the first bonding layer (126) is hybrid bonded to the second bonding layer (120), and wherein the third bonding layer (126/124) is hybrid bonded to the first bonding layer (120).
Re claim 19, Chien, Fig. 25 [as shown above] teaches the electronic assembly of Claim 18, further comprising an insulating material [SIL] disposed along a side surface of the first functional element (104) and on the first bonding layer (126).
Re claim 20, Chien, Fig. 25 [as shown above] teaches the electronic assembly of Claim 19, wherein the insulating material comprises an inorganic dielectric (note that [SIL] comprises 904 with silicon oxide material, [0052]).
Re claim 21, Chien, Fig. 25 [as shown above] teaches the electronic assembly of Claim 15, wherein the interconnect structure (interconnect pads form within 116/114) disposed on the backside (bottom) of the second semiconductor substrate (114) and electrically connected to the second contact feature.
Re claim 22, Chien, Fig. 25 [as shown above] teaches the electronic assembly of Claim 21, wherein the interconnect structure comprises an intermediate interconnect layer and a global interconnect layer,
wherein the intermediate interconnect layer (interconnect pads form within 114) is disposed near a back surface of the interconnect structure,
wherein the global interconnect layer (interconnect pads form within 116) is disposed on the intermediate interconnect layer nearer to a front surface of the interconnect structure than the intermediate interconnect layer, and
wherein the intermediate interconnect layer is in electrical communication with the global interconnect layer.
Re claim 23, Chien, Fig. 25 [as shown above] teaches the electronic assembly of Claim 21, wherein the interconnect structure further comprises an input/output (IO) pad (904) disposed near the front surface of the interconnect structure, wherein the IO pad is in electrical communication with the global interconnect layer (interconnect pads form within 116), and wherein the IO pad is exposed at the front surface of the interconnect structure (interconnect pads form within 116/114).
Conclusion
The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure:
Delacruz et al. (Patent No.: US 11127738); Haba et al. (Pub. No.: US 2020/0294908); Kao et al. (Patent No.: US 11217478).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TONY TRAN/Primary Examiner, Art Unit 2893
Prosecution Insights