Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/401,185 filed on 12/29/2023.
Election/Restrictions
Applicant’s election with traverse of Group I (claims 1-18) in the reply filed on 04/24/2026 is acknowledged. Applicant further elected Species 2 including claims 1-6, 8-13, and 15-18 with traverse.
The requirement for election of species among the device embodiments is withdrawn. Therefore, claims directed to the previously identified device species will be examined on their merits.
The requirement for election of invention between Group I (Device) and Group II (Method), as set forth in the Office Action mailed 02/24/2026, is maintained. Applicant elected Group I (Device), and claims drawn to Group II (Method) remain withdrawn from further consideration by the examiner.
Applicant’s argument that the restriction requirement is improper because the product and process claims are classified in the same or overlapping classifications is not persuasive. This is not found persuasive because as set forth in the restriction requirement, Group I (Device) is classified in H10W90/00, whereas Group II (Method) is classified in H10W70/611. Thus, the claims are not classified identically.
Moreover, classification is not the sole basis for establishing a restriction requirement. As explained in the restriction requirement, the restriction between Groups I and II is based on the patentable distinctness of the claimed product and process. The device claims require that the first sub-package, the second sub-package, and the memory sub-package be arranged so as to overlap each other in a first direction, a limitation not required by the method claims.
Conversely, the method claims recite steps including electrically coupling the first sub-package to the second sub-package and electrically coupling the memory sub-package to at least one of the first sub-package or the second sub-package, limitations not required by the device claims. These differences demonstrate that the claimed product and process define materially different inventions and support the restriction requirement under MPEP § 806.05(f).
Accordingly, Applicant’s traversal has been considered but is not persuasive, and the restriction requirement between Group I and Group II is maintained.
The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Objections
Claims 12 and 16 objected to because of the following informalities:
Specifically, the word “the” is repeated in line 2 of claim 12 and in line 4 of claim 16.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 7, 9, 11-15 and 17-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US Pub # 2023/0065941 to Tsai et al. (Tsai).
Regarding independent claim 1, Tsai discloses a circuit assembly (Fig. 14) comprising:
a first sub-package comprising a first chiplet (Fig. 14: 200”) including an active frontside that comprises active circuitry (220B; it is noted that Applicant’s Specification defines the ‘active circuitry’ as including active electrical connection regions, for example, electrically conductive paths such as input/output paths. Therefore, under the broadest reasonable interpretation consistent with the Specification, the claimed ‘active circuitry’ is reasonably interpreted as encompassing electrically conductive paths.”) and faces in a first direction;
a second sub-package comprising a second chiplet (Fig. 14: 300) including an active frontside that comprises active circuitry (320) and faces in a second direction opposite the first direction; and
a memory sub-package (Fig. 14: 800) comprising a memory (820a or 820b), wherein the first sub-package (200”), the second sub-package (300), and the memory sub-package (800) are arranged so as to overlap (see Fig. 14) each other in the first direction.
Regarding claim 2, Tsai discloses wherein at least one of the first sub-package (Fig. 14: 200”) or the second sub-package comprises at least one redistribution layer (RDL) (S140).
Regarding claim 7, Tsai discloses wherein the active frontside (Fig. 14: active frontside is where 220B is formed) of the first sub-package (200) faces toward the active frontside (Fig. 14: active frontside is where 320 is formed) of the second sub-package (300).
Regarding claim 9, Tsai discloses wherein: the first sub-package (Fig. 14: 200”) comprises a frontside RDL (combinations of 192 and 342 are presently considered to be a frontside RDL) adjacent the active frontside (active frontside is where 220B is formed) of the first chiplet (200”); and the frontside RDL (combinations of 192 and 342) is electrically coupled to the active frontside (active frontside is where 220B is formed) of the first chiplet (200”).
Regarding claim 11, Tsai discloses wherein the active frontside (active frontside is where 220B is formed) of the first chiplet (200”) is electrically coupled to the active frontside (active frontside is where 320 is formed) of the second chiplet (300) by a plurality of vias (see Examiner’s Mark-up below) passing through the frontside RDL (combinations of 192 and 342) of the first sub-package (200”).
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Regarding claim 12, Tsai discloses a plurality of integrated passive devices (IPDs) (Fig. 26: 160 and 400; the semiconductor die 400 includes a semiconductor substrate 410 having semiconductor devices, where the semiconductor devices include passive devices (e.g., capacitors, resistors, inductors, etc.), see ¶0104) electrically mounted on at least one of the first sub-package (200”) or the second sub-package (300).
Regarding claim 13, Tsai discloses wherein at least one of the plurality of IPDs (Fig. 26: 400) is disposed between the memory sub-package (800) and at least one of the first sub-package (200) or the second sub-package.
Regarding claim 14, Tsai discloses wherein at least one of the plurality of IPDs (Fig. 26: 400) is disposed on a surface of at least one of the first sub-package (200) or the second sub-package (300) facing away from the memory sub-package (800).
Regarding claim 15, Tsai discloses a plurality of interconnects (¶0083 and 0087 such as 850, 120 and 194) electrically coupling (through the conductive pillars and the redistribution circuit structure 140) the memory sub-package (800) to at least one of the first sub-package (200) or the second sub-package (300).
Regarding independent claim 17, Tsai discloses a circuit assembly (Fig. 14) comprising:
a first sub-package comprising a first chiplet (Fig. 14: 200”) including an active frontside that comprises active circuitry (220B) and faces in a first direction;
a second chiplet (Fig. 14: 300) including an active frontside that comprises active circuitry (320) and faces in a second direction opposite the first direction; and
a memory sub-package (Fig. 14: 800) comprising a memory (820a or 820b), wherein the second chiplet (300) is positioned between the first sub-package (200”) and the memory sub-package (800).
Regarding claim 18, Tsai discloses wherein: the first sub-package (Fig. 14: 200”) comprises a frontside RDL (combinations of 192 and 342 are presently considered to be a frontside RDL) adjacent the active frontside (active frontside is where 220B is formed) of the first chiplet (200”); and
the active frontside (where 320 is formed) of the second chiplet (300) is electrically coupled to the active frontside (where 220B is formed) of the first chiplet (200”) by a plurality of vias (see Examiner’s Mark-up below) passing through the frontside RDL (combinations of 192 and 342) of the first sub-package.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3-5, 8 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2023/0065941 to Tsai et al. (Tsai) in view of US Pub # 2019/0259737 to Song et al. (Song).
Regarding claim 3, Tsai discloses all of the limitations of claim 2 from which this claim depends.
Tsai fails to teach wherein the first chiplet is electrically coupled to the second chiplet by the at least one RDL.
Song discloses wherein the first chiplet (110) is electrically coupled to the second chiplet (210) by the at least one RDL (150).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the memory sub-package of Tsai with the RDL as taught by Song in order to support the plurality of memory chips, and connect the memory chips to other memory chips and/or the inter-package connecting member (¶0030).
Regarding claim 4, Tsai discloses all of the limitations of claim 2 from which this claim depends.
Tsai fails to teach wherein the memory sub-package is electrically coupled to the first chiplet and the second chiplet by the at least one RDL.
Song teaches wherein the memory sub-package (Fig. 6: MP: 110) is electrically coupled to the first chiplet (210) and the second chiplet (311) by the at least one RDL (150).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the circuit assembly of Tsai with the RDL as taught by Song in order to support the plurality of memory chips, and connect the memory chips to other memory chips and/or the inter-package connecting member (¶0030).
Regarding claim 5, Tsai discloses all of the limitations of claim 1 from which this claim depends.
Tsai fails to teach discloses wherein each of the first sub-package and the second sub-package comprises at least one RDL.
Song discloses wherein each of the first sub-package (Fig. 6: 210) and the second sub-package (Fig. 6: 311) comprises at least one RDL (250 and 350).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the circuit assembly of Tsai with the RDL as taught by Song in order to support the controller chip, and connect the controller chip to an external connecting member and the inter-layer connecting member, and to support the buffer chip, and may connect the buffer chip to the inter-package connecting member and the inter-layer connecting member (¶0038 and 0041).
Regarding claim 8, Tsai discloses all of the limitations of claim 1 from which this claim depends.
Tsai fails to teach wherein the active frontside of the first sub- package faces away from the active frontside of the second sub-package
Song discloses wherein the active frontside (Fig. 6: 220) of the first sub- package (210) faces away from the active frontside (320) of the second sub-package (311).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2023/0065941 to Tsai et al. (Tsai) in view of US Pub # 2019/0259737 to Song et al. (Song) and further in view of US Pub # 2019/0035757 to Yu et al. (Yu).
Regarding claim 6, Tsai as previously modified discloses all of the limitations of claim 5 from which this claim depends.
Tsai as previously modified fails to discloses wherein the first chiplet is electrically coupled to the second chiplet by the at least one RDL of the first chiplet and the at least one RDL of the second chiplet.
Yu discloses wherein the first chiplet (880) is electrically coupled to the second chiplet (810) by the at least one RDL (RDL1) of the first chiplet (880) and the at least one RDL (RDL2) of the second chiplet (810).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the circuit assembly of Tsai with the RDLs as taught by YU in order to provides good planarity for the subsequently formed upper layers (¶0029).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2023/0065941 to Tsai et al. (Tsai) in view of US Pub # 20240234273 to Liu.
Regarding claim 16, Tsai discloses all of the limitations of claim 15 from which this claim depends. Tsai discloses wherein the plurality of interconnects spans, in the first direction (¶0083 and 0087).
Tsai fails to teach, a gap between the memory sub- package the first sub-package or the second sub-package; and at least one IPD is positioned within the gap.
Liu discloses a gap (Fig. 34 and ¶0065; a gap is between 74 and 126 where 156 is located) between the memory sub- package (130) the first sub-package or the second sub-package (126) and at least one IPD (Figs. 32-34: 156) is positioned within the gap (see Fig. 34).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the circuit assembly of Tsai with a gap and IPD as taught by Liu in order to bond the IPD to a reconstructed wafer (¶0065).
Allowable Subject Matter
Claims 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 10 recites:
“wherein the first sub-package further comprises a backside RDL adjacent a backside of the first chiplet that is opposite the active frontside of the first chiplet, wherein the backside RDL of the first sub-package is electrically coupled to the frontside RDL of the first sub-package by a plurality of vias.”
Each of the above recitations, interpreted in combination with all other limitations of the claim and all limitations of any claims they depend from, is not taught or rendered obvious by the prior art of record and are indicated as allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pat # 9,349,707 to Sun et al., US Pub # 2022/0077130 to Kim., US Pat # 11,842,986 to Ramin, and US Pat # 11,855,056 to Rad.
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/MOHSEN AHMADI/ Primary Examiner, Art Unit 2896
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