Prosecution Insights
Last updated: May 29, 2026
Application No. 18/401,195

SOLID STATE LIGHTING DEVICE WITH DIFFERENT ILLUMINATION PARAMETERS AT DIFFERENT REGIONS OF AN EMITTER ARRAY

Non-Final OA §102§DP
Filed
Dec 29, 2023
Priority
Jun 15, 2010 — continuation of 8550647 +5 more
Examiner
LEBENTRITT, MICHAEL
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology, Inc.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
916 granted / 993 resolved
+24.2% vs TC avg
Moderate +6% lift
Without
With
+6.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
15 currently pending
Career history
1019
Total Applications
across all art units

Statute-Specific Performance

§101
4.3%
-35.7% vs TC avg
§103
60.3%
+20.3% vs TC avg
§102
12.9%
-27.1% vs TC avg
§112
1.4%
-38.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 993 resolved cases

Office Action

§102 §DP
Notice of Pre-AIA or AIA Status The present application is being examined under the pre-AIA first to invent provisions. Claim Objections The numbering of claims is not in accordance with 37 CFR 1.126 which requires the original numbering of the claims to be preserved throughout the prosecution. When claims are canceled, the remaining claims must not be renumbered. When new claims are presented, they must be numbered consecutively beginning with the number next following the highest numbered claims previously presented (whether entered or not). Misnumbered claim 13 has been renumbered as claim 14. Information Disclosure Statement The information disclosure statement (IDS) submitted on 12/29/2023 was filed after the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States. Claim(s) 1- 16 is/are rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by Fujiwara et al, US 2012/0139445 A1. Fujiwara teaches: A solid state lighting (SSL) emitter system, comprising: a substrate (12, figure 16, para 69); and a plurality of SSL emitters (11) figure 16, para 165) arranged on the substrate in an array of perpendicular columns and rows, wherein spacing between adjacent rows decreases with distance from a center of the array. (see figure 15) Also figures 5-7, 15, 16 and 29-30. 2. The SSL emitter system of claim 1, wherein spacing between adjacent columns decreases with distance from a center of the array. (see figure 15) Also figures 5-7, 15, 16 and 29-30 3. The SSL emitter system of claim 1, wherein the spacing between adjacent rows decreases symmetrically with the distance from the center of the array. (see figure 15) Also figures 5-7, 15, 16 and 29-30 4. The SSL emitter system of claim 1, wherein the spacing between adjacent rows decreases asymmetrically with the distance from the center of the array. (see figures 11-14) 5. The SSL emitter system of claim 1, wherein each of the plurality of SSL emitters has a same shape. (see figure 15) Also figures 5-7, 15, 16 and 29-30 6. The SSL emitter system of claim 1, wherein each of the plurality of SSL emitters has a same size. (see figure 15) Also figures 5-7, 15, 16 and 29-30 7. A solid state lighting (SSL) emitter system, comprising: a substrate (#12 in Fig. 16 and in 1 [0069]) having a central region ("near the center" in [0165]) and a peripheral surface (“near the periphery”. figure 16, para 165) surrounding the central surface; a first plurality of SSL emitters (11) (represented as area 13C) arranged on the central surface in a first array of perpendicular columns and rows (Figure 15); and a second plurality of SSL emitters (11) (represented as area 13T) arranged on the peripheral surface in a first array of perpendicular columns and rows (figure 15), wherein a first coverage area ratio of the first plurality of SSL emitters to the central surface is less than a second coverage area ratio of the second plurality of SSL emitters to the peripheral surface. (see figure 15) Also figures 5-7, 15, 16 and 29-30 8. The SSL emitter system of claim 7, wherein each of the first plurality of SSL emitters (represented as area 13C) and each of the second plurality of SSL emitters (represented as area 13T) has a same emitter area. (see figure 15) Also figures 5-7, 15,and 29-30 9. The SSL emitter system of claim 7, wherein each of the first plurality of SSL emitters (represented as area 13C) has a same first emitter area each of the second plurality of SSL emitters (represented as area 13T) has a same second emitter area greater than the first emitter area. (see figure 15) Also figures 5-7, 15, and 29-30 10. The SSL emitter system of claim 7, wherein each of the first plurality of SSL emitters (represented as area 13C) has a same first shape. (see figure 15) Also figures 5-7, 15 and 29-30 11. The SSL emitter system of claim 7, wherein each of the second plurality of SSL emitters (represented as area 13T) has a same second shape. (see figure 15) Also figures 5-7, 15 and 29-30 12. A solid state lighting (SSL) emitter system, comprising: a substrate (#12 in Fig. 16 and in 1 [0069]) having a central region ("near the center" in [0165]) and a peripheral surface (near the periphery. Para 165) surrounding the central surface; a first plurality of SSL emitters (11) (represented as area 13C) arranged on the central surface in a first array of perpendicular columns and rows; and a second plurality of SSL emitters (11) (represented as area 13 T) arranged on the peripheral surface in a first array of perpendicular columns and rows, wherein a first spacing between adjacent rows of the first plurality of SSL emitters is greater than a second spacing between adjacent rows of the second plurality of SSL emitters. See Figure 8-14, 16 13. The SSL emitter system of claim 12, wherein each of the first plurality of SSL emitters and each of the second plurality of SSL emitters has a same emitter area. (see figure 15) Also figures 5-7, 15 and 29-30 13. [14] The SSL emitter system of claim 12, wherein each of the first plurality of SSL emitters has a same first emitter area each of the second plurality of SSL emitters has a same second emitter area greater than the first emitter area. (see figure 15) Also figures 5-7, 15 and 29-30 14. [15] The SSL emitter system of claim 12, wherein each of the first plurality of SSL (represented as area 13C) emitters has a same first shape. (see figure 15) Also figures 5-7, 15 and 29-30 15. [16]The SSL emitter system of claim 12, wherein each of the second plurality of SSL emitters (represented by 13C) has a same second shape. (see figure 15) Also figures 5-7, 15 and 29-30 Double Patenting The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 7-11 rejected on the ground of non-statutory double patenting as being unpatentable over claims 9-19 of U.S. Patent No 11.626,615. Although the claims at issue are not identical, they are not patentably distinct from each other because similar subject matter is claimed: 7. A solid state lighting (SSL) emitter system, comprising: a substrate having a central surface and a peripheral surface surrounding the central surface; a first plurality of SSL emitters arranged on the central surface in a first array of perpendicular columns and rows; and a second plurality of SSL emitters arranged on the peripheral surface in a first array of perpendicular columns and rows, wherein a first coverage area ratio of the first plurality of SSL emitters to the central surface is less than a second coverage area ratio of the second plurality of SSL emitters to the peripheral surface. Application No. 17/687,991 9. A solid state lighting (SSL) emitter system, comprising: a substrate having a central surface and a peripheral surface surrounding the central surface; a first radially symmetric plurality of SSL emitters disposed on the central surface; and a second radially symmetric plurality of SSL emitters disposed on the peripheral surface, wherein a first coverage area ratio of the first plurality of SSL emitters to the central surface is less than a second coverage area ratio of the second plurality of SSL emitters to the peripheral surface. Application No. 17/687,991 17. A solid state lighting (SSL) emitter system, comprising: a substrate having a central surface and a peripheral surface surrounding the central surface; a first plurality of SSL emitters spaced apart on the central surface with a radial symmetry about a central point of the central surface; and a second plurality of SSL emitters spaced apart on the peripheral surface with the radial symmetry about the central point, wherein a first coverage area ratio of the first plurality of SSL emitters to the central surface is less than a second coverage area ratio of the second plurality of SSL emitters to the peripheral surface. The difference is that in application ‘991 additionally claims “radially” symmetric SSL emitters or SSL emitters with radial symmetry, which is a species of the of the generic SSL emitters. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references teach similar inventions: JP 2007109692 A JP 4684073 B2 KR 101023716 B1 KR 101441984 B1 Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL LEBENTRITT whose telephone number is (571)272-1873. The examiner can normally be reached IFP Mon- Fri 8:30 am- 6 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. MICHAEL . LEBENTRITT Primary Examiner Art Unit 2893 /MICHAEL LEBENTRITT/Primary Examiner, Art Unit 2893
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Prosecution Timeline

Dec 29, 2023
Application Filed
May 20, 2026
Non-Final Rejection mailed — §102, §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
98%
With Interview (+6.1%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 993 resolved cases by this examiner. Grant probability derived from career allowance rate.

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