DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I and Species 1, claims 1-10, in the reply filed on June 8, 2026 is acknowledged.
Accordingly, claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 8, 2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 9, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, and 10 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Ohtsuka et al (US Pub 2008/0006875).
In re claim 1, Ohtsuka et al discloses a method of forming an integrated circuit (i.e. see at least Figures 12-18), comprising: forming a polysilicon layer (i.e. 19) having a first side (i.e. the inner side of the left-side) over a semiconductor substrate having a top surface; forming over the semiconductor substrate a first resist layer (i.e. 121) having a second side (i.e. the side on the right-hand) spaced apart from the first side; forming a diode well (i.e. 7 in Figure 13A, formed by implantation of dopants in Figure 12B and paragraph 0237 and subsequent anneal, see paragraph 0242) extending into the semiconductor substrate between the first side and the second side, the diode well having a first conductivity type (i.e. p-type); forming over the semiconductor substrate a second resist layer (i.e. 145, see Figure 18A, paragraph 0276) having a third side (i.e. facing the left-hand); and forming a diode terminal (i.e. n+ region 9 in Figure 18B formed by implantation and subsequent anneal, paragraphs 0276 and 0277) extending into the semiconductor substrate between the first side and the third side, the diode terminal having an opposite second conductivity type (i.e. n-type) and extending from the diode well along the top surface (i.e. although this feature may be intended to define a diode terminal laterally extending beyond the diode well, any point of the diode well, e.g. the lateral portion below 19 of the p-n junction between regions 7 and 9, can be seen as a starting point of diode well 7 from which the diode terminal extends).
In re claim 3, Ohtsuka et al discloses wherein the diode well is P-type and the diode terminal is N-type (i.e. see at least Figures 12-18).
In re claim 10, Ohtsuka et al discloses wherein an implant that forms the diode well also forms a DWELL of a transistor extending into the semiconductor substrate (i.e. see at least Figures 12-18, portions of transistors inherently comprising diodes are associated with diode elements).
Allowable Subject Matter
Claims 2 and 4-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY HO whose telephone number is (571)270-1432. The examiner can normally be reached 9AM - 5PM, Monday-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY HO/Primary Examiner, Art Unit 2817
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