DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. TW 112112981, filed on 04/07/2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/22/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In Claim 1, line 17 & 22, the recitation of “a first threshold value “ and “a second threshold value” are not clear since the first and second threshold values are not clearly defined. Clarification is needed.
In Claim 15 is rejected in the same manner as discussed in Claim 1 above.
For the purpose of the examining the examiner interprets the first and second threshold values are inherently feature.
Claim 15 recites the limitation "the sum" in lines 16-17 & lines 22-23. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of the examining the examiner read “the sum” as --a sum--.
Claims 2-14 & 16-20 are rejected due to their dependency.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 & 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (CN 111294001 A, of record, hereinafter, Liu).
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Regarding claim 1 as best understood:
Liu discloses in annotated Fig. 9, a rail-to-rail input stage circuit (annotated Fig. 9, stage A1) coupled to an output stage circuit (stage B1) comprising an output terminal (Out) whose voltage level is related to voltage levels of a first input terminal (Vin1) and a second input terminal (Vin2), wherein the rail-to-rail input stage circuit comprises:
a first current source (current source I1 / CS1) providing a first current;
a second current source (current source I2 / CS2) providing a second current;
a first P-type transistor (P1) coupled between the first current source (CS1) and the output stage circuit (stage B1) and coupled to the first input terminal (Vin1);
a second P-type transistor (PM2) coupled between the first current source (CS1) and the output stage circuit (stage B1) and coupled to the second input terminal (Vin2);
a first N-type transistor (NM1) coupled between the second current source (CS2) and the output stage circuit (stage B1) and coupled to the first input terminal (Vin1);
a second N-type transistor (NM2) coupled between the second current source (CS2) and the output stage circuit (stage B1) and coupled to the second input terminal (Vin2);
a first processing circuit (annotated Proc1) generating a third current (e.g. current from drain terminal of transistor NM3) based on a first control voltage (a voltage from transistor PM10) in response to the voltage level of the first input terminal (Vin) being higher than a first threshold value (inherently threshold voltage of transistor turn on / off), wherein a sum of currents passing through the first N-type transistor (NM1) and the second N-type transistor (NM2) is equal to a sum of the first current and the third current;
a second processing circuit (annotated Proc 2) generating a fourth current (current from drain terminal of transistor PM3) based on a second control voltage (a voltage from transistor NM10) in response to the voltage level of the first input terminal (Vin) being lower than a second threshold value (inherently threshold voltage of transistor turn / off), wherein a sum of currents passing through the first P-type transistor and the second P-type transistor is equal to a sum of the second current and the fourth current;
a first voltage adjustment circuit (annotated ADJ1) adjusting the first control voltage in response to the voltage level (input volage) of the first input terminal (Vin1) being higher than the first threshold value; and
a second voltage adjustment circuit (annotated ADJ1) adjusting the second control voltage in response to the voltage level (input voltage) of the first input terminal (Vin) being lower than the second threshold value.
Regarding claim 2:
Liu discloses in Fig. 9, wherein the first processing circuit (Proc1) comprises:
a first transistor (transistor PM5) coupled to the first current source (CS1); and
a first current mirror (transistors NM4 and NM3 form a mirror circuit) receiving the current passing through the first transistor, and generating the third current.
Regarding claim 3:
Liu discloses in Fig. 9, wherein: the first current mirror comprises a second transistor (transistor NM4) and a third transistor (NM3), the drain and the gate of the second transistor (NM4) are coupled (via NM11) to the drain of the first transistor (PM5), the gate of the third transistor (NM3) is coupled to the gate of the second transistor (NM4), and the drain of the third transistor (NM3) is coupled to the first N-type transistor (NM1).
Regarding claim 15 as best understood:
Liu discloses in annotated Fig. 9, an operational amplifier comprising:
an input stage circuit (stage A1) comprising:
a first current source (CS1) providing a first current;
a second current source (CS2) providing a second current;
a first P-type transistor (PM1) coupled between the first current source (CS1) and a first node (node p2) and coupled to a first input terminal (Vin1 terminal);
a second P-type transistor (PM2) coupled between the first current source (CS1) and a second node (node p1) and coupled to a second input terminal (Vin2 terminal);
a first N-type transistor (NM1) coupled between the second current source (CS2) and a third node (node n2) and coupled to the first input terminal (Vin1 terminal);
a second N-type transistor (NM2) coupled between the second current source (CS2) and a fourth node (node n1) and coupled to the second input terminal (Vin2 terminal);
a first processing circuit (annotate Proc1) generating a third current based on a first control voltage (a voltage from PM10) in response to the voltage level of the first input terminal (Vin1 terminal) being higher than a first threshold value (inherently, threshold voltage of transistors turn on / off), wherein the sum of currents passing through the first N-type transistor and the second N-type transistor is equal to the sum of the first current and the third current;
a second processing circuit (Proc2) generating a fourth current based on a second control voltage (a voltage from transistor NM10) in response to the voltage level of the first input terminal (Vin1 terminal) being lower than a second threshold value (inherently threshold voltage of transistor turn on and off), wherein the sum of currents passing through the first P-type transistor (PM1) and the second P-type transistor (PM2) is equal to the sum of the second current and the fourth current;
a first voltage adjustment circuit (ADJ1) adjusting the first control voltage in response to the voltage level of the first input terminal (Vin1 terminal) being higher than the first threshold value; and
a second voltage adjustment circuit (ADJ2) adjusting the second control voltage in response to the voltage level of the first input terminal (Vin1 terminal) being lower than the second threshold value; and
an output stage circuit (stage B1) generating an output voltage based on voltage levels of the first node (p2), the second node (p1), the third node (n2), and the fourth node (n1).
Regarding claim 16:
Liu discloses in Fig. 9, wherein: the first processing circuit (Proc1) comprises a first compensation transistor (transistor NM11) and a first current mirror (transistors NM4 and NM3 form a current mirror), the first compensation transistor is coupled to the first current source (CS1), and the first current mirror provides the third current based on the current passing through the first compensation transistor (NM11), and
the second processing circuit (Proc2) comprises a second compensation transistor (PM11)and a second current mirror (from by transistors PM4 and PM3), the second compensation transistor (PM11) is coupled (via transistor NM5) to the second current source (CS2), and the second current mirror provides the fourth current based on the current passing through the second compensation transistor (NM5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (CN 111294001 A, of record, hereinafter, Liu).
Regarding claim 19:
Liu discloses the limitations as applied in claim 15 except wherein the third current is three times the first current, the fourth current is three times the second current, and the first current is equal to the second current. It would have been obvious to one having ordinary skill in the art at the time the invention was made to set, chosen or characterized the third current is three times the first current, the fourth current is three times the second current, and the first current is equal to the second current, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Allowable Subject Matter
Claim 4-14, 17-18 & 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph and if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Reference US 7,170,347 B1 to Kindt.
Figs. 1 & 2 of Kindt discloses an amplifier circuit comprising differential input and differential output and wherein differential input stage comprising transistors PMOS M1, M2 and transistors NMOS M3, M4 and output terminal connected to output state (e.g., Summer circuit 104 of Fig. 1) and wherein differential pair Mn and M2 connects to a current source (e.g., transistor M5) and differential pair transistors M3 and M4 connected to a current source (e.g., transistor M6)
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
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