DETAILED ACTION
This action is responsive to the following: The amendments and arguments made in amendment filed on November 21, 2025.
Claims 1, 4-11, and 14-20 are pending. Claims 1 and 11 are independent. Claims 2-3 and 12-13 are cancelled by applicant.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed November 21, 2025 has been entered. Claim 1, 4-11, and 14-20 remain pending. Claims 2-3 and 12-13 are cancelled by applicant. Applicant’s amendment to claims overcome the objections set forth in the previous Non-Final Office Action mailed September 29, 2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5-7, 9-12, 15-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shim et al. (US 20160111165) in view of Tanzawa et al. (US 20040141378) and Stoller et al. (US 20220199163).
Regarding Independent method Claim 1 and independent flash memory device claim 11, Shim teaches a flash memory device with a block of memory cells controlled by a memory controller that is configured to perform the erase method /(see Figs. 1 & 2), and a method of erasing memory cells of a flash memory device (Fig. 1: 100), and the method comprising:
performing first erase (Fig. 11: S311) operation to erase a block of memory cells (Fig. 2: BLK1) of the flash memory device by applying an erase bias voltage (Fig. 3: Vers1) on the block of memory cells (Fig. 2: BLK1);
increasing the erase bias voltage (Fig. 3: Vers1) in a stepping manner (Fig. 3: Vers1-3)
performing a first post program operation (Fig. 10: post-PGM) for recovering overly erased memory cells of the block of memory cells (Fig. 2: BLK1) until the lower edge of the distribution of threshold voltages (Fig. 10: E2) of the block of memory cells (Fig. 2: BLK1) is higher than a post verify voltage (Fig. 10: Vvp);
performing a second erase operation (Fig. 11: S331) to erase the block of memory cells to determine whether an upper edge of the distribution of threshold voltages (Fig. 10: E2) of the block of memory cells (Fig. 2: BLK1) is lower than an erase high side verify voltage (Fig. 10: Vve); and
having determined that the block of memory cells (Fig. 2: BLK1) to have been completely erased after the distribution of threshold voltages of the block of memory cells is completely within the post verify voltage and the erase high side verify voltage (para 94 “The erase verification voltage Vve may be a voltage corresponding to the upper limit of a threshold voltage distribution of an erase state E.”; para 126 “The lower limit of the threshold voltage distribution of the second erase state E2 is higher than the program verification voltage Vvp.”).
However, Shim fails to teach that the cells are initially erased until a lower edge of a distribution of threshold voltages of the block of memory cells is lower than an erase low side verify voltage;
Tanzawa teaches an erase low side verify voltage (Fig. 14: EVTL) that is lower than the post verify voltage (Fig. 14: OEVT) to which the low end of the distribution of cells is erased. Additionally, Tanzawa explain, from Figure 14, that an erase operation may cause over-erased cells and thus a “convergence step” (or “weak program”) will be subsequently required to increase the lower limit of the threshold voltage distribution after block erase (see e.g., para. 107).
It would be advantageous to limit over erasure of cells during an erase process to be within above a certain threshold. As in some memories the criteria for erasing an entire block leaves many cells well past the post verify voltage. When cells are over erased far past the post verify voltage a more time consuming iterative process of post-programming cells, erasing, and verifying may ensue. Thus, it would make sense to limit the amount to which cells are erased past the post verify voltage in order to limit the time spent during post programming process increasing the threshold voltage to within an acceptable range.
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Tanzawa further teach the erase low side verify voltage (Fig. 14: EVTL) and the post verify voltage (Fig. 14: OEVT) are predetermined threshold voltages (see Fig. 14), and the post verify voltage (Fig. 14: OEVT; see para. 77: OEVT = ~0.5V) is higher than the erase low side verify voltage (Fig. 14: EVTL).
Shim teach incremental step pulse erase, which employs a “step increase” of the erase bias (see e.g., Fig. 3: ∆Vers). Shim does not mention any actual permissible voltage values of ∆Vers.
Tanzawa teach their “post verify voltage” (Fig. 14: OEVT) is 0.5V (see para. 77). Tanzawa does not expressly mention a voltage value for their “erase low side verify voltage” (Fig. 14: EVTL), but it is less than the post verify voltage and it is a small difference.
The claim requires the “voltage difference between the post verify voltage and the erase low side verify voltage” to be “less than a step increase of the erase bias voltage.” In other words, to teach the claim, Tanzawa’s OEVT minus EVTL must be less than Shim’s ∆Vers. Or in short,
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As indicated, Shim does not provide express information about their voltage increment ∆Vers.
However, Stoller explains an improved incremental step pulse erase operation, where their erase procedure tracks and retains the previously applied erase voltages for use as the starting erase voltage in subsequent erase operations, instead of using the same initial starting erase voltage (see para. 15-16). Stoller’s erase operation utilizes an erase optimizer (Fig. 1: 113) to track and retain optimum erase settings, such as the initial erase voltage (para. 34) and also an offset used to increment the erase voltage (para. 42). Stoller teaches the increment (or i.e., “step increase”) for the erase may be 0.522 volts or even a range of voltages from 0.005 to 1 volt (para. 40). Stoller provides specific disclosure to use of 0.522 volts as the “step increase” for the erase bias (see e.g., para. 40 and 43).
Stoller explains motivation to use their improved optimized erase operation through paragraph 14, by contrasting conventional erase operations that simply use higher erase voltages until the suitable erase voltage is found or a single large erase pulse, both of which result in excessive degradation of the NAND memory device. Stoller’s optimized erase operation addresses those deficiencies by progressively increasing an initial erase voltage value used to erase the memory cells (see para. 15) and also permits additional control on “step increase” to be a value between 0.01 volts to 1 volt, but especially 0.522 volts (see para. 15, 40, 43).
When the teachings of Stoller are combined with Shim and Tanzawa, the voltage difference between Tazawa’s “post verify voltage” (Tanzawa Fig. 14: OEVT = 0.5V) and Tanzawa’s “erase low side verify voltage” (Tanzawa Fig. 14: EVTL < 0.5V) is less than Stoller’s “step increase” of 0.522V or even 1V (Stoller, para. 15, 40, 43).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Stoller and Tanzawa to the combined teachings of Shim in order to produce a memory that performs post programming and a second erase only after the cells first erase which concludes when the cells have been erase passed a certain low side verification voltage, such that Stoller’s optimized erase operation is utilized with its step increment of 0.522V or 1V for the purpose, generally, of minimizing wear and degradation during an erase as compared to the excessive degradation caused by conventional erase operations without Stoller’s erase optimizer (see Stoller para. 14 and 15).
Regarding Claims 5 and 15, Shim, Tanzawa, and Stoller teach the limitations of claim 1 and 11, respectively. Tanzawa further teaches wherein the erase high side verify voltage (Fig. 14: EVT1) is a predetermined threshold voltage (para 222 “ In the potential generating circuit 22, internal power supply for erase verify E. V. is set up (in step ST63).”) which provides an erase margin from a reference voltage which is between the distribution of threshold voltages (Fig. 14: Vcc) of the block of memory cells which are to be erased (Fig. 14: EVT1, “1”) and a distribution of threshold voltages of another block of memory cells which are programmed (Fig. 14: PVT1, “0”).
Regarding Claims 6 and 16, Shim, Tanzawa, and Stoller teach the limitations of claim 2 and 12, respectively.
Tanzawa further teach the erase low side verify voltage (Fig. 14: EVTL) provides a margin from a level of threshold voltage at which a leakage current occurs (see para. 77, explaining that leak current occurs at a threshold voltage less than 0.5V, which OEVT is set, and EVTL is less than OEVT as illustrated in Fig. 14, which means EVTL is much less than 0.5V, which in turn means EVTL provides a “margin” from a threshold voltage at which leakage current occurs).
Regarding Claims 7 and 17, Shim, Tanzawa, and Stoller teach the limitations of claim 1 and 11, respectively.
Shim further teaches wherein increasing the erase bias voltage in the stepping manner until the lower edge of the distribution of threshold voltages of the block of memory cells is lower than the erase low side verify voltage comprising:
performing the first post program operation (Fig. 10: post-PGM) in response to the lower edge of the distribution of threshold voltages of the block of memory cells being lower than post verify voltage (Fig. 10: Vvp); and
increasing the erase bias voltage automatically by one voltage step (Fig. 10: Vers1-3).
Shim fails to teach a low side verification voltage.
Tanzawa teaches a low side verification voltage (Fig. 14: EVTL).
The rationale for combining Shim and Tanzawa is the same as Claim 1.
Regarding Claims 9 and 19, Shim, Tanzawa, and Stoller teach the limitations of Claim 1 and 11, respectively.
Shim further teaches wherein performing a first post program operation for recovering overly erased memory cells of the block of memory cells comprising:
adjusting a word line voltage (Fig. 9: WL, Vpgm1) which is connected to the bit line in an increasing manner (Fig. 9: Vpgm2) until a leakage current of the bit line is less than a predetermined threshold (Fig. 9: VvP).
However, Shim fails to teach setting the bit lines to a predetermined value during an erase.
Tanzawa teaches setting a bit line of the block of memory cells (Fig. 2: BLK1, BL) at a predetermined voltage (para 22 “The potential of a bit line BL to which a memory cell (selected cell), for which "0"-programming is conducted, is connected is set at Vss (e.g., 0V).”);
The rationale for combining the references is that same as claim 1.
Regarding Claims 10 and 20, Shim, Tanzawa, and Stoller teach the limitations of Claim 7 and 17, respectively. Tanzawa further teaches wherein determining whether the lower edge of the distribution of threshold voltages of the block of memory cells is lower than the erase low side verify voltage (Fig. 14: EVTL) comprising:
determine a bit line conducts current while setting the bit line at the erase low side verify voltage and setting each word line at a constant voltage (para 25 “the potential of the selected word line WL is set at, for example, Vcc (e.g., a potential of about 5V) and that of the unselected word line WL is set at, for example, Vss (e.g., 0V)”; para 27 “a current flows into the cell in the "1" state and the potential of the bit line BL to which this cell is connected is decreased to Vss. No current flows into the cell in the "0" state and the potential of the bit line BL to which this cell is connected, is, therefore, maintained Vd. Data read is executed if a sense amplifier senses the potential change of this bit line BL.”).
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Shim et al. (US 20160111165), Tanzawa et al. (US 20040141378), and Stoller et al. (US 20220199163) in further view of Choi (US 20020060929).
Regarding Claims 4 and 14, Shim, Tanzawa, and Stoller teaches the limitations of claim 1 and 11, respectively.
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Tanzawa teach the erase low side verify voltage (Fig. 14: EVTL, which is less than 0.5V because OEVT can be 0.5V), which is also at the lower edge of the distribution of threshold voltages for the erase state.
Each of Shim, Tanzawa and Stoller teach erase procedures that increment the erase bias. In this regard, Shim, Tanzawa, and Stoller are silent to using a constant voltage for the erase bias, as well as doing so in response to the lower edge of the threshold voltage distribution being less than the erase low side erase voltage.
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Choi, however, also teach an erase procedure utilizing incremental step pulse erase (see Fig. 8, noting the incremental bulk bias applied for erase; see also, para. 52). In Figure 8, after the pre erase verification passes, then the erase bias is held constant (see para. 50). In other word, Choi teaches changing the erase bias to constant in response to the pre erase verification operation passing. Choi shows in Figure 9B, illustrates the threshold voltage distribution of the cells after the pre-erase verification operation passes, and notably shows the lower end of the threshold voltage distribution touches the over-erased threshold voltage zone. In other words, Choi’s application of a constant erase bias coincides with both the passing of the pre-erase verification operation and the touching of the lower end of the threshold voltage distribution to the over-erased zone. Although Choi uses a pre-erase verification voltage on the upper end of threshold voltage distribution, the lower end of the threshold voltage distribution crosses the over-erased zone, which is also a zone Tanzawa expressed concern and utilized their erase low side verify voltage (Tanzawa Fig. 14: EVTL) and over-erase verify threshold voltage (Tanzawa Fig. 14: OEVT).
When combined with Tanzawa’s teachings to utilizing the erase low side verify voltage (Tanzawa Fig. 14: EVTL), Choi’s application of the constant erase bias is just as much in response to the passing of the pre-verification as it would have been “in response to the lower end of the distribution of threshold voltages of the block of memory cells being lower than the erase low side verify voltage.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Choi to the teachings of Shim, Tanzawa and Stoller (especially Tanzawa) such that the erase bias is kept constant (as taught by Choi in Fig. 9B) for the purpose of further improving an erase operation to reduce or minimize over-erased cells and reducing any subsequently required erase repair operations (see Choi para. 51).
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Shim et al. (US 20160111165) and Tanzawa et al. (US 20040141378) and Stoller et al. (US 20220199163), in view of Leung et al. (US 7020021).
Regarding Claims 8 and 18, Shim and Tanzawa teaches the limitations of claim 1 and 11, respectively. Shim further teaches wherein performing the second erase operation (Fig. 9: Vers2) to erase the block of memory cells (Fig. 2: BLK1) to determine whether the upper edge of the distribution of threshold voltages of the block of memory cells is lower than the erase high side verify voltage (Fig. 10: Vve) comprising:
determining whether the upper edge of the distribution of threshold voltages (Fig. 6: S222) of the block of memory cells is lower than the erase high side verify voltage (Fig. 10: Vve); and
performing a third erase operation (Fig. 9: Vers3; Fig. 6: S231) to erase the block of memory cells in response to the upper edge of the distribution of threshold voltages of the block of memory cells (Fig. 2: BLK1) being higher than the erase high side verify voltage (Fig. 10: Vve).
However, Shim and Tanzawa fail to teach a second program operation.
Leung Teaches a second program operation (Fig. 1: 123).
It stands to reason that when iteratively performing erase and post programming operations that it cells may become over erased on the erase operations following programming operations. Thus, subsequent post programming operations may need to be performed in order for the threshold voltages of the distribution to be within an acceptable range. Threshold voltages which are too low on erase cells can cause additional leakage and negatively impact idle power consumption in flash memories.
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Leung to the teachings of Shim and Tanzawa in order to produce a method of erasing a cell where after a first erase and post programming operation a second erase and second post programming operation occur.
Response to Arguments
Applicant's arguments filed November 21, 2025 have been fully considered but they are not persuasive.
The rejections under 35 U.S.C. under 103 are maintained under a new combination of references since the amendments incorporated dependent claims 3 and 13 in 1 and 11 respectively necessitating the addition of Stoller to come to an obviousness rejection.
Applicant principally argued against the basis for obviousness. The first argument dealt with claimed that the references cannot be combined the teachings of Shim and Tanzawa to show the obviousness of these references with respect to the rejections of claim 1. However, MPEP 2145(III) states that “’The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference.... Rather, the test is what the combined teachings of those references would have suggested to those of ordinary skill in the art.’” Since both Shim and Tanzawa deal with the same basic concepts of erasing non-volatile memory cell and correcting for over erasure it would be obvious to one of ordinary skill in the art to be able to combine these two references. Applicant states that “the erasure process of Shim is already complete and self-contained” however this could be said of any disclosed invention. Completeness and being self-contained do not preclude the ability to improve or modify beyond what is disclosed in the prior art. The rationale for combining as stated in the previous office action is that significantly over erasing cells can increase the time spent in post programming operations. And thus, limiting magnitude to which cells are over erased would represent an obvious improvement. Thus, the rationale to reject is maintained.
The second argument seemed to suggest that rationale for combining Stoller and Tanzawa with Shim represented impermissible hindsight on the part of the examiner. However, MPEP 2145 (X)(A) states “’Applicants may also argue that the combination of two or more references is "hindsight" because "express" motivation to combine the references is lacking. However, there is no requirement that an "express, written motivation to combine must appear in prior art references before a finding of obviousness.’” Stoller teaches a method of optimizing erase operations by adjusting the step size of erase voltages. The advantages of the Stollers smaller step size are provided in paragraph 14 of Stoller to reduce where and degradation. Thus, one of ordinary skill in the art would reasonably come to combining the references to produce a step size smaller than difference between the post verify and low side verify voltages. Therefore, the rejection is maintained.
Finally, applicant argued that The combination of Choi with the teachings of Tanzawa, Stoller, and Shim was not obvious because Choi fails to anticipate the exact feature in Claim 4. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). It is the combination of Choi with the other reference that represents obviousness. Though Choi teaches a verification voltage at the upper edge which is used to end the stepping of the erase voltage and keep it constant the other references teach verification voltages at the lower edge and using those verification voltages would represent and obvious combination. Therefore, the rejection is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/ Supervisory Patent Examiner, Art Unit 2825