DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1, 11 and 18.
Pending: 1-4, 6-7, 9-11, 13-23.
Canceled: 5, 8, 12.
Newly added: 21-23.
Response to Arguments
Applicant's arguments with respect to claims 1-4, 6-7, 9 and 10 have been considered but are moot in view of the new ground(s) of rejection.
Applicant’s arguments with respect to claims 11, 13-22, reference Su et al., fail to teach “wherein the gate electrode of the logic device has an upper surface substantially aligned with the upper surface of the first electrode and the upper surface of the second electrode.” However Examiner disagree, as shown in Su upper surface of the gate electrode (102, fig. 26) is substantially aligned (upper surface of 102 is approximately aligned same plane with upper surface of 54 and 104) with the upper surface of the first electrode (54 and 104, fig. 26), therefore, Su does teach this limitation. Applicant further argue that Su fail to teach “forming a sidewall spacer structure on a sidewall of the first electrode and the substrate, wherein the sidewall spacer structure laterally surrounds the first electrode removing a portion of the first electrode within an inner perimeter of the sidewall spacer structure to form a plurality of openings after the sidewall spacer structure is formed” however Examiner also disagree, Su teaches forming a sidewall spacer structure (52, fig. 12) on a sidewall of the first electrode (54 and 104, fig. 26) and the substrate (12, fig. 26), wherein the sidewall spacer structure (52, fig. 12) laterally surrounds the first electrode (54 and 104, fig. 26); removing a portion of the first electrode (54 and 104, fig. 26) within an inner perimeter of the sidewall spacer structure (52, fig. 12) to form a plurality of openings after the sidewall spacer structure (52, fig. 12) is formed. Therefore, Su does teach these limitation, and the rejection is maintained.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 11-12, 14, 16-19, and 22 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Su et al., US PG pub. 20080048232 A1.
Re: Independent Claim 11, Su discloses a substrate (12, fig. 26); a capacitor structure (54, 74 and 104, fig. 26) disposed on a first region of the substrate (12, fig. 26), wherein the capacitor structure (54, 74 and 104, fig. 26) comprises: a first electrode (54 and 104, fig. 26) having an top surface facing away from the substrate (12, fig. 26); and a second electrode (74, fig. 26) inset into the first electrode (54 and 104, fig. 26) and having an top surface substantially aligned with the top surface (surface under gate structure 104, fig. 26) of the first electrode (54 and 104, fig. 26); and a logic device comprising a gate electrode (102, fig. 26), wherein the gate electrode (102, fig. 26) of the logic device is located at an elevation, with respect to the substrate (12, fig. 26), substantially the same as that of the first electrode (54 and 104, fig. 26) of the capacitor structure (54, 74 and 104, fig. 26), and wherein the gate electrode (102, fig. 26) of the logic device has an upper surface substantially aligned (102 considerably aligned on the same plane with 54 and 104) with the upper surface of the first electrode (54 and 104, fig. 26) and the upper surface of the second electrode (74, fig. 26).
Re: Claim 12, Su disclose(s) all the limitations of claim 11 on which this claim depends. Su further discloses: wherein the top surface of the second electrode (74, fig. 26) of the capacitor structure (54, 74 and 104, fig. 26) has an elevation substantially the same as that of an top surface of the gate electrode (102, fig. 26).
Re: Claim 14, Su disclose(s) all the limitations of claim 11 on which this claim depends. Su further discloses: wherein the capacitor structure (54, 74 and 104, fig. 26) comprises a third electrode (114, fig. 26) electrically connected to the second electrode (74, fig. 26), and the second electrode (74, fig. 26) is located at an elevation different from that of the third electrode (114, fig. 26).
Re: Claim 16, Su disclose(s) all the limitations of claim 11 on which this claim depends. Su further discloses: a spacer structure (85 and spacer of 104, fig. 26) sandwiching the first electrode (54 and 104, fig. 26) and the second electrode (74, fig. 26).
Re: Claim 17, Su disclose(s) all the limitations of claim 11 on which this claim depends. Su further discloses: wherein the capacitor structure (54, 74 and 104, fig. 26) further comprises a capacitor dielectric (72, fig. 26) separating the first electrode (54 and 104, fig. 26) from the second electrode (74, fig. 26), and a portion of the first electrode (54 and 104, fig. 26) is disposed between the capacitor dielectric (72, fig. 26) and the substrate (12, fig. 26).
Re: Independent Claim 18, Su discloses providing a substrate (12, fig. 26); forming a first electrode (54 and 104, fig. 26) on the substrate (12, fig. 26);
forming a sidewall spacer structure (52, fig. 12) on a sidewall of the first electrode (54 and 104, fig. 26) and the substrate (12, fig. 26), wherein the sidewall spacer structure (52, fig. 12) laterally surrounds the first electrode (54 and 104, fig. 26);
removing a portion of the first electrode (54 and 104, fig. 26) within an inner perimeter of the sidewall spacer structure (52, fig. 12) to form a plurality of openings after the sidewall spacer structure (52, fig. 12) is formed; forming capacitor dielectric (72, fig. 26)s within the plurality of openings; and forming second electrodes (74, fig. 26) on corresponding capacitor dielectric (72, fig. 26)s, wherein the second electrodes (74, fig. 26) are electrically connected to each other.
Re: Claim 19, Su disclose(s) all the limitations of claim 18 on which this claim depends. Su further discloses: forming a logic device comprising a gate electrode (102, fig. 22) on the substrate (12, fig. 22); and planarizing (fig. 26) the first electrode (54 and 104, fig. 26), the capacitor dielectric (72, fig. 26)s, and the second electrodes (74, fig. 26) and the gate electrode (102, fig. 22) of the logic device concurrently (54, 104, 102 are alongside on the substrate 12).
Re: Claim 22, Su disclose(s) all the limitations of claim 18 on which this claim depends. Su further discloses: wherein the first electrode (54 and 104, fig. 26) is completely formed before the sidewall spacer structure (52, fig. 12) is formed.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 8-10, 13 and 23 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Su et al., US PG pub. 20080048232 A1; in view of Kim et al., US PG pub. 20210273042 A1.
Re: Independent Claim 1, Su discloses a substrate (12, fig. 26); and a capacitor structure (54, 74 and 104, fig. 26) disposed on the substrate (12, fig. 26), wherein the capacitor structure (54, 74 and 104, fig. 26) comprises: a first electrode (54 and 104, fig. 26); and a plurality of second electrodes (74, fig. 26), wherein at least one of the plurality of second electrodes (74, fig. 26) is embedded within the first electrode (54 and 104, fig. 26).
Su is silent regarding: wherein the capacitor structure overlies the substrate, and wherein a bottom surface of the first electrode and a bottom surface of the at least one of the plurality of second electrodes are elevated relative to a top surface of the substrate.
Kim discloses a capacitor structure (170, fig. 1) overlies the substrate (132, fig. 1) and wherein a bottom surface of the first electrode (171a, fig. 1) and a bottom surface of the at least one of the plurality of second electrodes (171D, fig. 1) are elevated relative to a top surface of the substrate (132, fig. 1).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include capacitor structure elevated relative to a top surface of the substrate since this can enables a greater reduction of dynamic noise (di/dt) and a greater reduction in voltage drop caused by the noise without increasing the size of the die.
Re: Claim 2, Su disclose(s) all the limitations of claim 1 on which this claim depends. Su further discloses: wherein a portion of the first electrode (54 and 104, fig. 26) is disposed between the one of the plurality of second electrodes (74, fig. 26) and the substrate (12, fig. 26).
Re: Claim 3, Su disclose(s) all the limitations of claim 1 on which this claim depends. Su further discloses: wherein a first thickness (thickness under the gate structure 104, fig. 26) of the first electrode (54 and 104, fig. 26) is greater than a second thickness (thickness under contact structure 112, fig. 26) of the one of the plurality of second electrodes (74, fig. 26).
Re: Claim 4, Su disclose(s) all the limitations of claim 1 on which this claim depends. Su further discloses: wherein the first electrode (54 and 104, fig. 26) has a top surface facing away from the substrate (12, fig. 26), and the top surface (surface under gate structure 104, fig. 26) of the first electrode (54 and 104, fig. 26) is substantially aligned with an top surface (surface under contact structure 112, fig. 26) of the at least one of the plurality of second electrodes (74, fig. 26).
Re: Claim 8, Su disclose(s) all the limitations of claim 1 on which this claim depends. Su further discloses: an isolation structure (11, fig. 26) within the substrate (12, fig. 26), wherein the isolation structure (11, fig. 26) is disposed between the substrate (12, fig. 26) and the capacitor structure (54, 74 and 104, fig. 26).
Re: Claim 9, Su disclose(s) all the limitations of claim 1 on which this claim depends. Su further discloses: wherein the capacitor structure (54, 74 and 104, fig. 26) further comprises: a first capacitor dielectric (52, fig. 26) disposed between the first electrode (54 and 104, fig. 26) and the substrate (12, fig. 26); and a second capacitor dielectric (72, fig. 26) separating the one of the plurality of second electrodes (74, fig. 26) from the first electrode (54 and 104, fig. 26).
Re: Claim 10, Su disclose(s) all the limitations of claim 9 on which this claim depends. Su further discloses: wherein the first electrode (54 and 104, fig. 26) has a plurality of parts physically separated from each other by the second capacitor dielectric (72, fig. 26).
Re: Claim 13, Su disclose(s) all the limitations of claim 11 on which this claim depends. Su is silent regarding: wherein the first electrode has a lower surface opposite to the upper surface of the first electrode, and the lower surface of the first electrode has an elevation between an elevation of an upper surface of the substrate and an elevation of a lower surface of the second electrode.
Kim discloses a capacitor structure (170, fig. 1) wherein the first electrode (171a, fig. 1) has a lower surface opposite to the upper surface of the first electrode (171a, fig. 1), and the lower surface of the first electrode (171a, fig. 1) has an elevation between an elevation of an upper surface of the structure (170, fig. 1) and an elevation of a lower surface of the second electrodes (171D, fig. 1).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include capacitor structure elevated relative to a top surface of the substrate since this can enables a greater reduction of dynamic noise (di/dt) and a greater reduction in voltage drop caused by the noise without increasing the size of the die.
Re: Claim 23, Su disclose(s) all the limitations of claim 1 on which this claim depends. Su further discloses: a sidewall spacer structure (52, fig. 26) on a sidewall of the first electrode (54 and 104, fig. 26), wherein the at least one of the plurality of second electrodes (74, fig. 26) has a top surface substantially level with a top surface of the sidewall spacer structure (52, fig. 26) and a top surface of the first electrode (54 and 104, fig. 26).
Claim(s) 20 and 21 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Su et al., US PG pub. 20080048232 A1;in view of Booth, Jr. et al., 20120068237 A1.
Re: Claim 20, Su discloses all the limitations of claim 18 on which this claim depends. Su further discloses: substrate (12, fig. 26) comprises active region below gate oxide layer 92 (¶0054).
Su is silent regarding: a first well region within the substrate (12, fig. 26), wherein the first well region has a first conductive type; forming a second well region surrounded by the first well region, wherein the second well region has a second conductive type different from the first conductive type; forming a doped region over the second well region, wherein the doped region has the first conductive type; and electrically connecting the doped region and the second electrodes (74, fig. 26).
Booth discloses in fig. 19 wherein the substrate (8) comprises a first well region (30A) having a first conductive type, a second well region (32A, 34A) surrounded by the first well region and having a second conductive type different from the first conductive type, and a doped region (16) over the second well region (32A, 34A) and having the first conductive type, and wherein the doped region (16) of the substrate (8) functions as another one of the plurality of second electrodes (16 second electrode of a capacitor).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include to show that Su active substrate could have a source/drain and channel region below the gate structure transistor structure since having an embedded trench capacitor in a transistor device can improve capacitance in smaller area.
Re: Claim 21, Su and Booth discloses all the limitations of claim 20 on which this claim depends. Booth further discloses in figure 19: forming a third well region (12) surrounded by the second well region (32A, 34A), wherein the third well region (12) has the second conductive type, and a dopant concentration of the third well region (12) is greater than that of the second well region (32A, 34A).
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Hsieh et al., US PG pub. 20160218172 A1”) Discloses a metal-insulator-metal (MIM) capacitor. In some embodiments, the MIM capacitor has a capacitor bottom metal (CBM) electrode arranged over a semiconductor substrate. The MIM capacitor has a high-k dielectric disposed over the CBM electrode and a capacitor top metal (CTM) electrode arranged over the high-k dielectric layer. The MIM capacitor has a dummy structure that is disposed vertically over the high-k dielectric layer and laterally apart from the CTM electrode. The dummy structure includes a conductive body having a same material as the CTM electrode.
* (“Yen et al., US Patent 8815679 B1”) discloses first and second multi-layer structures are formed within respective openings in at least one dielectric layer formed over a semiconductor substrate. The first multi-layer structure comprises a gate electrode, and the second multi-layer structure comprises a resistor and a first electrode of a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure is completed by forming a dielectric film on the at least one dielectric layer and forming a second electrode on the dielectric film.
Allowable Subject Matter
Claim(s) 6-7 and 15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re: Claim 6 (and its dependent claim(s) 7), the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: wherein the substrate comprises a first well region having a first conductive type, a second well region surrounded by the first well region and having a second conductive type different from the first conductive type, and a doped region over the second well region and having the first conductive type, and wherein the doped region of the substrate functions as another one of the plurality of second electrodes, and wherein the doped region is disposed below the bottom surface of the first electrode.
Re: Claim 15, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: wherein the substrate comprises a doped region functioning as the third electrode of the capacitor structure.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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