DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1, 11 and 18.
Pending: 1-20.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE INCLUDING TRENCH CAPACITOR WITH EMBEDDED ELECTRODES AND METHOD OF MANUFACTURING THE SAME.
Information Disclosure Statement
Applicant’s IDS(s) submitted on 2/12/2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 8-14 and 16-19 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Su et al., US PG pub. 20080048232 A1.
Re: Independent Claim 1, Su discloses a substrate (12, fig. 26); and a capacitor structure (54, 74 and 104, fig. 26) disposed on the substrate (12, fig. 26), wherein the capacitor structure (54, 74 and 104, fig. 26) comprises: a first electrode (54 and 104, fig. 26); and a plurality of second electrodes (74, fig. 26), wherein at least one of the plurality of second electrodes (74, fig. 26) is embedded within the first electrode (54 and 104, fig. 26).
Re: Claim 2, Su disclose(s) all the limitations of claim 1 on which this claim depends. Su further discloses: wherein a portion of the first electrode (54 and 104, fig. 26) is disposed between the one of the plurality of second electrodes (74, fig. 26) and the substrate (12, fig. 26).
Re: Claim 3, Su disclose(s) all the limitations of claim 1 on which this claim depends. Su further discloses: wherein a first thickness (thickness under the gate structure 104, fig. 26) of the first electrode (54 and 104, fig. 26) is greater than a second thickness (thickness under contact structure 112, fig. 26) of the one of the plurality of second electrodes (74, fig. 26).
Re: Claim 4, Su disclose(s) all the limitations of claim 1 on which this claim depends. Su further discloses: wherein the first electrode (54 and 104, fig. 26) has an upper surface facing away from the substrate (12, fig. 26), and the upper surface (surface under gate structure 104, fig. 26) of the first electrode (54 and 104, fig. 26) is substantially aligned with an upper surface (surface under contact structure 112, fig. 26) of the one of the plurality of second electrodes (74, fig. 26).
Re: Claim 5, Su disclose(s) all the limitations of claim 4 on which this claim depends. Su further discloses: wherein the first electrode (54 and 104, fig. 26) has a lower surface (surface above STI structure 11, fig. 26) opposite to the upper surface, and the lower surface of the first electrode (54 and 104, fig. 26) has an elevation, with respect to the substrate (12, fig. 26), different from that of a lower surface (surface formed on layer 72, fig. 26) of the one of the plurality of second electrodes (74, fig. 26).
Re: Claim 8, Su disclose(s) all the limitations of claim 1 on which this claim depends. Su further discloses: an isolation structure (11, fig. 26) within the substrate (12, fig. 26), wherein the isolation structure (11, fig. 26) is disposed between the substrate (12, fig. 26) and the capacitor structure (54, 74 and 104, fig. 26).
Re: Claim 9, Su disclose(s) all the limitations of claim 1 on which this claim depends. Su further discloses: wherein the capacitor structure (54, 74 and 104, fig. 26) further comprises: a first capacitor dielectric (52, fig. 26) disposed between the first electrode (54 and 104, fig. 26) and the substrate (12, fig. 26); and a second capacitor dielectric (72, fig. 26) separating the one of the plurality of second electrodes (74, fig. 26) from the first electrode (54 and 104, fig. 26).
Re: Claim 10, Su disclose(s) all the limitations of claim 9 on which this claim depends. Su further discloses: wherein the first electrode (54 and 104, fig. 26) has a plurality of parts physically separated from each other by the second capacitor dielectric (72, fig. 26).
Re: Independent Claim 11, Su discloses a substrate (12, fig. 26); a capacitor structure (54, 74 and 104, fig. 26) disposed on a first region of the substrate (12, fig. 26), wherein the capacitor structure (54, 74 and 104, fig. 26) comprises: a first electrode (54 and 104, fig. 26) having an upper surface facing away from the substrate (12, fig. 26); and a second electrode (74, fig. 26) inset into the first electrode (54 and 104, fig. 26) and having an upper surface substantially aligned with the upper surface (surface under gate structure 104, fig. 26) of the first electrode (54 and 104, fig. 26); and a logic device comprising a gate electrode (102, fig. 26), wherein the gate electrode (102, fig. 26) of the logic device is located at an elevation, with respect to the substrate (12, fig. 26), substantially the same as that of the first electrode (54 and 104, fig. 26) of the capacitor structure (54, 74 and 104, fig. 26).
Re: Claim 12, Su disclose(s) all the limitations of claim 11 on which this claim depends. Su further discloses: wherein the upper surface of the second electrode (74, fig. 26) of the capacitor structure (54, 74 and 104, fig. 26) has an elevation substantially the same as that of an upper surface of the gate electrode (102, fig. 26).
Re: Claim 13, Su disclose(s) all the limitations of claim 11 on which this claim depends. Su further discloses: wherein the first electrode (54 and 104, fig. 26) has a lower surface opposite to the upper surface (surface under gate structure 104, fig. 26) of the first electrode (54 and 104, fig. 26), and the lower surface of the first electrode (54 and 104, fig. 26) has an elevation, with respect to the substrate (12, fig. 26), different from that of a lower surface of the second electrode (74, fig. 26).
Re: Claim 14, Su disclose(s) all the limitations of claim 11 on which this claim depends. Su further discloses: wherein the capacitor structure (54, 74 and 104, fig. 26) comprises a third electrode (114, fig. 26) electrically connected to the second electrode (74, fig. 26), and the second electrode (74, fig. 26) is located at an elevation different from that of the third electrode (114, fig. 26).
Re: Claim 16, Su disclose(s) all the limitations of claim 11 on which this claim depends. Su further discloses: a spacer structure (85 and spacer of 104, fig. 26) sandwiching the first electrode (54 and 104, fig. 26) and the second electrode (74, fig. 26).
Re: Claim 17, Su disclose(s) all the limitations of claim 11 on which this claim depends. Su further discloses: wherein the capacitor structure (54, 74 and 104, fig. 26) further comprises a capacitor dielectric (72, fig. 26) separating the first electrode (54 and 104, fig. 26) from the second electrode (74, fig. 26), and a portion of the first electrode (54 and 104, fig. 26) is disposed between the capacitor dielectric (72, fig. 26) and the substrate (12, fig. 26).
Re: Independent Claim 18, Su discloses providing a substrate (12, fig. 26); forming a first electrode (54 and 104, fig. 26) on the substrate (12, fig. 26); removing a portion of the first electrode (54 and 104, fig. 26) to form a plurality of openings; forming capacitor dielectric (72, fig. 26)s within the plurality of openings; and forming second electrodes (74, fig. 26) on corresponding capacitor dielectric (72, fig. 26)s, wherein the second electrodes (74, fig. 26) are electrically connected to each other.
Re: Claim 19, Su disclose(s) all the limitations of claim 18 on which this claim depends. Su further discloses: planarizing (fig. 26) the first electrode (54 and 104, fig. 26), the capacitor dielectric (72, fig. 26)s, and the second electrodes (74, fig. 26).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 20 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Su et al., US PG pub. 20080048232 A1;in view of Booth, Jr. et al., 20120068237 A1.
Re: Claim 6, Su discloses all the limitations of claim 1 on which this claim depends. Su further discloses: wherein the substrate (12, fig. 26) comprises active region below gate oxide layer 92 (¶0054).
Su is silent regarding: wherein the substrate comprises a first well region having a first conductive type, a second well region surrounded by the first well region and having a second conductive type different from the first conductive type, and a doped region over the second well region and having the first conductive type, and wherein the doped region of the substrate functions as another one of the plurality of second electrodes.
Booth discloses in fig. 19 wherein the substrate (8) comprises a first well region (30A) having a first conductive type, a second well region (32A, 34A) surrounded by the first well region and having a second conductive type different from the first conductive type, and a doped region (16) over the second well region (32A, 34A) and having the first conductive type, and wherein the doped region (16) of the substrate (8) functions as another one of the plurality of second electrodes (16 second electrode of a capacitor).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include to show that Su active substrate could have a source/drain and channel region below the gate structure transistor structure since having an embedded trench capacitor in a transistor device can improve capacitance in smaller area.
Re: Claim 20, Su discloses all the limitations of claim 18 on which this claim depends. Su further discloses: substrate (12, fig. 26) comprises active region below gate oxide layer 92 (¶0054).
Su is silent regarding: a first well region within the substrate (12, fig. 26), wherein the first well region has a first conductive type; forming a second well region surrounded by the first well region, wherein the second well region has a second conductive type different from the first conductive type; forming a doped region over the second well region, wherein the doped region has the first conductive type; and electrically connecting the doped region and the second electrodes (74, fig. 26).
Booth discloses in fig. 19 wherein the substrate (8) comprises a first well region (30A) having a first conductive type, a second well region (32A, 34A) surrounded by the first well region and having a second conductive type different from the first conductive type, and a doped region (16) over the second well region (32A, 34A) and having the first conductive type, and wherein the doped region (16) of the substrate (8) functions as another one of the plurality of second electrodes (16 second electrode of a capacitor).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include to show that Su active substrate could have a source/drain and channel region below the gate structure transistor structure since having an embedded trench capacitor in a transistor device can improve capacitance in smaller area.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Juengling US patent 7807541 B2”) Discloses a container capacitor structure in which at least two container capacitors, e.g., an inner and outer container capacitor, are made concentric and nested with respect to one another. The nested capacitors are formed in one embodiment by defining a hole in a dielectric layer for the nested container capacitors in the vicinity of two capacitor contact plugs. An outer capacitor plate is formed by etching back poly 1 to leave it substantially on the vertical edges of the hole and in contact with one of the plugs. At least one sacrificial sidewall is formed on the poly 1, and poly 2 is deposited over the sidewalls to form an inner capacitor plate in contact with the other plug. The structure is planarized, the sacrificial sidewalls are removed, a capacitor dielectric is formed, and is topped with poly 3. Additional structures such as a protective layer (to prevent poly 1-to-poly 2 shorting) and a conductive layer (to strap the plugs to their respective poly layers) can also be used.
* (“Chuang et al., US patent 9679909 B2”) discloses a split-gate flash memory cell, and the resulting integrated circuit, are provided. A semiconductor substrate having memory cell and capacitor regions are provided. The capacitor region includes one or more sacrificial shallow trench isolation (STI) regions. A first etch is performed into the one or more sacrificial STI regions to remove the one or more sacrificial STI regions and to expose one or more trenches corresponding to the one or more sacrificial STI regions. Dopants are implanted into regions of the semiconductor substrate lining the one or more trenches. A conductive layer is formed filling the one or more trenches. A second etch is performed into the conductive layer to form one of a control gate and a select gate of a memory cell over the memory cell region, and to form an upper electrode of a finger trench capacitor over the capacitor region.
* (“Su et al., US PG pub. 20070296010 A1”) discloses a pick-up structure for DRAM capacitors and a DRAM process are described. A substrate with trenches therein is provided, wherein the trenches include a first trench and the sidewall of each of the trenches is formed with a dielectric layer thereon. A conductive layer is formed on the surfaces of the substrate and the trenches, and then a patterned photoresist layer is formed on the conductive layer filling in the trenches and further covering the first trench. The exposed conductive layer is removed to form bottom electrodes in the trenches, and then the patterned photoresist layer is removed. A capacitor dielectric layer is formed on each bottom electrode, and then top electrodes are formed on the substrate filling up the trenches. A contact is then formed on the bottom electrode in the first trench, electrically connecting the substrate via the bottom electrode.
* (“Chu et al., US patent 12154939 B2”) discloses a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.
Allowable Subject Matter
Claim(s) 7 and 15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re: Claim 7, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: wherein the substrate comprises a third well region with the second conductive type and surrounded by the second well region, and a dopant concentration of the third well region is greater than that of the second well region.
Re: Claim 15, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: wherein the substrate comprises a doped region functioning as the third electrode of the capacitor structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898