DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group II (claims 1-9, 12,17, and 20) in the reply filed on 4/22/26 is acknowledged. Further, applicant's election with traverse of Species 2 (claims 12-17, and 20) in the reply filed on 4/22/26 is acknowledged. The traversal is on the ground(s) that the applicant has given no reason. The requirement is still deemed proper, and therefore made FINAL. No claims have been withdrawn, and all claims currently in the application are being examined.
Drawings
The drawings are objected to because in paragraph [0067] of the specification, the applicant states a FIG. 4E; however, the Drawings filed 1/2/24 do not contain a FIG. 4E. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 26 is objected to because of the following informalities: in line 1, there appears to be an extra punctuation at the end of the line (i.e. “:.”). Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21, 22, and 29 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 21, and 22 recite the limitation "spacer element" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 29 recites the limitation "hybrid GaN/poly-SiC wafer" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In view of the 112 rejection above, claim(s) 12, 17, and 21 thru 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over You et al. US 2014/0073120 A1 in view of Weeks, Jr. et al. US 6,617,060 B2 in view of Kasai et al. US 2010/0210089 A1. You discloses (see, for example, Fig 1-5) a method, comprising: forming or providing a donor wafer structure including a gallium nitride (GaN) layer 21; bonding the GaN layer 21 of the donor wafer structure to a polycrystalline SiC (poly-SiC) wafer base 23; and performing a dividing process to remove a partial thickness of the GaN layer 21 to provide a hybrid GaN/poly-SiC wafer 21b/23 comprising a remaining portion of the GaN layer 21b bonded to the poly-SiC wafer base 23. In paragraph [0026], You discloses the layer 23 includes silicon carbide. You discloses the gallium nitride layer 23, but does not disclose the gallium nitride layer being formed on a donor wafer base. However, Weeks, Jr. discloses (see, for example, Fig. 1) a method comprising forming a structure including a gallium nitride layer 16 on a donor wafer base 12/14, and further states (see, for example, abstract) that such a structure lowers stress, and reduces the tendency of cracks in the gallium nitride material. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the donor wafer structure including a donor wafer base in order to lower stress, and reduce the tendency of cracks in the gallium nitride material.
You in view of Weeks, Jr. does not clearly disclose the SiC as polycrystalline. However, Kasai discloses (see, for example, paragraph [0063], and FIG. 3) a method comprising using single crystal or polycrystal including polycrystals of SiC for matching the substrate different in type to the thin film of GaN in coefficient of thermal expansion or contributing to reduced cost. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the SiC as polycrystalline in order to match the SiC to the GaN layer in coefficient of thermal expansion or contribute to reduced cost.
Regarding claim 17, see, for example, column 7, line 54 wherein Weeks, Jr. discloses the
donor wafer base 14 including silicon.
Regarding claim 21, and 22, see the 112 rejection above.
Regarding claim 23, see, for example, column 8, lines 66-67 wherein Weeks, Jr. discloses growing a gallium nitride material layer.
Regarding claim 24, see, for example, column 7, lines 54-55 wherein Weeks, Jr. discloses single-crystal silicon, and in FIG. 1 discloses a buffer layer 12.
Regarding claim 25, see, for example, column 4, lines 62-63 wherein Weeks, Jr. discloses the buffer layer 12 being AlxGa(1-x)N ( i.e. aluminum nitride).
Claim(s) 13, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over You et al. US 2014/0073120 A1 in view of Weeks, Jr. et al. US 6,617,060 B2 in view of Kasai et al. US 2010/0210089 A1 as applied to claims 12, 17, and 21-25 above, and further in view of Chung et al. US 2010/0301347 A1. You in view of Weeks, Jr. in view of Kasai does not disclose performing a pressing operation to further bond the remaining portion of the GaN layer to the poly-SiC wafer base. However, Chung discloses (see, for example, paragraph [0017]) a method comprising using thermal compression (i.e. pressing operation) to bond a semiconductor layer 2 to a wafer 8. It would have been obvious to one of ordinary skill in the art to perform a pressing operation to further bond the remaining portion of the GaN layer to the poly-SiC wafer base in order to enhance the bond rate, and make better and more uniform contact.
Regarding claim 14, see, for example, paragraph [0017] wherein Chan discloses using hot plates (i.e. press in thermal compression process) to compress the plurality of hybrid GaN/poly-SiC wafers. Further, You in view of Weeks, Jr. in view of Kasai in view of Chan does not clearly disclose forming a plurality of hybrid GaN/poly-SiC wafers, wherein respective hybrid GaN/poly- SiC wafers of the plurality of hybrid GaN/poly-SiC wafers comprise a respective remaining portion of a respective GaN layer bonded to a respective poly-SiC wafer base; and wherein the pressing operation comprises: loading the plurality of hybrid GaN/poly-SiC wafers in a press in a stacked arrangement; however, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, in order to make a plurality of hybrid GaN/poly-SiC wafers at a same time for saving processing time, and since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Further,
Claim(s) 15, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over You et al. US 2014/0073120 A1 in view of Weeks, Jr. et al. US 6,617,060 B2 in view of Kasai et al. US 2010/0210089 A1 as applied to claims 12, 17, and 21-25 above, and further in view of Ku et al. US 2025/0084561 A1. You in view of Weeks in view of Kasai does not disclose arranging a spacer element between adjacent hybrid GaN/poly-SiC wafers. However, Ku discloses (see, for example, fig. 8) arranging a spacer element 132 between adjacent wafers. It would have been obvious to one of ordinary skill in the art to arrange a spacer element between adjacent hybrid GaN/poly-SiC wafers in order to improve spacing between the wafers, and thereby improve flow between the wafers that increases growth rate, reduces defects, and improves crystal properties.
Regarding claim 16, You in view of Weeks, Jr. in view of Kasai in view of Ku does not
specifically disclose the spacer element having a lattice mismatch of at least 5% relative to both the GaN layer and the poly-SiC wafer base; however, it would have been obvious to one of ordinary skill in the art to have the spacer element having a lattice mismatch of at least 5% relative to both the GaN layer and the poly-SiC wafer base in order to minimize stress, and since it has been held that discovering an optimum value of a result effective value involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
In view of the 112 rejection, claim(s) 20, 29, and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Aktas et al. US 2019/0252186 A1 in view of Davis et al. 6,051,849. Aktas discloses (see, for example, FIG. 2A-2D) a method comprising forming a semiconductor wafer structure 220/240, wafer base 220 and a gallium nitride (GaN) layer 240, arranging a stencil 250, pattern of openings 252, performing a doping process 260, and dopant regions 246. The stencil 250 provides a pattern of physical openings 252 that act as a stencil for the subsequent formation of the dopant regions 246. Aktas does not disclose depositing additional GaN over the dopant regions in the GaN layer, the additional deposited GaN increasing a thickness of the GaN layer. However, Davis discloses (see, for example, FIG. 4) a method comprising a GaN layer 104 wherein the GaN layer 104 receives additional deposited GaN 108a that increases the thickness of the GaN layer 104. In column 2, lines 7-15, Davis discloses that the overgrown gallium nitride semiconductor layer is relatively defect-free and high performance microelecronic devices may be formed in the overgrown gallium nitride semiconductor layer. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to deposit additional GaN over the dopant regions in the GaN layer, the additional deposited GaN increasing a thickness of the GaN layer in order to expand the GaN layer with a relatively defect-free gallium nitride semiconductor layer for integrating more high performance microelectronic devices.
Regarding claim 29, see the 112 rejection above.
Regarding claim 30, Aktas in view of Davis does not specifically disclose performing
multiple iterations of forming dopant regions at different depths with the same stencil and the dopant regions having the same pattern; however, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to perform at least one iteration of the dopant region formation process comprises: performing a first iteration of the dopant region formation process to define first dopant regions at a first depth in the GaN layer performing a second iteration of the dopant region formation process to define second dopant regions at a second depth in the GaN layer; wherein the same stencil is used for both the first iteration and the second iteration of the dopant region formation process, such that the first dopant regions and the second dopant regions have the same pattern in order to evenly distribute the p-type conductivity throughout the GaN layer, and since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Claim(s) 26, and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over You et al. US 2014/0073120 A1 in view of Weeks, Jr. et al. US 6,617,060 B2 in view of Kasai et al. US 2010/0210089 A1 as applied to claims 12, 17, and 21-25 above, and further in view of Fujiwara et al. US 2013/0161647 A1. You in view of Weeks, Jr. in view of Kasai does not disclose forming the poly-SiC wafer base by: performing a pressing operation on a volume of silicon carbide (SiC) powder to form a polycrystalline SiC (poly-SiC) ingot; dividing the poly-SiC ingot into a plurality of poly-SiC wafer bases. However, Fujiwara discloses (see, for example, paragraph [ 0054]) a method comprising using a SiC powder to form a SiC ingot, and the use of pressure (i.e. pressing operation) in the crucible in forming the ingot. In paragraph [0053], Fujiwara discloses slicing, and in FIG. 2 shows a plurality of poly-SiC wafer bases. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to form the poly-SiC wafer base by: performing a pressing operation on a volume of silicon carbide (SiC) powder to form a polycrystalline SiC (poly-SiC) ingot; dividing the poly-SiC ingot into a plurality of poly-SiC wafer bases in order to more efficiently manufacture the ingot, and increase the production yield from the same ingot to make a plurality of wafer bases at the same time.
Regarding claim 27, see, for example, paragraph [0055] wherein Fujiwara discloses using
different ratio of Al in the Al/B ratio in forming the substrates. Further, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to
use different quantities of SiC powder having different dopant characteristics to form the poly-SiC ingot, such that respective poly-SiC wafer bases of the plurality of poly-SiC wafer bases exhibit different dopant characteristics in order to form wafers able to form devices according to the preferences of the user as a matter of obvious design choice.
Claim(s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over You et al. US 2014/0073120 A1 in view of Weeks, Jr. et al. US 6,617,060 B2 in view of Kasai et al. US 2010/0210089 A1 as applied to claims 12, 17, and 21-25 above, and further in view of Aktas et al. US 2019/0252186 A1, and further in view of Davis et al. 6,051,849. You in view of Weeks, Jr. in view of Kasai does not disclose performing at least one iteration of a dopant region formation process in the hybrid GaN/poly-SiC wafer, wherein a respective iteration of the dopant region formation process includes: arranging a stencil on a first side of the hybrid GaN/poly-SiC wafer, the stencil including a pattern of openings; performing a doping process through the pattern of openings in the stencil to form dopant regions in the GaN layer of the hybrid GaN/poly-SiC wafer; and depositing additional GaN over the dopant regions in the GaN layer, the additional deposited GaN increasing a thickness of the GaN layer. However, Aktas discloses (see, for example, FIG. 2A-2D) a method comprising forming a semiconductor wafer structure 220/240, wafer base 220 and a gallium nitride (GaN) layer 240, arranging a stencil 250, pattern of openings 252, performing a doping process 260, and dopant regions 246. The stencil 250 provides a pattern of physical openings 252 that act as a stencil for the subsequent formation of the dopant regions 246. It would have been obvious to one of ordinary skill in the art to perform at least one iteration of a dopant region formation process in the hybrid GaN/poly-SiC wafer, wherein a respective iteration of the dopant region formation process includes: arranging a stencil on a first side of the hybrid GaN/poly-SiC wafer, the stencil including a pattern of openings; performing a doping process through the pattern of openings in the stencil to form dopant regions in the GaN layer of the hybrid GaN/poly-SiC wafer in order to form multiple doped regions in the GaN layer at the same, minimizing processing time.
You in view of Weeks, Jr. in view of Kasai in view of Aktas does not disclose depositing additional GaN over the dopant regions in the GaN layer, the additional deposited GaN increasing a thickness of the GaN layer. However, Davis discloses (see, for example, FIG. 4) a method comprising a GaN layer 104 wherein the GaN layer 104 receives additional deposited GaN 108a that increases the thickness of the GaN layer 104. In column 2, lines 7-15, Davis discloses that the overgrown gallium nitride semiconductor layer is relatively defect-free and high performance microelecronic devices may be formed in the overgrown gallium nitride semiconductor layer. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to deposit additional GaN over the dopant regions in the GaN layer, the additional deposited GaN increasing a thickness of the GaN layer in order to expand the GaN layer with a relatively defect-free gallium nitride semiconductor layer for integrating more high-performance microelectronic devices.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM.
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Eugene Lee
May 6, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815
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