DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/1/2026 was filed after the mailing date of the non-final rejection on 6/2/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Status
Previous action: claims 1 through 16 rejected, claims 17 through 20 withdrawn
Present action: claims 1, 3 through 16 rejected, claims 17 through 20 withdrawn.
Response to Amendment
Claim 14 was indicated as being original despite the claim being amended in lines 12 and 13.
In the claim listing, the status of every claim must be indicated after its claim number by using one of the following identifiers in a parenthetical expression: (Original), (Currently amended), (Canceled), (Withdrawn), (Previously presented), (New), and (Not entered). MPEP 714.c.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1, 3, 4, 6, 7, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kao (US 2021/0391302) in view of Lii (US 2022/0238353) in view of Uzoh (US 2020/0051937)
Regarding claim 1.
Kao teaches:
A semiconductor package (fig 1,22:2200; [para 0014,0056]), comprising: a first semiconductor chip (fig 22:102; [para 0014,0056]);
a second semiconductor chip (fig 22:104; [para 0014,0056]);
and a bonding layer (fig 22:120a,126; [para 0014,0056]), wherein the first semiconductor chip (fig 22:102; [para 0014,0056])includes: a first substrate (fig 22:108a; [para 0014,0056]);
a first semiconductor device layer (fig 22:110a; [para 0014,0056]) disposed on the first substrate (fig 22:108a; [para 0014,0056]);
a first chip wiring layer (fig 22:112a; [para 0014,0056]) disposed on the first semiconductor device layer (fig 22:110a; [para 0014,0056]);
and a first bonding pad (fig 7,22:122,123; [para 0014,0056]) directly connected to the first chip wiring layer (fig 22:112a; [para 0014,0056]) ;
and a first bonding insulating film (fig 22:124; [para 0014,0056]) disposed on the first chip wiring layer (fig 22:112a; [para 0014,0056]) and surrounding at least a portion of a side surface of the first bonding pad (fig 22:122; [para 0014,0056]);
wherein the second semiconductor chip (fig 22:104; [para 0014,0056]) includes: a second substrate (fig 22:108b; [para 0014,0056]);
a first through-via (fig 22:132; [para 0057]) that penetrates through the second substrate (fig 22:108b; [para 0014,0056]);
and a second bonding pad (fig 22:122,123; [para 0014,0055]) directly connected to the first through-via (fig 22:132; [para 0057]) , wherein the first semiconductor chip (fig 22:102; [para 0014,0056]) and the second semiconductor chip (fig 22:104; [para 0014,0056]) are bonded to each other (fig 1:100; [para 0014,0056]) so that the first bonding pad (fig 7,22:122,123; [para 0014,0056]) and the second bonding pad (fig 22:122,123; [para 0014,0055]) face each other;
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Kao does not teach that the bond pads comprise a dished portion filled with material separated from the bonding insulating layer.
Lii teaches:
and a bonding layer (fig 18a:59; [para 0041]),
a first chip wiring layer (fig 9:30; [para 0019]) disposed on the first semiconductor device layer (fig 9:22; [para 0016]);
and a first bonding pad (fig 9,18a:54; [para 0027]) directly connected to the first chip wiring layer (fig 9:30; [para 0019]) and that includes a first dishing (fig 15a,18a:55; [para 0027]) formed therein;
and a first bonding insulating film (fig 9,18a:42; [para 0027]) disposed on the first chip wiring layer (fig 9:30; [para 0019]) and surrounding at least a portion of a side surface of the first bonding pad (fig 9,18a:54; [para 0027]);
and a second bonding pad (fig 9,18a:154; [para 0038]) that includes a second dishing (fig 18a; [para 0041]) formed therein, wherein the first semiconductor chip (fig 9:2; [para 0016]) and the second semiconductor chip (fig 9:100; [para 0036]) are bonded (fig 18a:60; [para 0039]) to each other so that the first bonding pad (fig 9,18a:54; [para 0027]) and the second bonding pad (fig 9,18a:154; [para 0038]) face each other;
and the bonding layer (fig 18a:59; [para 0041]) fills the first dishing (fig 15a,18a:55; [para 0027]) of the first bonding pad (fig 9,18a:54; [para 0027]) and the second dishing (fig 18a; [para 0041]) of the second bonding pad (fig 9,18a:154; [para 0038]) and is separated from the first bonding insulating film (fig 9,18a:42; [para 0027])by the first bonding pad (fig 9,18a:54; [para 0027]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to fill the dish with a bonding material metal layer so that in the subsequent bonding of the package component with another package component, a better bonding is achieved (paragraph 11)
Kao does not teach that the bond pads comprise a dished portion filled with gold.
Uzoh teaches:
a gold bonding layer (fig 1:114,116; [para 0045]), a first bonding pad (fig 1b,c:110; [para 0045]) that includes a first dishing (fig 1b:d1; [para 0032]) formed therein;
a second bonding pad (fig 1b,d:110; [para 0045]) that includes a second dishing (fig 1b:d1; [para 0032]) formed therein, wherein the first bonding pad (fig 1b,c:110; [para 0045]) and the second bonding pad (fig 1b,d:110; [para 0045]) face each other (fig 1e; [para 0048]);
and the gold bonding layer (fig 1e:114,116; [para 0045]) fills the first dishing (fig 1b:d1; [para 0032]) of the first bonding pad (fig 1b,c:110; [para 0045]) and the second dishing (fig 1b:d1; [para 0032]) of the second bonding pad (fig 1b,d:110; [para 0045]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a gold bonding layer because of gold’s resistance to corrosion and oxidation and to reduce the temperature at which bonding occurs (paragraph 16).
Regarding claim 3.
Kao in view of Lii in view of Uzoh teaches the semiconductor package of claim 1,
Kao teaches:
a buffer insulating film (fig 12,22:802,1202; [para 0045]) formed on a back surface of the second substrate (fig 22:108; [para 0014,0056]).
Regarding claim 4.
Kao in view of Lii in view of Uzoh teaches the semiconductor package of claim 3,
Kao teaches:
the first through-via a first through-via (fig 22:132; [para 0057]) penetrates through the second substrate (fig 22:108; [para 0014,0056]) and the buffer insulating film (fig 12,22:802,1202; [para 0045]).
Regarding claim 6.
Kao in view of Lii in view of Uzoh teaches the semiconductor package of claim 3,
Kao teaches:
the second semiconductor chip (fig 22:104; [para 0014,0056]) further includes a second bonding insulating film (fig 22:1810; [para 0051,0056]) disposed on the buffer insulating film (fig 12,22:802,1202; [para 0045]) and that surrounds at least a portion of a side surface of the second bonding pad (fig 22:122,123; [para 0014,0055]).
Regarding claim 7.
Kao in view of Lii in view of Uzoh teaches the semiconductor package of claim 6,
Kao teaches:
the buffer insulating film (fig 12,22:802,1202; [para 0045]) includes a first oxide film (fig 12,22:802; [para 0040]) and a nitride film (fig 12,22:1202; [para 0045]) that are sequentially stacked, wherein the second bonding insulating film (fig 21:1810; [para 0051]) includes a second oxide film (fig 21:1810; [para 0051]) formed on the nitride film (fig 12,22:1202; [para 0045]).
Regarding claim 8.
Kao in view of Lii in view of Uzoh teaches the semiconductor package of claim 1,
Kao teaches:
the first chip wiring layer (fig 7,22:112a; [para 0014,0056])includes at least one connective pad (fig 7,22:114; [para 0014,0056]) disposed on an uppermost layer thereof, wherein the first bonding pad (fig 7,22:122,123; [para 0014,0056]) directly contacts the connective pad (fig 7,22:114; [para 0014,0056]).
Claim(s) 1, 3, 5, 9, 10, 11, 12, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu (US 2023/0230902) in view of Lii (US 2022/0238353) in view of Uzoh (US 2020/0051937)
Regarding claim 1.
Lu teaches:
A semiconductor package (fig 1:10; [para 0029]), comprising: a first semiconductor chip (fig 1,3:200; [para 0036]);
a second semiconductor chip (fig 1,4:300; [para 0043]);
and a bonding layer (fig 1:bs2,fs3; [para 0036,0043]), wherein the first semiconductor chip (fig 1,3:200; [para 0036])includes: a first substrate (fig 3:220; [para 0036]);
a first semiconductor device layer (fig 3:230; [para 0038]) disposed on the first substrate (fig 3:220; [para 0036]);
a first chip wiring layer (fig 3:242; [para 0039]) disposed on the first semiconductor device layer (fig 3:230; [para 0038]);
and a first bonding pad (fig 3:262; [para 0042]) directly connected to the first chip wiring layer (fig 3:242; [para 0039]) ;
and a first bonding insulating film (fig 1,3:200; [para 0036]) disposed on the first chip wiring layer (fig 1,3:261; [para 0041]) and surrounding at least a portion of a side surface of the first bonding pad (fig 3:262; [para 0042]);
wherein the second semiconductor chip (fig 1,4:300; [para 0029]) includes: a second substrate (fig 4:320; [para 0043]);
a first through-via (fig 1,4:350; [para 0043]) that penetrates through the second substrate (fig 4:320; [para 0043]);
and a second bonding pad (fig 4:312; [para 0044]) directly connected to the first through-via (fig 4:350; [para 0043]) , wherein the first semiconductor chip (fig 1,3:200; [para 0036]) and the second semiconductor chip (fig 1,4:300; [para 0043]) are bonded to each other (fig 1; [para 0060]) so that the first bonding pad (fig 1,3:262; [para 0042]) and the second bonding pad (fig 1,4:312; [para 0044]) face each other;
Lu does not teach does not teach that the bond pads comprise a dished portion filled with material separated from the bonding insulating layer.
Lii teaches:
and a bonding layer (fig 18a:59; [para 0041]),
a first chip wiring layer (fig 9:30; [para 0019]) disposed on the first semiconductor device layer (fig 9:22; [para 0016]);
and a first bonding pad (fig 9,18a:54; [para 0027]) directly connected to the first chip wiring layer (fig 9:30; [para 0019]) and that includes a first dishing (fig 15a,18a:55; [para 0027]) formed therein;
and a first bonding insulating film (fig 9,18a:42; [para 0027]) disposed on the first chip wiring layer (fig 9:30; [para 0019]) and surrounding at least a portion of a side surface of the first bonding pad (fig 9,18a:54; [para 0027]);
and a second bonding pad (fig 9,18a:154; [para 0038]) that includes a second dishing (fig 18a; [para 0041]) formed therein, wherein the first semiconductor chip (fig 9:2; [para 0016]) and the second semiconductor chip (fig 9:100; [para 0036]) are bonded (fig 18a:60; [para 0039]) to each other so that the first bonding pad (fig 9,18a:54; [para 0027]) and the second bonding pad (fig 9,18a:154; [para 0038]) face each other;
and the bonding layer (fig 18a:59; [para 0041]) fills the first dishing (fig 15a,18a:55; [para 0027]) of the first bonding pad (fig 9,18a:54; [para 0027]) and the second dishing (fig 18a; [para 0041]) of the second bonding pad (fig 9,18a:154; [para 0038]) and is separated from the first bonding insulating film (fig 9,18a:42; [para 0027])by the first bonding pad (fig 9,18a:54; [para 0027]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to fill the dish with a bonding material metal layer so that in the subsequent bonding of the package component with another package component, a better bonding is achieved (paragraph 11)
Lu does not teach that the bond pads comprise a dished portion filled with gold.
Uzoh teaches:
a gold bonding layer (fig 1:114,116; [para 0045]),
a first bonding pad (fig 1b,c:110; [para 0045]) that includes a first dishing (fig 1b:d1; [para 0032]) formed therein;
a second bonding pad (fig 1b,d:110; [para 0045]) that includes a second dishing (fig 1b:d1; [para 0032]) formed therein,
wherein the first bonding pad (fig 1b,c:110; [para 0045]) and the second bonding pad (fig 1b,d:110; [para 0045]) face each other (fig 1e; [para 0048]);
and the gold bonding layer (fig 1e:114,116; [para 0045]) fills the first dishing (fig 1b:d1; [para 0032]) of the first bonding pad (fig 1b,c:110; [para 0045]) and the second dishing (fig 1b:d1; [para 0032]) of the second bonding pad (fig 1b,d:110; [para 0045]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a gold bonding layer in the dished pad surface due to gold’s resistance to corrosion and oxidation and to reduce the temperature at which bonding occurs (paragraph 16).
Regarding claim 3.
Lu in view of Lii in view of Uzoh teaches the semiconductor package of claim 1,
Lu teaches:
a buffer insulating film (fig 4:311; [para 0044]) formed on a back surface of the second substrate (fig 4:320; [para 0043]).
Regarding claim 5.
Lu in view of Lii in view of Uzoh teaches the semiconductor package of claim 3,
Lu teaches:
the second bonding pad (fig 4:312; [para 0044]) directly contacts the buffer insulating film (fig 4:311; [para 0044]) and the first through-via (fig 1,4:350; [para 0043]).
Regarding claim 9.
Lu in view of Lii in view of Uzoh teaches the semiconductor package of claim 1,
Lu teaches:
the first semiconductor chip (fig 1,3:200; [para 0036]) further includes a second through-via (fig 1,3:250; [para 0036]) that penetrates through the first substrate (fig 1,3:220; [para 0036]) and is connected to the first bonding pad (fig 1,3:262; [para 0042]).
Regarding claim 10.
Lu in view of Lii in view of Uzoh teaches the semiconductor package of claim 9,
Lu teaches:
the first semiconductor chip (fig 1,3:200; [para 0036]) further includes a third bonding pad (fig 1,3:212; [para 0037]) that is directly connected to the second through-via (fig 1,4:350; [para 0043]) and opposite to the first bonding pad (fig 1,3:262; [para 0042]).
Regarding claim 11.
Lu in view of Lii in view of Uzoh teaches the semiconductor package of claim 10,
Lu teaches:
the third bonding pad (fig 1,3:212; [para 0037])
Uzoh teaches:
the bonding pad (fig 1b,c:110; [para 0045]) has a dishing (fig 1b,d1; [para 0032]) formed therein, wherein at least a portion of the third dishing is filled with gold (Au) (fig 1e:114; [para 0045]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a gold bonding layer in the dished pad surface in order to provide a level surface for improved bonding (paragraph 7) and to reduce the temperature at which bonding occurs (paragraph 16).
Regarding claim 12.
Lu in view of Lii in view of Uzoh teaches the semiconductor package of claim 1,
Lu teaches:
the second semiconductor chip (fig 1,4:300; [para 0043]) includes a fourth bonding pad (fig 1,4:362; [para 0048]) connected to the first through-via (fig 1,4:350; [para 0047]) and opposite to the second bonding pad (fig 1,4:312; [para 0044]).
Regarding claim 13.
Lu in view of Lii in view of Uzoh teaches the semiconductor package of claim 12,
Lu teaches:
the second semiconductor chip (fig 1,4:300; [para 0043])
Uzoh teaches:
the bonding pad (fig 1b,c:110; [para 0045]) has a dishing (fig 1b,d1; [para 0032]) formed therein, wherein at least a portion of the third dishing is filled with gold (Au) (fig 1e:114; [para 0045]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a gold bonding layer in the dished pad surface in order to provide a level surface for improved bonding (paragraph 7) and to reduce the temperature at which bonding occurs (paragraph 16).
Claim(s) 14, 15, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu (US 2023/0230902) in view of Lii (US 2022/0238353) in view of Uzoh (US 2020/0051937)
Regarding claim 14.
Lu teaches:
A semiconductor package (fig 1:10; [para 0029]), comprising: a first semiconductor chip (fig 1,2:100; [para 0030]);
and a second semiconductor chip (fig 1,2:200; [para 0036]), wherein the first semiconductor chip (fig 1,2:100; [para 0030]) includes: a first substrate (fig 1,2:120; [para 0030]);
a first semiconductor device layer (fig 1,2:130; [para 0030])disposed on the first substrate (fig 1,2:120; [para 0030]);
a first chip wiring layer (fig 1,2:160; [para 0030]) disposed on the first semiconductor device layer (fig 1,2:130; [para 0030]);
a first bonding insulating film (fig 1,2:161; [para 0033]) disposed on the first chip wiring layer (fig 1,2:160; [para 0030]);
a first bonding pad (fig 1,2:162; [para 0033]) , wherein at least a portion of a side surface of the first bonding pad (fig 1,2:162; [para 0033]) is surrounded by the first bonding insulating film (fig 1,2:161; [para 0033]);
;
and a first through-via that penetrates (fig 1,2:150; [para 0034]) through the first substrate (fig 1,2:120; [para 0030]) and is connected to the first bonding pad (fig 1,2:162; [para 0033]), wherein the second semiconductor chip (fig 1,3:200; [para 0036]) includes: a second substrate (fig 1,3:220; [para 0036]);
a second bonding insulating film (fig 1,3:261; [para 0041]) disposed on the second substrate (fig 1,3:220; [para 0036]);
a second bonding pad (fig 1,3:262; [para 0041]) , wherein at least a portion of a side surface of the second bonding pad (fig 1,3:262; [para 0041]) is surrounded by the second bonding insulating film (fig 1,3:261; [para 0041]);
;
and a second through-via (fig 1,3:250; [para 0040]) that penetrates through the second substrate (fig 1,3:220; [para 0036]) and is connected to the second bonding pad (fig 1,3:262; [para 0041]), wherein the first semiconductor chip (fig 1,2:100; [para 0030]) and the second semiconductor chip (fig 1,3:200; [para 0036]) are bonded to each other so that the first bonding pad (fig 1,2:162; [para 0033]) and the second bonding pad (fig 1,3:262; [para 0041]) face each other, .
Lu does not teach that the bond pads comprise a dished portion filled with a layer separated from the bonding insulating film
Lii teaches:
a first bonding pad (fig 9,18a:54; [para 0027]) that includes a first dishing (fig 15a,18a:55; [para 0027])formed therein, wherein at least a portion of a side surface of the first bonding pad (fig 9,18a:54; [para 0027]) is surrounded by the first bonding insulating film (fig 9,18a:42; [para 0027]);
a first layer (fig 16a,18a:58; [para 0029])that fills the first dishing (fig 15a,18a:55; [para 0027])and is separated from the first bonding insulating film (fig 9,18a:42; [para 0027])by the first bonding pad (fig 9,18a:54; [para 0027]);
a second bonding insulating film (fig 9,18a:142; [para 0037])disposed on the second substrate (fig 9:114; [para 0036]);
a second bonding pad (fig 9,18a:154; [para 0038]) that includes a second dishing (fig 18a; [para 0041]) formed therein, wherein at least a portion of a side surface of the second bonding pad (fig 9,18a:154; [para 0038]) is surrounded by the second bonding insulating film (fig 9,18a:142; [para 0037]);
a second layer (fig 18a:158; [para 0041])that fills the second dishing (fig 18a; [para 0041]);
the first bonding pad (fig 9,18a:54; [para 0027]) and the second bonding pad (fig 9,18a:154; [para 0038]) face each other, and wherein the first layer (fig 16a,18a:58; [para 0029]) and the second layer (fig 18a:158; [para 0041]) are bonded to each other.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to fill the dish with a bonding material metal layer so that in the subsequent bonding of the package component with another package component, a better bonding is achieved (paragraph 11)
Lu does not teach that the bond pads comprise a dished portion filled with gold.
Uzoh teaches:
a first gold layer (fig 1b,c:114; [para 0045]) that fills the first dishing (fig 1b:d1; [para 0032]);
a second gold layer (fig 1b,d:116; [para 0045]) that fills the second dishing (fig 1b:d1; [para 0032]);
and wherein the first gold layer (fig 1b,c:114; [para 0045]) and the second gold layer (fig 1b,d:116; [para 0045]) are bonded to each other (fig 1e:118; [para 0048])and wherein the first gold layer (fig 1b,c:114; [para 0045]) and the second gold layer (fig 1b,d:116; [para 0045]) are bonded to each other.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a gold bonding layer because of gold resistance to corrosion and to reduce the temperature at which bonding occurs (paragraph 16).
Regarding claim 15.
Lu in view of Lii in view of Uzoh teaches the semiconductor package of claim 14,
Lu teaches:
the second bonding pad (fig 1,3:262; [para 0041])is directly connected to the second through-via (fig 1,3:250; [para 0040]).
Regarding claim 16.
Lu in view of Lii in view of Uzoh teaches the semiconductor package of claim 14,
Lu teaches:
the second semiconductor chip (fig 1,3:200; [para 0036]) further includes: a second semiconductor device layer (fig 1,3:230; [para 0036]) disposed between the second substrate (fig 1,3:220; [para 0036]) and the second bonding insulating film (fig 1,3:261; [para 0041]);
and a second chip wiring layer (fig 1,3:242; [para 0041]) disposed between the second semiconductor device layer (fig 1,3:230; [para 0036]) and the second bonding insulating film (fig 1,3:261; [para 0041]), wherein the second bonding pad (fig 1,3:262; [para 0041]) is directly connected to the second chip wiring layer (fig 1,3:242; [para 0041]).
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference combination applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The newly applied reference Lii (US 2022/038353) anticipates the amendments to the claims
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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