DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seliskar et al. (US 6,335,532).
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(Claim 1) Seliskar et al. teach a capacitor structure, comprising:
a first well region (30);
a first semiconductor layer (80) disposed over the first well region;
a second semiconductor layer (74) disposed on the first semiconductor layer;
a dielectric layer (fig. 3 #50) disposed on the second semiconductor layer,
wherein the dielectric layer (fig. 3 #50) has a top surface, a bottom surface, one or more protrusions extending towards the second semiconductor layer, and
one or more openings (46) in the top surface; and
a gate structure (60) disposed on the dielectric layer.
(Claim 2) Seliskar et al. teach the capacitor structure, further comprising a second well region (22, 24) disposed in the first well region (30).
(Claim 3) Seliskar et al. teach wherein the first well region (30) and the second well region (22, 24) comprise dopants of a same conductivity type (col. 8 lines 15 – 16).
(Claim 4) Seliskar et al. teach wherein a dopant concentration of the second well region (22, 24) is substantially greater than a dopant concentration of the first well region (30, col 8 lines 15 – 16).
(Claim 5) Seliskar et al. teach wherein the first semiconductor layer (80) comprises a species of a first conductivity type (P, col. 12 lines 24 – 32), and the first well region (30) comprises a dopant of a second conductivity type (N) opposite the first conductivity type (col, 18 lines 9 – 16).
(Claim 6) Seliskar et al. teach wherein the first (80) and second semiconductor layers (74) comprise species of a same conductivity type (P, col. 12 lines 24 – 32).
(Claim 7) Seliskar et al. teach wherein the first and second semiconductor layers are formed by an epitaxial growth process (col. 11 lines 29 – 32).
(Claim 8) Seliskar et al. teach wherein the first semiconductor layer and the second semiconductor layer each has a serpentine profile (fig. 20).
(Claim 9) Seliskar et al. teach a capacitor structure, comprising:
a first well region (30);
a semiconductor layer (80 P+, 70 P) disposed over the first well region,
wherein the semiconductor layer has a gradient concentration of n-type or p-type species that decreases in a direction from a bottom surface of the semiconductor layer to a top surface of the semiconductor layer (col. 12 lines 24 – 34), and
one or more openings (46) are formed in the top surface of the semiconductor layer;
a dielectric layer (fig. 3 #50) disposed on the semiconductor layer and in the one or more openings (46); and
a gate structure (60) disposed on the dielectric layer.
(Claim 10) Seliskar et al. teach wherein the semiconductor layer (80/70) further comprises one or more protrusions extending towards the first well region.
(Claim 11) Seliskar et al. teach wherein the bottom surface of the semiconductor layer (80/70) is substantially flat.
(Claim 12) Seliskar et al. teach the capacitor structure, further comprising a second well region (22, 24) disposed in the first well region (30),
wherein the first well region and the second well region comprise dopants of a same conductivity type.
(Claim 13) Seliskar et al. teach wherein the semiconductor layer comprises a species of a first conductivity type (P, ) (col. 12 lines 24 – 34), and the first well region comprises dopants of a second conductivity type (N) opposite the first conductivity type.
Allowable Subject Matter
Claims 14 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
(Claim 14) the capacitor structure, further comprising a deep well region, wherein the deep well region comprises dopants of the first conductivity type.
(Claim 15) the capacitor structure, further comprising a third well region surrounding the first well region, wherein the third well region comprises dopants of the first conductivity type.
Claims 16 – 20 are allowable, because prior does not teach:
(Claim 9) a semiconductor layer disposed over the first well region,
wherein the semiconductor layer has a gradient concentration of n-type or p-type species that decreases in a direction from a bottom surface of the semiconductor layer to a top surface of the semiconductor layer.
(Claim 16) forming a first well region between the first and second isolation regions;
forming a second well region in the first well region;
forming one or more openings in the second well region;
recessing the second well region, wherein the one or more openings are extended into the recessed second well region;
forming a first semiconductor layer on the second well region and in the one or more openings,
wherein the first semiconductor layer is formed by an epitaxial growth process, and the first semiconductor layer has a serpentine profile.
Response to Arguments
Applicant's arguments filed on July 2, 2026 have been fully considered but they are not persuasive.
Applicant argues:
Claims 1 - 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seliskar et al. (US 6,335,532). Applicant respectfully traverses the rejection.
Seliskar is directed to a field-effect transistor (FET), not to a capacitor structure. Specifically, Seliskar is titled "Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET" and the entire disclosure of Seliskar is directed to a dual-gate CMOS FET having a plurality of narrow vertically- oriented silicon channel segments interdigitated with a dual-gate structure. Seliskar does not disclose, suggest, or contemplate a capacitor structure comprising a capacitor. Pending independent claims 1 and 9 are each expressly directed to "A capacitor structure comprising a capacitor". Withdrawal of the rejection is respectfully requested.
Reply:
A Metal-Oxide-Semiconductor capacitor consists of a metal conductor plate and a semiconductor plate separated by an insulating dielectric.
Seliskar et al. teach using the structure as a capacitor and transistor by scaling the plate size to control the current capacities (col. 17 lines 40 – 65).
Furthermore, instant application also teaches the claimed structure (fig. 11, paragraph 28, reproduced below) can be used as a capacitor and transistor.
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[0028] The gate structure 132 is formed by a gate-first process or a gate-last process. The gate structure 132 is also formed in the active device regions to function as a gate of a transistor. The gate electrode layer of the gate structure 132 formed in the passive device region functions as the top electrode of the MOS capacitor, while the first and second semiconductor layers 124, 126 function as the bottom electrode of the MOS capacitor. The dielectric layer 130 (and the gate dielectric layer in some embodiments) functions as the insulator of the MOS capacitor.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Prior art made of record and not relied upon, considered pertinent to applicant's disclosure are listed in PTO – 892 Form.
Contact Information
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/IGWE U ANYA/Primary Examiner, Art Unit 2891
March 21, 2026
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