DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Amendment filed on 10/01/2025 has been received and entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 6 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2022/0366944 cited in the last office action) in view of Ghosh et al. (US 10,916,275, hereinafter “Ghosh”).
Regarding claim 1, Lee (Fig. 2 and Fig. 12) shows a serial read write memory comprising:
a bank of bitcells (Fig. 2, 130) arranged into a plurality of columns, wherein the plurality of columns includes a multiplexed group of columns (Fig. 12, COL1 and COL2);
a write column multiplexer (236b) configured to select for a write-selected column (COL2) from the multiplexed group of columns during a write operation (Fig. 12, when WM2 is high), wherein the multiplexed group of columns includes a write-unselected column (COL1);
a first precharge circuit (240b) configured to charge a first pair of bit lines (BL2 and BLS2) in the write-selected column to a memory power supply voltage responsive to an assertion of a first bit line precharge signal (when PCH2 is low); and
a second precharge circuit (240a) configured to charge a second pair of bit lines BL1 and BLS1) in the write- unselected column to the memory power supply voltage responsive to an assertion of a second bit line precharge signal (when PCH1 is low); and
a write driver (Fig.12, 235) configured to charge a first bit line in the first pair of bit lines during the write operation and configured to discharge a second bit line in the first pair of bit lines during the write operation (Fig. 14, BL2/BLS2 at time t11 to t12),
wherein the write column multiplexer is configured to couple the first bit line (BL2) to a first write driver node (node between write driver 235 and transistor MN3”) during the write operation and to couple the second bit line (BLS2) to a second write driver node (node between write driver 235 and transistor MN4”) during the write operation.
Lee does not disclose the write driver comprising a first transistor coupled between the first write driver node and ground; a second transistor coupled between the first write driver node and a node for the memory power supply voltage; a third transistor coupled between the second write driver node and ground; and a fourth transistor coupled between the second write driver node and the node for the memory power supply voltage. a first transistor coupled between the first write driver node and ground; a second transistor coupled between the first write driver node and a node for the memory power supply voltage; a third transistor coupled between the second write driver node and ground; and a fourth transistor coupled between the second write driver node and the node for the memory power supply voltage.
However, Ghosh (Fig. 7) shows a write driver 530 comprising a first transistor (736) coupled between the first write driver node and ground; a second transistor (732) coupled between the first write driver node and a node for the memory power supply voltage; a third transistor (738) coupled between the second write driver node and ground; and a fourth transistor (734) coupled between the second write driver node and the node for the memory power supply voltage to charge the first bit line (when data is 0) in the first pair of bit lines during the write operation and configured to discharge the second bit line (data_b is 1) in the first pair of bit lines during the write operation. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lee by using the write driver of Gosh to charge the first bit line in the first pair of bit lines during the write operation and configured to discharge the second bit line in the first pair of bit lines during the write operation
Regarding claim 2, Lee discloses the serial read write memory of claim 1, further comprising:
a precharge generation circuit configured to assert the second bit line precharge signal (PCH1 is low) during the write operation (Fig. 14, t10-t13) while the first bit line precharge signal (Fig, 14, PCH2 is high from t10-t13) remains de-asserted responsive to a read operation occurring to the bank of bitcells (RM1 is low, read operation in the first interval of the clock cycle) during an initial portion of a memory clock cycle, wherein the memory clock cycle is divided into the initial portion (Fig. 14, t1-t8) and a final portion t8-t15), and wherein the write operation occurs during the final portion (period t10-t13 is in the final portion).
Regarding claim 5, Lee (Fig. 3) discloses the serial read write memory of claim 1, wherein each bitcell comprises a six-transistor static-random-access memory bitcell.
Regarding claim 6, Lee (Figs. 12 and 14) shows the serial read write memory of claim 2, wherein the bank of bitcells are further arranged into rows, with each row traversed by a corresponding word line, and wherein the serial read write memory is further configured to charge a first word line (VWL1 is high in the first portion of the clock cycle) during the read operation and to charge a second word line (VWL2 is high in the second portion of the clock cycle) during the write operation.
Regarding claim 8, Lee discloses the serial read write memory of claim 2, wherein the precharge generation circuit (260a) is further configured to latch the second bit line precharge signal (PCH1 is high) during the read operation (Fig. 14, the first portion of the clock cycle).
Regarding claim 9, Lee (Fig. 12) shows the serial read write memory of claim 1, wherein the multiplexed group of columns includes only two columns (COL1 and COL2).
Regarding claim 10, Lee (Fig. 12) shows the serial read write memory of claim 2, wherein the first bit line precharge signal (PCH2) and the second bit line precharge signal (PCH1) are both active-low signals, and wherein the precharge generation circuit is further configured to assert the second bit line precharge signal by a discharge of the second bit line precharge signal to ground (Fig. 14, from t6 to t15).
Claims 1, 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over
Poplevine et al. (US 6,563,730 cited in the last office action, hereinafter "Poplevine") in view of Ghosh.
Regarding claim 1, Poplevine (Fig. 3) shows a serial read write memory comprising:
a bank of bitcells (memory array) arranged into a plurality of columns, wherein the plurality of columns includes a multiplexed group of columns (BTO and BB0; BT1 and BB1, and BTM and BBM);
a write column multiplexer (310) configured to select for a write-selected column (YO selects the first column from left) from the multiplexed group of columns during a write operation, wherein the multiplexed group of columns includes a write-unselected column (a second column from left);
a first precharge circuit (304 and 306) configured to charge a first pair of bit lines (BTO and BB0) in the write-selected column to a memory power supply voltage responsive to an assertion of a first bit line precharge signal YS0); and
a second precharge circuit (transistors in 308 connected to YS1) configured to charge a second pair of bit lines in the write-unselected column to the memory power supply voltage responsive to an assertion of a second bit line precharge signal (YS1).
Poplevine does not disclose the write driver comprising a first transistor coupled between the first write driver node and ground; a second transistor coupled between the first write driver node and a node for the memory power supply voltage; a third transistor coupled between the second write driver node and ground; and a fourth transistor coupled between the second write driver node and the node for the memory power supply voltage. a first transistor coupled between the first write driver node and ground; a second transistor coupled between the first write driver node and a node for the memory power supply voltage; a third transistor coupled between the second write driver node and ground; and a fourth transistor coupled between the second write driver node and the node for the memory power supply voltage.
However, Ghosh (Fig. 7) shows a write driver 530 comprising a first transistor (736) coupled between the first write driver node and ground; a second transistor (732) coupled between the first write driver node and a node for the memory power supply voltage; a third transistor (738) coupled between the second write driver node and ground; and a fourth transistor (734) coupled between the second write driver node and the node for the memory power supply voltage to charge the first bit line (when data is 0) in the first pair of bit lines during the write operation and configured to discharge the second bit line (data_b is 1) in the first pair of bit lines during the write operation. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Poplevine by using the write driver of Gosh to charge the first bit line in the first pair of bit lines during the write operation and configured to discharge the second bit line in the first pair of bit lines during the write operation
Regarding claim 5, Poplevine discloses the serial read write memory of claim 1, wherein each bitcell comprises a six- transistor static-random-access memory bitcell (column 3, lines 64-67).
Regarding claim 7, Poplevine discloses the serial read write memory of claim 1, wherein the write-unselected column comprises a plurality of write-unselected columns (the second column from left to right).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Ghosh.
Claim 11 differs from Lee in view of Ghosh in reciting that the serial read write memory is included within a cellular telephone. However, the use of a memory in a cellular telephone is well-known in the art to store data and information to perform the functions of the cellular telephone. It would have been obvious to one having ordinary skill in the art before the claimed invention to use a memory in a cellular telephone to store data and information to perform the functions of the cellular telephone.
Allowable Subject Matter
Claims 12,14-19 and 21 are allowed.
Response to Arguments
Applicant’s arguments with respect to claims 1, 2 and 5-11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/HUAN HOANG/ Primary Examiner, Art Unit 2827