DETAILED ACTION
1. This Office action is in response to the amendment filed on 01/14/2026
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claim(s) 1, 3 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2022/0069703 A1 and CN 116225120 B; (hereinafter Krishnamurthy et al and Min et al). Krishnamurthy et al cited in previous office action dated 10/17/2025.
Regarding claim 1, Krishnamurthy et al [e.g., Fig. 2] discloses a digital low- dropout voltage regulator (DLVR) circuit [e.g., voltage regulator 200] comprising: a driver array [e.g., array of switches MPhs1, MPb1, MNb1 and MNIs1] configured to output a voltage supply [e.g., configured to output voltage Vout], wherein the driver array comprises a plurality of transistors [e.g., p. 0039 recites "… each phase includes a high-side switch MPhs (e.g., binary weighted MPhs1 through MPhs8) and a low-side switch MNIs (e.g., binary weighted MNIs1 through MNIs8)"]; an analog-to-digital converter [e.g., analog-to- digital converter ADC 202] configured to compare the voltage supply to a reference voltage to determine a difference in voltage level between the voltage supply and the reference voltage [e.g., compares Vout to Vref, p. 0041 recites "ADC 202 monitors the output voltage Vout (or a divided version of Vout) against a reference Vref and generates a digital representation e(k) of a difference between Vout and Vref"]; a digital controller [e.g., Type-III Digital Controller 203] configured to modulate a gate voltage supplied to the driver array based on the difference in voltage level [e.g., p. 0041 - 0042 recites "The output of the comparator is e[k]. The Type-III digital controller 203 is a linear digital compensator (Linear) or PID filter which takes the voltage error e[k] as an input and outputs a duty cycle command d[k] to the Digital PWM (DPWM) block(s) (2051 through 2058) for each of the active phases. The duty cycle command d[k] controls the duty cycle of a pulse width modulated wave which controls the pDrv and nDrv."]; and a duty cycle control module [e.g., Digital PWM Generation Logic 205] configured to modify the duty cycle of the gate voltage supplied to the driver array [e.g., p. 0045 recites "…duty cycle command d[k] provides the adjustment to the threshold voltage of PWM generator logic 205 to realize the change in duty cycle at the output of the comparator of PWM generator logic 205. The output of PWM generator logic 205 is a PWM wave which is then converted to pDrv and nDrv signals by bridge controller 201a"].
Krishnamurthy et al does not discloses wherein the duty cycle control module comprises a down sampling circuit responsive to a frequency input to modify the duty cycle of the gate voltage.
Min et al [e.g., Fig. 5] teaches wherein the duty cycle control module comprises a down sampling circuit [e.g., shift register 50112,] responsive to a frequency input [e.g., responsive to CLK signal generated by timing control subcircuit 5021, Embodiment 2 recites “…and the shift register 50112 operates at the falling edge of the internal clock signal CLK’’] to modify the duty cycle of the gate voltage [e.g., modify gate voltage of power module 5012, Embodiment 2 recites “The second state control storage subcircuit 5023 includes a latch array 50231 and a two-choice data selector array 50232, which are sequentially connected in series between the shift register 50112 and the power module 5012, and their connection relationship is controlled by an internal PWM control signal…”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Krishnamurthy et al with wherein the duty cycle control module comprises a down sampling circuit responsive to a frequency input to modify the duty cycle of the gate voltage as suggested by Min et al to improve the recovery of the target control voltage when the LDO resumes operation following an idle state.
Regarding claim 3, Krishnamurthy et al [e.g., Fig. 2] discloses wherein the gate voltage is a first gate voltage [e.g., gate voltage pDrv delivered to high-side switches MPhs1 - MPhs8 via respective driver]; and wherein plurality of transistors comprises a first transistor [e.g., hide-side switches MPhs1 - MPhs8] comprising a first source/drain connected to a high voltage signal [e.g., sources of high side switches MPhs1 - MPhs8 connected to Vin] and a first gate configured to receive the first gate voltage [e.g., first gate voltage (pDrv) delivered to high-side switches MPhs1 - MPhs8 via respective driver]; and a second transistor [e.g., bias transistor MPb1 - MPb8] comprising a second gate configured to receive a second gate voltage [e.g., configured to receive Vmid], wherein the second gate voltage level is lower than the high voltage signal voltage level [e.g., second gate voltage Vmid lower than high voltage Vin, p. 0040 recites "…,bias transistors MPb and MNb are coupled between the high-side switch MPhs and the low-side switch MNIs. For example, bias transistors MPb1 through MPb8 are coupled to the high-side switches MPhs1 through MPhs8, respectively, and bias transistors MNb1 through MNb8 are coupled to low-side switches MNhs1 through MNhs8, respectively as shown. The bias transistors MPb and MNb may be controlled by a bias voltage such as Vmid (e.g., Vin/2)"].
Regarding claim 7, Krishnamurthy et al [e.g., Fig. 2] discloses wherein the duty cycle control module [e.g., Digital PWM Generation Logic 205] comprises a digital phase control circuit [e.g., p. 0045 recites "…, PWM generator logic 205 comprises a triangular (or other waveform) wave generator which generates a periodic triangular wave. The triangular wave is input to a comparator. Another input of the comparator is coupled to a threshold voltage. In some embodiments, the threshold voltage is adjusted (e.g., raised or lowered) to change a duty cycle of the output of the comparator. In some embodiments, duty cycle command d[k] provides the adjustment to the threshold voltage of PWM generator logic 205 to realize the change in duty cycle at the output of the comparator of PWM generator logic 205. The output of PWM generator logic 205 is a PWM wave which is then converted to pDrv and nDrv signals by bridge controller 201a"].
7. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Krishnamurthy et al in view of Min et al and US Pub. No. 2023/0018398 A1; (hereinafter Krishnamurthy et al, Min et al and Whitcombe et al).
Regarding claim 2, Krishnamurthy et al [e.g., Fig. 2] discloses a frequency control module connected to the duty cycle control module [e.g., Phase Clocks 206, p. 0045 recites "…, the comparator of PWM generation logic 205 is a clocked comparator which samples the output of the comparator by clocks of one or more phases Clkphases generated by phase clock generator 206"].
Krishnamurthy et al does not disclose wherein the frequency control module comprises a ring oscillator.
Whitcombe et al [e.g., Fig. 9] teaches wherein the frequency control module comprises a ring oscillator [e.g., 905 ring oscillator, p. 0049 recites "Ring oscillator comprises inverters 1 through N coupled in a ring formation. The output of each inverter (or its equivalent logic gate) is a clock which is used to clock a comparator of an LDO circuitry. Finer time resolution may be obtained by applying phase interpolation to the ring oscillator outputs. In some embodiments, LDO circuitry 901 can be arrayed, with staggered comparator clocks (e.g., CLK 1, CLK 2, CLK N) to provide finer time resolution. For example, clock CLK 1 is used to sample comparator 804 of LDO circuitry 901-1, clock CLK 2 is used to sample comparator 804 of LDO circuitry 901-2, and SO on"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Krishnamurthy et al with wherein the frequency control module comprises a ring oscillator as suggested by Whitcombe et al to provide finer timing resolution that improves regulation accuracy.
8. Claim(s) 4 - 6 are rejected under 35 U.S.C. 103 as being unpatentable over Krishnamurthy et al in view of Min et al and US Pub. No. 2023/0195151 A1; (hereinafter Krishnamurthy et al, Min et al and Sorace et al).
Regarding claim 4, Krishnamurthy et al discloses the claimed invention except for wherein the analog-to-digital controller is connected to the driver array through a first level shifter; and the digital controller and the duty cycle control module are connected to the driver array through a second level shifter.
Sorace et al [e.g., Fig. 6] teaches wherein the analog-to-digital controller [e.g., Comparator 110] is connected to the driver array through a first level shifter [e.g., connected to Power Devices 150 via Level Shifter 155a]; and the digital controller and the duty cycle control module [e.g., Digital Multibit Delta Sigma Modulator (Delta Sigma modulator and Multibit Quantizer)] are connected to the driver array through a second level shifter [e.g., connected to Level Shifter and Driver 155b].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Krishnamurthy et al with wherein the analog-to-digital controller is connected to the driver array through a first level shifter; and the digital controller and the duty cycle control module are connected to the driver array through a second level shifter as suggested Sorace et al to allow control of the voltage level to move from one level (e.g. high/low) to another one.
Regarding claim 5, Krishnamurthy et al [e.g., Fig. 2] discloses wherein the driver array comprises a DLVR driver circuit [e.g., array containing high side switches MPhs1 - MPhs8), bias transistors (MPb1 - Mpb8 and MNb1 - MNb8) and low- side switches (MNIs1 - MNIs8) with respective drivers] and a high voltage pre-driver circuit [e.g., Bridge Controller 201a].
Regarding claim 6, Krishnamurthy et al discloses the claimed invention except for wherein the high voltage pre-driver circuit receives an input voltage from the second level shifter and outputs the gate voltage to a first transistor of the DLVR driver circuit.
Sorace et al [e.g., Fig. 6] teaches wherein the high voltage pre-driver circuit receives an input voltage from the second level shifter [e.g., Level Shifter and Driver 155b, p. 0059 recites "In this example, which is based on the example of FIG. 5, there is a first level shifter device 155a coupled between the comparator device 110 and the digital modulation device 120, while a second driver and level shifter device 155b is coupled between the digital modulation device 120 and the power device 150. Thereby, potentially different power domains may be established in the device 100"] and outputs the gate voltage to a first transistor of the DLVR driver circuit [e.g., output gate voltage to power devices 150].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Krishnamurthy et al with wherein the high voltage pre-driver circuit receives an input voltage from the second level shifter and outputs the gate voltage to a first transistor of the DLVR driver circuit as suggested Sorace et al to allow control of the voltage level to move from one level (e.g. high/low) to another one.
9. Claim 9 - 11 are rejected under 35 U.S.C. 103 as being unpatentable over Krishnamurthy et al in view of Min et al and US Pub. No. 2014/0266143 A1; (hereinafter Krishnamurthy et al, Min et al and Saint-Laurent et al).
Regarding claim 9, Krishnamurthy et al [e.g., Fig. 2] discloses the claimed invention except for wherein the duty cycle control module comprises an analog phase control circuit.
Saint-Laurent et al [e.g., Fig. 2] teaches wherein the duty cycle control module [e.g., Digital Circuit 104, Control logic 108 and voltage comparator 222] comprises an analog phase control circuit [e.g., p. 0045 recites "The voltage comparator 222 generates the analog adjustment signal 220 that controls duty cycles of the transistors 430, 434, 438, 442 to control the second output voltage 210. In response to the analog voltage adjustment signal 220, the transistors 430, 434, 438, 442 may be selectively turned on or off using gating circuits (not shown). By controlling the duty cycles of the transistors 430, 434, 438, 442, the voltage comparator 222 may control phases of currents that drive the inductors 446, 448 to generate the second output voltage 210. Accordingly, the voltage comparator 222 may control the second output voltage 210"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Krishnamurthy et al with wherein the duty cycle control module comprises an analog phase control circuit as suggested by Saint-Laurent et al to control the analog variable impedance element via an analog voltage adjustment signal.
Regarding claim 10, Krishnamurthy et al [e.g., Fig. 2] discloses the claimed invention except for wherein the analog phase control circuit comprises a comparator configured to provide pulse width modulation.
Saint-Laurent et al teaches wherein the analog phase control circuit comprises a comparator [e.g., voltage comparator 222] configured to provide pulse width modulation [e.g., p. 0045 recites "By controlling the duty cycles of the transistors 430, 434, 438, 442, the voltage comparator 222 may control phases of currents that drive the inductors 446, 448 to generate the second output voltage 210. Accordingly, the voltage comparator 222 may control the second output voltage 210"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Krishnamurthy et al with wherein the analog phase control circuit comprises a comparator configured to provide pulse width modulation as suggested by Saint-Laurent et al to control the analog variable impedance element via an analog voltage adjustment signal.
Regarding claim 11, Krishnamurthy et al discloses the claimed invention except for wherein the duty cycle control module comprises a digital phase control circuit and an analog phase control circuit.
Saint-Laurent et al [e.g., Fig. 2] teaches wherein the duty cycle control module comprises a digital phase control circuit [e.g., Digital Circuit 104 and Control Logic 108, p. 0026 recites “The control logic 108 may be a digital circuit that is configured to control other circuits via digital signals"] and an analog phase control circuit [e.g., Voltage Comparator 222, p. 0033 recites “The voltage comparator 222 may adjust the analog variable impedance element 206 to generate a second output voltage 210 based on the supply voltage 212"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Krishnamurthy et al with wherein the duty cycle control module comprises a digital phase control circuit and an analog phase control circuit as suggested by Saint-Laurent et al to control the analog variable impedance element and digital variable impedance element via an analog voltage adjustment signal and digital signal, respectively.
10. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Krishnamurthy et al in view of Min et al, Saint-Laurent et al and US Patent No. 10,156,859 B2; (hereinafter Krishnamurthy et al, Min et al , Saint-Laurent et al and Luria et al).
Regarding claim 12, Krishnamurthy et al [e.g., Fig. 2] discloses the claimed invention except for a multiplexer connected to the digital phase control circuit and the analog phase control circuit and configured to switch the duty cycle control module between the digital phase control circuit and the analog phase control circuit.
Luria et al [e.g., Fig. 1] teaches a multiplexer [e.g., multiplexer 101] connected to the digital phase control circuit [e.g., connected to Digital gate mode 106n (Logic 103 and PG Driver via Multiplexer 101, column 3 lines 38 - 41 recites "…during digital gate mode 106, digital signal generated by logic 103 is used to control gate terminal of M1. In one embodiment, output of logic 103 is buffered by the buffer"] and the analog phase control circuit [e.g., LDO-VR core 102, column 3 lines 32 - 36 recites "…, LDO-VR core 102 receives reference voltage Vref and compares it with output voltage Vout to adjust signal on node n3. Here, the term signal and node on that signal are interchangeably used"] and configured to switch the duty cycle control module between the digital phase control circuit and the analog phase control circuit [e.g., column 3 lines 12 - 23 recites "…, M1 has a dual purpose or modes. For example, in a first mode M1 is used as a traditional power gate transistor when mux 101 selects signal on node n4 to control gate terminal of M1, and in a second mode M1 is used as part of linear voltage regulation when mux 101 selects signal on node n3 to couple to the gate terminal of M1. The former is referred to as digital power gate mode 106 and the later is referred to as the LDO-VR mode 105. In one embodiment, source terminal of M1 is coupled to first power supply (Vcca) and the drain terminal of M1 is coupled to Vout. The first power supply is also referred to as the un-gated power supply"].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Krishnamurthy et al with a multiplexer connected to the digital phase control circuit and the analog phase control circuit and configured to switch the duty cycle control module between the digital phase control circuit and the analog phase control circuit as suggested by Luria et al to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch.
11. Claim 17, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Krishnamurthy et al in view of US Patent No. 11,320,888 B2; (hereinafter Krishnamurthy et al and Augustine et al).
Regarding claim 17, Krishnamurthy et al [e.g., Fig. 2] discloses a method of operating a circuit, comprising: receiving an input voltage by a digital low dropout voltage regulator (DLVR) [e.g., input voltage Vin received by voltage regulator VR 200 with digital controls, p. 0038 recites "FIG. 2 illustrates voltage regulator (VR) 200 with apparatus for seamless transition from non-linear control to linear regulation mode"], wherein a driver array of the DLVR takes the input voltage as an input and generates an output voltage [e.g., generates output voltage Vout via array of switches MPhs1, MPb1, MNb1 and MNIs1]; comparing the output voltage to a reference voltage [e.g., compares output voltage Vout to reference voltage Vref via analog-to-digital converter ADC 202]; determining a difference between the output voltage and the reference voltage [e.g., signal e[k], p. 0041 recites "ADC 202 monitors the output voltage Vout (or a divided version of Vout) against a reference Vref and generates a digital representation e(k) of a difference between Vout and Vref"]; supplying the modulated gate signal to the driver array of the DLVR based on the determined difference [e.g., p. 0041 - 0042 recites "The output of the comparator is e[k]. The Type-III digital controller 203 is a linear digital compensator (Linear) or PID filter which takes the voltage error e[k] as an input and outputs a duty cycle command d[k] to the Digital PWM (DPWM) block(s) (2051 through 2058) for each of the active phases. The duty cycle command d[k] controls the duty cycle of a pulse width modulated wave which controls the pDrv and nDrv"]; suppling the duty cycle control signal to the driver array of the DLVR [e.g., PWM signal delivered by PWM Generation Logic 205, p. 0045 recites "In some embodiments, duty cycle command d[k] provides the adjustment to the threshold voltage of PWM generator logic 205 to realize the change in duty cycle at the output of the comparator of PWM generator logic 205. The output of PWM generator logic 205 is a PWM wave which is then converted to pDrv and nDrv signals by bridge controller 201a"]; and generating a modified output voltage based on the modulated gate signal and duty cycle control signal [e.g., generates Vout based on signal d[k] and PWM].
Krishnamurthy et al does not discloses down-sampling a frequency input from a ring oscillator to generate a duty cycle control signal.
Augustine et al [e.g., Fig. 3] teaches down-sampling a frequency input from a ring oscillator to generate a duty cycle control signal [e.g., up/down shifter 102 receiving signal ROCLK from oscillator 301, col. 6 lines 3 - 5 recites “oscillator 301 is a free running ring oscillator which is powered by the voltage provided by the output power supply rail Vout.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Krishnamurthy et al with down-sampling a frequency input from a ring oscillator to generate a duty cycle control signal as suggested by Augustine et al to maintain a voltage while ensuring stable operation due to input supply voltage Vin changing due to dynamic voltage and frequency scaling events.
Regarding claim 19, Krishnamurthy et al [e.g., Fig. 2] discloses wherein the input voltage is a high voltage supply [e.g., input voltage supply Vin].
Regarding claim 20, Krishnamurthy et al [e.g., Fig. 2] discloses wherein the supplying a duty cycle control signal [e.g., Type-III Digital Controller 203] is controlled with a binary weighting process comprising selecting a number of driver control bits to be in an ON state [e.g., p. 0039 recites "…, each phase (e.g. 2011) includes a plurality of bridges. The bridges may be thermometer weighted or binary weighted (as shown). In some embodiments, each phase includes a high-side switch MPhs (e.g., binary weighted MPhs1 through MPhs8) and a low-side switch MNIs (e.g., binary weighted MNIs1 through MNIs8)"].
Examiner’s Note
12. Examiner has cited particular columns, paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
13. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Response to Arguments
14. Applicant’s arguments with respect to claim(s) 1 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
14. Claims 13 - 15 and 21 are allowed.
15. Claim 8 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 8 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the digital phase control circuit comprises the down sampling circuit and a shift register configured to receive the frequency input from a ring oscillator.”
The primary reason for the indication of the allowability of claim 13 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “a duty cycle control module configured to modify a duty cycle of a gate voltage supplied to the driver array, wherein the duty cycle control module comprises a shift register configured to receive a frequency input from a ring oscillator.”
The primary reason for the indication of the allowability of claim 18 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the input voltage and duty cycle control signal are selected such that the circuit sustains a self-heating effect (SHE) penalty of less than 5°C.”
Conclusion
16. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ULARISLAO CORDOVA whose telephone number is (571)272-4690. The examiner can normally be reached Monday-Friday 7:30 - 5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ULARISLAO CORDOVA/Examiner, Art Unit 2838
/JEFFREY A GBLENDE/Primary Examiner, Art Unit 2838
Prosecution Insights