Prosecution Insights
Last updated: August 16, 2026
Application No. 18/402,497

INTEGRATED CIRCUIT PACKAGES FOR FACILITATING POWER CONVERTER SYSTEMS AND METHODS

Non-Final OA §102§103
Filed
Jan 02, 2024
Examiner
REIDA, MOLLY KAY
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Murata Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
85%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
360 granted / 435 resolved
+14.8% vs TC avg
Minimal +2% lift
Without
With
+2.2%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
22 currently pending
Career history
465
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
50.4%
+10.4% vs TC avg
§102
30.1%
-9.9% vs TC avg
§112
17.2%
-22.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 435 resolved cases

Office Action

§102 §103
DETAILED ACTION Election/Restrictions Applicant's election with traverse of Group I, Species A1 (allegedly claims 1-14) in the reply filed on 05/12/2026 is acknowledged. The traversal is on the ground(s) that a serious search burden does not exist because both groups I and II and each species are within the H10W subclass “which is already a subclass of H10 of the …CPC”. This is not found persuasive because over 1.3 million references exist within the H10W subclass; thus, the Examiner maintains that searching the entire subclass for both groups and all species would provide a search burden. In actuality, individual searches with different search terms and/or subclasses would be required for each group and species – which is also a search burden. The traversal is on the ground(s) that the Restriction Requirement does not address the relationships that are disclosed between Species A1, A2, and A3, as required by MPEP 808.01(a). This is not found persuasive because such relationships are implied by the restriction requirement as a whole; that is, for example, all A species are semiconductor packages while all B species are methods of making semiconductor package. Despite the species having “a relationship”, reasons were advanced leading to the conclusion that the disclosed relation does not prevent restriction (also required by MPEP 808.01(a)) by pointing out the (independent or distinct) differences between the species. Thus, the requirements of MPEP 808.01(a) are considered to have been met. Furthermore, claims 2-5 and 14 drawn to non-elected species A2 and claims 7 and 12 drawn to non-elected species A3 are hereby withdrawn. The requirement is still deemed proper and is therefore made FINAL. Information Disclosure Statement The information disclosure statement (IDS) submitted on 12/20/2024 and 05/01/2025 has been considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wen et al. (US Pub. 2011/0292632). Regarding independent claim 1, Wen teaches a semiconductor package (Fig. 7; para. 0029) comprising: a leadframe (12) (para. 0020); an integrated circuit (IC) die (40) coupled to the leadframe (para. 0021), wherein the IC die comprises a plurality of switches (46, 48) coupled in series between an input voltage and a ground reference (para. 0021); a plurality of metal clips (66, 68) (para. 0025); at least one energy storage component (74) coupled to the IC die via the plurality of metal clips, wherein each of the at least one energy storage component is coupled to a respective subset of the plurality of switches via a respective subset of the plurality of metal clips (para. 0026-0027); and a mold compound (96) to encapsulate the leadframe, the IC die, the plurality of metal clips, and the at least one energy storage component (para. 0028). Re claim 6, Wen teaches wherein the plurality of metal clips are coupled to the leadframe, and wherein the at least one energy storage component is coupled to the leadframe via the plurality of metal clips (Fig. 7; para. 0025-0027). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Wen et al. (US Pub. 2011/0292632) in view of Medic et al. (US Pub. 2023/0017391). Re claim 8, Wen teaches wherein the plurality of switches may comprises; for example, a plurality of vertical transistors (para. 0023). Wen is silent with respect to lateral transistors, in particular. Medic teaches a semiconductor package wherein semiconductor transistors can be implemented as vertical devices or lateral devices (para. 0047); that is, both vertical and lateral devices are known in the art and choosing one over the other would have been an obvious matter of engineering choice. Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Wen et al. (US Pub. 2011/0292632) in view of Qian et al. (US Pub 2010/0232131). Re claim 9, Wen does teach wherein a top surface of at least a portion of the at least one energy storage component is covered with the molding rather than exposed. Qian teaches a semiconductor package wherein a top surface of at least a portion of the at least one energy storage component may be preferably exposed (Fig. 2A; para. 0021, 0030) or not (para. 0033). It would have been obvious to one of ordinary skill in the art at the time of filing to modify the package of Wen such that a top surface of at least a portion of the at least one energy storage component is exposed as taught by Qian for the purpose of; for example, forming a thinner package. With regard to “to provide a thermal path” – this language amounts to a functional limitation (MPEP 2114). The exposure of the capacitor provides a thermal path as a function of its structure, which is taught by the prior art. Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wen et al. (US Pub. 2011/0292632) in view of Hebert et al. (US Pub. 2012/0098090), Giuliano (US Pub. 2014/0369018), and Official Notice. Re claim 10, Wen teaches wherein the semiconductor package is a quad flat no-lead package (Figs. 7, 11 – while the specific term “quad flat no-lead package” is not used, it can be seen from the Figures 7 and 11 that the package of Figures 7 and 11 could be considered quad flat no-lead packages because they have the same features as one). Wen teaches a second semiconductor die (108) wherein the second IC die further comprises a control circuit configured to control a state of at least a subset of switches of the plurality of switches (para. 0031). Wen does not teach wherein the control circuitry is part of the same IC die comprising the switches. Hebert teaches a similar package wherein the control circuitry is part of the same IC die comprising the switches (para. 0018). It would have been obvious to one of ordinary skill within the art at the time of filing to modify the disclosure of Wen such that the controlling circuitry was formed as part of the IC die 40 instead of as a separate die for the purpose of; for example, reducing package footprint and simplifying process flow. Wen teaches wherein the at least one energy storage component comprises at least one capacitor (para. 0026). Wen is silent with respect to wherein the capacitor is a multi-layer ceramic capacitor, specifically. Giuliano teaches a similar package wherein the capacitors are multi-layer ceramic capacitors (para. 0007, 0048). Furthermore, the Examiner is taking Official Notice that multi-layer ceramic capacitors are known to have the advantages of being cost-effective because they are mass produced, having a compact size, and high reliability. It would have been obvious to one of ordinary skill in the art at the time of filing to use a multi-layer ceramic capacitor as taught by Giuliano as the capacitor of Wen with a reasonable expectation of success and one of ordinary skill in the art at the time of filing would have been motivated to use a multi-layer ceramic capacitor for the above disclosed advantages. Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Wen et al. (US Pub. 2011/0292632) in view of Hebert et al. (US Pub. 2010/0133674), Qian et al. (US Pub 2010/0232131), and Official Notice. Re claim 11, Wen teaches wherein a front surface of the IC die faces the capacitor and is coupled to the plurality of metal clips, and wherein a back surface of the IC die opposite the front surface is coupled to the leadframe via a die attach layer. In other words, the IC die of Wen could be considered “normally oriented” as opposed to “flip chip oriented”. Hebert teaches a semiconductor package wherein the IC dies may be normally oriented or flip-chip oriented (para. 0072). Hebert is silent with respect to solder bumps. Qian also teaches a semiconductor package wherein the IC die may be normally oriented (Fig. 1B) or flip-chip oriented (Fig. 1C) wherein the flip-chip orientation uses solder bumps to attach the IC die to the carrier. It would have been obvious to one of ordinary skill in the art at the time of filing that the IC die of Wen could be normally oriented or flip-chip mounted and choosing one over the other would have been a simple matter of engineering choice. Furthermore, the Examiner is taking Official Notice that flip-chips have some known advantages such as high-density interconnections which can result in a smaller package. When choosing flip-chip orientation for the above known advantages, the limitations of claim 11 of “wherein a front surface of the IC die faces the leadframe and is coupled to the leadframe via a plurality of solder bumps, and wherein a back surface of the IC die opposite the front surface is coupled to the plurality of metal clips” would naturally follow. Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Wen et al. (US Pub. 2011/0292632) in view of Hebert et al. (US Pub. 2010/0133674), Qian et al. (US Pub 2010/0232131), and/or Giuliano (US Pub. 2014/0369018). Re claim 13, Wen teaches an electronic device comprising the semiconductor package of claim 1 (refer to rejection of claim 1), the electronic device comprising: a power converter comprising: the semiconductor package (para. 0002 – Wen teaches the package of claim 1 may be used as part of a voltage regulator which is a type of power converter). Wen is silent with respect to a capacitor coupled to and external to the semiconductor package. Output filters such as LC filters comprising a capacitor coupled to and external to a semiconductor package are known in the art as evidenced by Hebert ‘674 Fig. 1, Qian Fig. 1, Giuliano Figs. 3A, 4. It would have been obvious to one of ordinary skill in the art at the time of filing to include an LC filter as taught by Hebert, Qian, and/or Giuliano coupled to and external to the semiconductor package of Wen to arrive at the claimed invention for the purpose of providing a smoother/clearer output signal. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408)918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOLLY K REIDA/Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Jan 02, 2024
Application Filed
Mar 27, 2024
Response after Non-Final Action
Jul 14, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12690321
DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME
3y 9m to grant Granted Jul 21, 2026
Patent 12684823
LAYER STRUCTURES INCLUDING CONFIGURATION INCREASING OPERATION CHARACTERISTICS, METHODS OF MANUFACTURING THE SAME, ELECTRONIC DEVICES INCLUDING LAYER STRUCTURES, AND ELECTRONIC APPARATUSES INCLUDING ELECTRONIC DEVICES
4y 1m to grant Granted Jul 14, 2026
Patent 12672279
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 4m to grant Granted Jun 30, 2026
Patent 12666590
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
3y 6m to grant Granted Jun 23, 2026
Patent 12660161
CAPACITOR STRUCTURE AND METHOD FOR MANUFACTURING SAME, SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME
3y 1m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
85%
With Interview (+2.2%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 435 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month