Office Action Predictor
Last updated: April 16, 2026
Application No. 18/402,519

USING A VECTOR PROCESSOR TO CONFIGURE A DIRECT MEMORY ACCESS SYSTEM FOR FEATURE TRACKING OPERATIONS IN A SYSTEM ON A CHIP

Non-Final OA §103
Filed
Jan 02, 2024
Examiner
NAM, HYUN
Art Unit
2183
Tech Center
2100 — Computer Architecture & Software
Assignee
Nvidia Corporation
OA Round
3 (Non-Final)
86%
Grant Probability
Favorable
3-4
OA Rounds
2y 6m
To Grant
86%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
750 granted / 867 resolved
+31.5% vs TC avg
Minimal -0% lift
Without
With
+-0.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
20 currently pending
Career history
887
Total Applications
across all art units

Statute-Specific Performance

§101
10.4%
-29.6% vs TC avg
§103
38.4%
-1.6% vs TC avg
§102
16.2%
-23.8% vs TC avg
§112
19.2%
-20.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 867 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/12/2026 has been entered. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 10-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bailey et al. (U.S. Publication 2016/03313445), hereinafter Bailey in view of Vemula (U.S. Publication 2016/0313445), hereinafter Vemula. . Referring to claim 1, Bailey teaches, as claimed, a method comprising: storing (loading main memory, see Paragraph 60; and see Fig. 9B, Main Memory), using a direct memory access (DMA) system (direct memory access, see Paragraph 60; and Fig. 9A, DMA Request/Grant 908/910) , first data in (see Fig. 9A, Memory Data In) one or more memories for access by a processor (processor 128, see Paragraph 60; and see Fig. 9A RISC Processor 128), the first data reading (from external flash memory, see Paragraph 60), using the DMA system, second data (hold values, see Paragraph 57) stored in the one or more memories (memory cells, see Paragraph 57) by the processor, the second data representative of one or more locations (position reference, see Paragraph 47) associated with the tracked feature as determined by the processor using at least a portion (data reduction, see Paragraph 47) of the first data (adjustment of range, see Paragraph 47); and updating, using the DMA system and based at least on the one or more locations (position references, see Paragraph 47), the first data Bailey does not disclose expressly data representative of the one or more descriptors. Vemula does disclose data representative of the one or more descriptors (description information makes … self-documenting, see Paragraph 21). At the time of the invention it would have been obvious to a person of ordinary skill in the art to incorporate DMA descriptors of Vemula into Bailey. The suggestion/motivation for doing so would have been to manage functioning DMA transfers (DMA descriptor manger, see Vemula Paragraph 3) . As to claim 11, the modification teaches the method of claim 10, further comprising: determining, using the DMA system and with respect to the one or more memories, one or more previous locations associated with the tracked feature (ladar sensor, see Abstract; Note, implicitly ladar sensor senses movement, therefore time of past and present), wherein the storing the first data representative of the one or more descriptors associated with the tracked feature is based at least on the one or more previous locations (Note, ladar sensor is based on location) . As to claim 12, the modification teaches the method of claim 11, wherein: the one or more previous locations associated with the tracked (tracking, see Paragraph 37) feature are determined using second sensor (ladar sensors, see Abstract) data obtained using a machine (see Fig. 1) ; and the one or more locations associated with the tracked feature are determined using the sensor data obtained using the machine and the at least the portion of the first data (portion, see Paragraph 43). As to claim 13, the modification teaches the method of claim 10, further comprising: determining, using the DMA system and based at least on the first data, the one or more locations (position references, see Paragraph 47) associated with the tracked feature. As to claim 14, the modification teaches the method of claim 10, wherein: the storing the first data representative of the one or more descriptors associated with the tracked features is in a first memory of the one or more memories; and the reading the second data representative of the one or more locations associated with the tracked feature is from a second memory of the one or more memories (see Fig. 8B, Memory 1-3) . As to claim 15, the modification teaches the method of claim 10, further comprising: receiving, using the DMA system, an indication that the one or more locations associated with the tracked feature are stored in the one or more memories, wherein the reading the second data representative of the one or more locations associated with the tracked feature is based at least on the receiving the indication (see Fig. 8B, Peak Detect and Detector Array) . As to claim 18, the modification teaches the method of claim 10, wherein the updating the first data representative of the one or more descriptors associated with the tracked feature comprises storing, using the DMA system and in the one or more memories, third data representative of at least one of the one or more descriptors (see Vemula Fig. 5, Descriptor Generator) associated with the tracked feature or one or more second descriptors associated with the tracked feature. As to claim 19, it is directed to a system to implement the method as set forth in claim 10. Therefore, it is rejected on the same basis as set forth hereinabove. As to claim 20, the modification teaches the system of claim 19, wherein the system is comprised in at least one of: a control system for an autonomous or semi-autonomous machine; a perception system for an autonomous or semi-autonomous machine; a system for performing simulation operations; a system for performing deep learning operations; a system on chip (SoC);a system including a programmable vision accelerator (PVA);a system including a vison processing unit (GPU, see Paragraph 60) ; a system implemented using an edge device; a system implemented using a robot; a system incorporating one or more virtual machines (VMs); a system implemented at least partially in a data center; or a system implemented at least partially using cloud computing resources. . Allowable Subject Matter Claim 1-9 are allowed. Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hyun Nam whose telephone number is (571) 270-1725 and fax number is (571) 270-2725. The examiner can normally be reached on Monday through Friday 8:30 AM to 5:00 PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HYUN NAM/Primary Examiner, Art Unit 2183
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Prosecution Timeline

Jan 02, 2024
Application Filed
Jun 14, 2025
Non-Final Rejection — §103
Sep 04, 2025
Applicant Interview (Telephonic)
Sep 05, 2025
Response Filed
Sep 06, 2025
Examiner Interview Summary
Dec 12, 2025
Final Rejection — §103
Jan 12, 2026
Request for Continued Examination
Jan 23, 2026
Response after Non-Final Action
Mar 20, 2026
Non-Final Rejection — §103
Mar 31, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
86%
Grant Probability
86%
With Interview (-0.1%)
2y 6m
Median Time to Grant
High
PTA Risk
Based on 867 resolved cases by this examiner. Grant probability derived from career allow rate.

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