DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 and/or 103 rejections have been provided in parenthesis.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Claim Objections
Claims 14, 19, and 20 are objected to because of the following informalities:
claim 14 recites “a through connecting portion that penetrates the mold layer to connect the first redistribution portion and the second redistribution portion, the through connecting portion at the first region”; this limitation should be corrected to “a through connecting portion that penetrates the mold layer to connect the first redistribution portion and the second redistribution portion, the through connecting portion being disposed at the first region”.
Claim 19 recites “and a heat source mark at the second region to overlap at least a portion of the second element in a vertical direction at an outer surface of the second redistribution portion and configured as a bonding member, the vertical direction extending perpendicular to an in-plane direction of the lower semiconductor package” but should be corrected to recite:
“a heat source mark at the second region to overlap at least a portion of the second element in a vertical direction at an outer surface of the second redistribution portion, the vertical direction extending perpendicular to an in-plane direction of the lower semiconductor package; and wherein the heat source mark is configured as a bonding member”.
claim 20 recites:
“The lower semiconductor package of claim 19, wherein the first region is at one side of one direction of the lower semiconductor package and the second region is disposed at another side of the one direction of the lower semiconductor package, the semiconductor chip further includes a through connecting portion that penetrates the mold layer at the first region to connect the first redistribution portion and the second redistribution portion, and the semiconductor chip is shifted toward the other side of the one direction”.
However, in order to avoid any potential issues concerning 35 U.S.C. 112(a), the claim should be corrected to recite:
“The lower semiconductor package of claim 19, further comprising a through connecting portion that penetrates the mold layer at the first region to connect the first redistribution portion and the second redistribution portion, and wherein the first region is at one side of one direction of the lower semiconductor package and the second region is disposed at another side of the one direction of the lower semiconductor package, the semiconductor chip being shifted toward the other side of the one direction”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 7, 11, 13-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (WO 2023087323 A1), hereinafter referred to as “Zhang” (all following citations to Zhang refer to the copy of Zhang included with this Action), in view of Rotem et al. (US 20210064804 A1), hereinafter referred to as “Rotem”.
PNG
media_image1.png
694
995
media_image1.png
Greyscale
Regarding claim 1, Zhang discloses a stacked semiconductor package (Zhang fig. 3, 200), comprising:
a first semiconductor package (see Zhang fig. 3: the first semiconductor package includes electronic integrated circuit 20, first redistribution layer 51, second redistribution layer 52, molding compound 40, and overmolded vias 401) that includes a first region (see Zhang fig. 3) and a second region (see Zhang fig. 3);
the first semiconductor package including a semiconductor chip (Zhang fig. 3, 20; see page 8, lines 24-27);
a second semiconductor package (Zhang fig. 3, 30; see page 10, lines 18-23) on the first region of the first semiconductor package;
and a member for heat dissipation (Zhang fig. 3, 61 and 522; see page 10, lines 29-40) that is disposed at the second region of the first semiconductor package, the member for heat dissipation overlapping at least a portion of the semiconductor chip in a vertical direction (see Zhang fig. 3), the vertical direction extending perpendicular to an in-plane direction of the first semiconductor package (see Zhang fig. 3; heat conduction block 61 overlaps a portion of electronic integrated circuit 20 within the second region of the first semiconductor package in a vertical direction extending perpendicular from the first semiconductor package).
Zhang fails to disclose the semiconductor chip including a first element at the first region and a second element at the second region.
Rotem discloses a system-on-chip (SoC) semiconductor chip (Rotem fig. 11, 1100; see [0028] and [0090]) including a first element (Rotem fig. 11, 1130; see [0091]) at the first region (see Rotem fig. 11; DSP unit is disposed on one side (i.e. first region) of SoC 1100 along a length direction) and a second element (Rotem fig. 11, 1110; see [0090]) at the second region (see Rotem fig. 11; CPU domain 1110 is disposed on another side (i.e. second region) of SoC 1100 along a length direction).
The semiconductor chip of Rotem is incorporated as the semiconductor chip of the device of Zhang, wherein the combination discloses a semiconductor chip, the semiconductor chip including a first element at the first region and a second element at the second region; and the member for heat dissipation overlapping at least a portion of the second element in a vertical direction (since heat conducting block 61 vertically overlaps most of electronic integrated circuit 20 in the second region in the device of Zhang (see Zhang fig. 3), the member for heat dissipation vertically overlaps at least a portion of the second element of the semiconductor chip (from Rotem) in the combined device), the vertical direction extending perpendicular to an in-plane direction of the first semiconductor package.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Zhang with the semiconductor chip of Rotem to enable high performance for communication functions (See Rotem [0090]);
and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of the semiconductor chip of Zhang (Zhang fig. 3, 20) with the semiconductor chip of Rotem (Rotem fig. 11, 1100) to obtain predictable results (see Rotem [0090]; the substitution would lead to predictably higher performance for communication functions for the chip).
Regarding claim 2, Zhang and Rotem disclose the stacked semiconductor package of claim 1, wherein the second element (Rotem fig. 11, 1110) is a higher power element than the first element (Rotem fig. 11, 1130; see [0090]-[0091]: “CPU domain 1110 may be a quad core processor having … high power processor cores. … A DSP unit 1130 may provide one or more low power DSPs for handling low-power multimedia applications such as music playback, audio/video and so forth”; the DSP unit performs low power media functions while the CPU domain operates through high power processing cores).
Regarding claim 4, Zhang and Rotem disclose the stacked semiconductor package of claim 1, wherein the second element (Rotem fig. 11, 1110) includes a central processing unit (CPU) (see Rotem fig. 11 and [0090]).
Regarding claim 7, Zhang and Rotem disclose the stacked semiconductor package of claim 1, wherein the member for heat dissipation (Zhang fig. 3, 61 and 522; see page 10, lines 29-40) includes a heat source mark (Zhang fig. 3, 522).
Regarding claim 11, Zhang and Rotem disclose the stacked semiconductor package of claim 1, wherein the member for heat dissipation (Zhang fig. 3, 61 and 522) includes a heat source mark (Zhang fig. 3, 522) configured as a bonding member (see Zhang fig. 3 and page 10, lines 30-32; heat conduction block 61 is bonded to thermally conductive layer 522, so conductive layer 522 is a bonding member), and a heat dissipation member (Zhang fig. 3, 61) bonded to the heat source mark.
PNG
media_image2.png
693
995
media_image2.png
Greyscale
Regarding claim 13, Zhang and Rotem disclose the stacked semiconductor package of claim 11, wherein the heat dissipation member (Zhang fig. 3, 61) includes a metal (see Zhang page 10, lines 36-38), and one surface of the second semiconductor package (Zhang fig. 3, 30; see sixth surface 306) at an opposite side of the first semiconductor package and one surface of the heat dissipation member (see Zhang fig. 3: the surface of heat conducting block 61 opposite thermally conductive layer 522) are coplanar (see Zhang fig. 3).
PNG
media_image3.png
695
1183
media_image3.png
Greyscale
Regarding claim 14 (applicant is reminded of the above claim objection), Zhang and Rotem disclose the stacked semiconductor package of claim 1,
wherein the first semiconductor package (see Zhang fig. 3: the first semiconductor package includes electronic integrated circuit 20, first redistribution layer 51, second redistribution layer 52, molding compound 40, and overmolded vias 401) further includes a first redistribution portion (Zhang fig. 3, 51; see page 8, lines 40-46) and a second redistribution portion (Zhang fig. 3, 52; see page 9, lines 1-8) respectively on opposite surfaces of the semiconductor chip (Rotem fig. 11, 1100; c.f. Zhang fig. 3, 20),
a mold layer (Zhang fig. 3, 40; see page 8, lines 28-32) surrounding the semiconductor chip between the first redistribution portion and the second redistribution portion,
and a through connecting portion (Zhang fig. 3, 401; see page 8, lines 33-39) that penetrates the mold layer to connect the first redistribution portion and the second redistribution portion (see Zhang fig. 3 and page 9, lines 21-24: via 401 connects the two active semiconductor components through the first and second redistribution layers), the through connecting portion being disposed at the first region (see Zhang fig. 3).
PNG
media_image1.png
694
995
media_image1.png
Greyscale
Regarding claim 15, Zhang and Rotem disclose the stacked semiconductor package of claim 1, wherein the first region (see Zhang fig. 3) is at one side of one direction of the first semiconductor package (see Zhang fig. 3: the first semiconductor package includes electronic integrated circuit 20, first redistribution layer 51, second redistribution layer 52, molding compound 40, and overmolded vias 401) and the second region (see Zhang fig. 3; the second region is located at an opposite side of the first semiconductor package relative to the first region) is at another side of the one direction of the first semiconductor package, and the semiconductor chip (Rotem fig. 11, 1100; c.f. Zhang fig. 3, 20) is shifted toward the other side of the one direction (the semiconductor chip (at the location of the electronic integrated circuit 20 as shown in Zhang fig. 20) is shifted toward the second region of the first semiconductor package at the other side of said one direction).
PNG
media_image4.png
695
1183
media_image4.png
Greyscale
Regarding claim 16, Zhang discloses a stacked semiconductor package (Zhang fig. 3, 200), comprising:
a first semiconductor package (see Zhang fig. 3: the first semiconductor package includes electronic integrated circuit 20, first redistribution layer 51, second redistribution layer 52, molding compound 40, and overmolded vias 401) that includes a first region (see Zhang fig. 3) and a second region (see Zhang fig. 3);
the first semiconductor package including a semiconductor chip (Zhang fig. 3, 20; see page 8, lines 24-27);
a second semiconductor package (Zhang fig. 3, 30; see page 10, lines 18-23) at the first region of the first semiconductor package;
and a heat source mark (Zhang fig. 3, 522; see page 10, lines 36-40) at the second region to overlap at least a portion of the semiconductor chip in a vertical direction, the vertical direction extending perpendicular to an in-plane direction of the first semiconductor package (see Zhang fig. 3; first thermally conductive layer 522 overlaps a portion of electronic integrated circuit 20 within the second region of the first semiconductor package in a vertical direction extending perpendicular from first semiconductor package).
Zhang fails to disclose the semiconductor chip including a first element at the first region and a second element at the second region, the second element being a higher power element than the first element;
Rotem discloses a system-on-chip (SoC) semiconductor chip (Rotem fig. 11, 1100; see [0028] and [0090]) including a first element (Rotem fig. 11, 1130; see [0091]) at the first region (see Rotem fig. 11; DSP unit is disposed on one side (i.e. first region) of SoC 1100 along a length direction) and a second element (Rotem fig. 11, 1110; see [0090]) at the second region (see Rotem fig. 11; CPU domain 1110 is disposed on another side (i.e. second region) of SoC 1100 along a length direction), wherein the second element is a higher power element than the first element (see Rotem [0090]-[0091]: “CPU domain 1110 may be a quad core processor having … high power processor cores. … A DSP unit 1130 may provide one or more low power DSPs for handling low-power multimedia applications such as music playback, audio/video and so forth”).
The semiconductor chip of Rotem is incorporated as the semiconductor chip of the device of Zhang, wherein the combination discloses a semiconductor chip, the semiconductor chip including a first element at the first region and a second element at the second region, the second element being a higher power element than the first element; and a heat source mark overlapping at least a portion of the second element in a vertical direction (since conductive layer 522 vertically overlaps most of electronic integrated circuit 20 in the second region in the device of Zhang, the heat source mark vertically overlaps at least a portion of the second element of the semiconductor chip (from Rotem) in the combined device), the vertical direction extending perpendicular to an in-plane direction of the first semiconductor package.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Zhang with the semiconductor chip of Rotem to enable high performance for communication functions (See Rotem [0090]);
and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of the semiconductor chip of Zhang (Zhang fig. 3, 20) with the semiconductor chip of Rotem (Rotem fig. 11, 1100) to obtain predictable results (see Rotem [0090]; the substitution would lead to predictably higher performance for communication functions for the chip).
Regarding claim 17, Zhang and Rotem disclose the stacked semiconductor package of claim 16, wherein the heat source mark (Zhang fig. 3, 522; see page 10, lines 36-40) is configured as a bonding member (see Zhang fig. 3 and page 10, lines 30-31; heat conduction block 61 is bonded to thermally conductive layer 522, so conducive layer 522 is a bonding member), and the stacked semiconductor package further comprises a heat dissipation member (Zhang fig. 3, 61) bonded to the second region (see Zhang fig. 3) of the first semiconductor package (see Zhang fig. 3: the first semiconductor package includes electronic integrated circuit 20, first redistribution layer 51, second redistribution layer 52, molding compound 40, and overmolded vias 401) by the heat source mark.
PNG
media_image5.png
695
1183
media_image5.png
Greyscale
Regarding claim 19 (applicant is reminded of the above claim objection), Zhang discloses a lower semiconductor package (see Zhang fig. 3: the lower semiconductor package includes electronic integrated circuit 20, first redistribution layer 51, second redistribution layer 52, molding compound 40, and overmolded vias 401) for a stacked semiconductor package (see Zhang fig. 3), the lower semiconductor package comprising:
a semiconductor chip (Zhang fig. 3, 20; see page 8, lines 24-27);
a first redistribution portion (Zhang fig. 3, 51) and a second redistribution portion (Zhang fig. 3, 52) respectively on opposite surfaces of the semiconductor chip;
a mold layer (Zhang fig. 3, 40; see page 8, lines 28-32) surrounding the semiconductor chip between the first redistribution portion and the second redistribution portion;
a heat source mark (Zhang fig. 3, 522; see page 10, lines 29-40) at a second region (see Zhang fig. 3) to overlap at least a portion of the semiconductor chip in a vertical direction at an outer surface of the second redistribution portion (see Zhang fig. 3: thermally conductive layer 522 is at an outer portion of redistribution layer 52 and overlaps a portion of electronic integrated circuit 20 over the second region in a vertical direction extending perpendicular to electronic integrated circuit 20), the vertical direction extending perpendicular to an in-plane direction of the lower semiconductor package;
and wherein the heat source mark is configured as a bonding member (see Zhang fig. 3 and page 10, lines 30-31; heat conduction block 61 is bonded to thermally conductive layer 522, so conductive layer 522 is a bonding member).
Zhang fails to disclose a semiconductor chip including a first element at a first region and a second element at a second region, the second element being a higher power element than the first element.
Rotem discloses a system-on-chip (SoC) semiconductor chip (Rotem fig. 11, 1100; see [0028] and [0090]) including a first element (Rotem fig. 11, 1130; see [0091]) at the first region (see Rotem fig. 11; DSP unit is disposed on one side (i.e. first region) of SoC 1100 along a length direction) and a second element (Rotem fig. 11, 1110; see [0090]) at the second region (see Rotem fig. 11; CPU domain 1110 is disposed on another side (i.e. second region) of SoC 1100 along a length direction), wherein the second element is a higher power element than the first element (see Rotem [0090]-[0091]: “CPU domain 1110 may be a quad core processor having … high power processor cores. … A DSP unit 1130 may provide one or more low power DSPs for handling low-power multimedia applications such as music playback, audio/video and so forth”).
The semiconductor chip of Rotem is incorporated as the semiconductor chip of the device of Zhang, wherein the combination discloses a semiconductor chip including a first element at a first region and a second element at a second region, the second element being a higher power element than the first element; and a heat source mark at the second region to overlap at least a portion of the second element in a vertical direction (since conductive layer 522 vertically overlaps most of electronic integrated circuit 20 in the second region in the device of Zhang (see Zhang fig. 3), the heat source mark vertically overlaps at least a portion of the second element of the semiconductor chip (from Rotem) in the combined device) at an outer surface of the second redistribution layer, the vertical direction extending perpendicular to an in-plane direction of the first semiconductor package.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Zhang with the semiconductor chip of Rotem to enable high performance for communication functions (See Rotem [0090]);
and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of the semiconductor chip of Zhang (Zhang fig. 3, 20) with the semiconductor chip of Rotem (Rotem fig. 11, 1100) to obtain predictable results (see Rotem [0090]; the substitution would lead to predictably higher performance for communication functions for the chip).
Regarding claim 20 (applicant is reminded of the above claim rejection), Zhang and Rotem disclose the lower semiconductor package of claim 19, further comprising a through connecting portion (Zhang fig. 3, 401; see page 8, lines 33-39; also see Zhang page 9, lines 21-24: via 401 connects the two active semiconductor components through the first and second redistribution layers) that penetrates the mold layer (Zhang fig. 3, 40; see page 8, lines 28-32) at the first region (see Zhang fig. 3) to connect the first redistribution portion (Zhang fig. 3, 51) and the second redistribution portion (Zhang fig. 3, 52), and wherein the first region (see Zhang fig. 3) is at one side of one direction of the lower semiconductor package and the second region (see Zhang fig. 3) is disposed at another side of the one direction of the lower semiconductor package, the semiconductor chip being shifted toward the other side of the one direction (see Zhang fig. 3: in the combined device, the semiconductor chip is shifted towards the second region (similar to integrated circuit 20 in the device of Zhang)).
Claims 1 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang, in view of Nagamura et al. (US 20090077524 A1), hereinafter as “Nagamura”.
PNG
media_image1.png
694
995
media_image1.png
Greyscale
Regarding claim 1, Zhang discloses a stacked semiconductor package (Zhang fig. 3, 200), comprising:
a first semiconductor package (see Zhang fig. 3: the first semiconductor package includes electronic integrated circuit 20, first redistribution layer 51, second redistribution layer 52, molding compound 40, and overmolded vias 401) that includes a first region (see Zhang fig. 3) and a second region (see Zhang fig. 3);
the first semiconductor package including a semiconductor chip (Zhang fig. 3, 20; see page 8, lines 24-27);
a second semiconductor package (Zhang fig. 3, 30; see page 10, lines 18-23) on the first region of the first semiconductor package;
and a member for heat dissipation (Zhang fig. 3, 61 and 522; see page 10, lines 29-40) that is disposed at the second region of the first semiconductor package, the member for heat dissipation overlapping at least a portion of the semiconductor chip in a vertical direction (see Zhang fig. 3), the vertical direction extending perpendicular to an in-plane direction of the first semiconductor package (see Zhang fig. 3; heat conduction block 61 overlaps a portion of electronic integrated circuit 20 within the second region of the first semiconductor package in a vertical direction extending perpendicular from the first semiconductor package).
Zhang fails to disclose the semiconductor chip including a first element at the first region and a second element at the second region.
Nagamura discloses a semiconductor chip (Nagamura fig. 4, “CHP”; see [0067]) including a first element (Nagamura fig. 4, C7) at the first region (see Nagamura fig. 4: input/output circuit C7 is disposed on one side (i.e. first region) of semiconductor chip CHP along a length direction) and a second element (Nagamura fig. 4, C1) at the second region (see Nagamura fig. 4: logic circuit C1 is disposed on another side (i.e. second region) of semiconductor chip CHP along a length direction).
The semiconductor chip of Nagamura is incorporated as the semiconductor chip of the device taught in Zhang, wherein the combination discloses a semiconductor chip, the semiconductor chip including a first element at the first region and a second element at the second region; and the member for heat dissipation overlapping at least a portion of the second element in a vertical direction (since heat conducting block 61 vertically overlaps most of electronic integrated circuit 20 in the second region in the device of Zhang, the member for heat dissipation vertically overlaps at least a portion of the second element of the semiconductor chip (from Nagamura) in the combined device), the vertical direction extending perpendicular to an in-plane direction of the first semiconductor package.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Zhang with the semiconductor chip of Nagamura because the combination is simple substitution of one known element for another to obtain predictable results—the combination involves substituting the semiconductor chip of Nagamura (for which the constituent elements are disclosed) with the semiconductor chip of Zhang (which is essentially a generic integrated circuit due to lack of disclosed details in Zhang) to achieve the predictable result of integrating a semiconductor chip implementing a complex memory/non-memory system into the combined device.
Regarding claim 3, Zhang and Nagamura disclose the stacked semiconductor package of claim 1, wherein the second element (Nagamura fig. 4, C1) has a finer wiring structure or a finer pattern than the first element (Nagamura fig. 4, C7; see Nagamura [0067]: “the wiring that forms the logic circuit C1 is formed with the smallest feature size, and is arranged … with the highest wiring density; on the other hand, the input/output circuit C7 has … a wiring density not as high as that of the logic circuit C1”; note that wiring density is akin to the fineness of the wiring structure”).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang, in view of Rotem, further in view of Kim et al. (US 20200027818 A1), hereinafter referred to as “Kim”.
PNG
media_image6.png
780
602
media_image6.png
Greyscale
Regarding claim 5, the combined device of Zhang and Rotem discloses the stacked semiconductor package of claim 1.
Zhang and Rotem fail to explicitly disclose wherein the member for heat dissipation overlaps an entire portion of the second element in the vertical direction.
Kim discloses a stacked semiconductor package (see Kim fig. 1B and [0019]) comprising: a lower semiconductor chip (Kim fig. 1B, SC1; see [0022]) including a second element (Kim fig. 1B, 111; see [0022]); and a member for heat dissipation (Kim fig. 1B, 140; see [0028]) disposed above the lower semiconductor chip, wherein the member for heat dissipation overlaps an entire portion of the second element in the vertical direction (see Kim fig. 1B and [0028]: heat radiation spacer 140 vertically overlaps the entirety of the heat source 111 shown in Kim fig. 1B).
The vertical overlap teachings of Kim are incorporated with the combined device of Zhang and Rotem wherein the combination discloses wherein the member for heat dissipation overlaps an entire portion of the second element in the vertical direction.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Zhang and Rotem with the teachings of Kim to achieve better alignment between components of the stacked semiconductor package (by positioning the member for heat dissipation to entirely overlap the second element, overall alignment in the device is improved).
Regarding claim 6, the combined device of Zhang and Rotem discloses the stacked semiconductor package of claim 1.
Zhang and Rotem fail to explicitly disclose wherein a size or an area of the member for heat dissipation is equal to or greater than a size or an area of the second element in a plan view.
Kim discloses a stacked semiconductor package (see Kim fig. 1B; see [0019]) comprising: a lower semiconductor chip (Kim fig. 1B, SC1; see [0022]) including a second element (Kim fig. 1B, 111; see [0022]); and a member for heat dissipation (Kim fig. 1B, 140; see [0028]) disposed above the lower semiconductor chip, wherein a size or an area of the member for heat dissipation is equal to or greater than a size or an area of the second element in a plan view (see Kim figs. 1A-1C: while fig. 1C does not show the area of heat source 111 in plan view, figs. 1A-1B together show that the plan-view area of heat radiation spacer 140 must be greater than the plan-view area of a heat source 111; the plan view area of the components is determined solely by their width and length: the width of heat source 111 in the D1 direction is less than the D1 width of spacer 140 (see fig. 1B) and the length of the rightmost heat source 111 in the D2 direction is less than the D2 length of spacer 140).
The relative plan area teachings of Kim are incorporated with the combined device of Zhang and Rotem wherein the combination discloses the stacked semiconductor package of claim 1, wherein a size or an area of the member for heat dissipation is equal to or greater than a size or an area of the second element in a plan view.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Zhang and Rotem with the teachings of Kim to achieve better alignment between components of the stacked semiconductor package (by fully overlapping the second element with the member for heat dissipation, overall alignment in the device is improved).
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang, in view of Rotem, further in view of Yu et al. (US 20210305123 A1), hereinafter referred to as “Yu”.
The combined device of Zhang and Rotem discloses the stacked semiconductor package of claim 7.
Zhang and Rotem fail to disclose wherein the heat source mark includes an adhesive layer between the first semiconductor package and the member for heat dissipation.
Yu discloses a semiconductor package (Yu fig. 1H, 100; see [0012]) comprising a first semiconductor chip (Yu fig. 1H, 110; see [0016]-[0017]), a second semiconductor chip (Yu fig. 1H. 120; see [0016]-[0017]), a mold layer (Yu fig. 1H, 140; see [0022]), a redistribution layer (Yu fig. 1H, 150; see [0026]), and an adhesive layer (Yu fig. 1H, 180; see [0031]) between a portion of the semiconductor package and a member for heat dissipation (Yu fig. 1H, 182; see [0031]).
The adhesive layer of Yu is incorporated into the heat source mark (placed above and included with thermally conductive layer 522 (as shown in Zhang fig. 3)) wherein the combination discloses wherein the heat source mark includes an adhesive layer between the first semiconductor package and the member for heat dissipation.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Zhang and Rotem with the adhesive layer of Yu to further reduce the risk of electrostatic discharge between the semiconductor chip and the member for heat dissipation.
Regarding claim 18, the combined device of Zhang and Rotem discloses the stacked semiconductor package of claim 17.
Zhang and Rotem fail to disclose wherein the heat source mark includes an adhesive layer between the first semiconductor package and the heat dissipation member, or the heat source mark is configured as a portion of an outermost wiring layer of a redistribution portion included in the first semiconductor package.
Yu discloses a semiconductor package (Yu fig. 1H, 100; see [0012]) comprising a first semiconductor chip (Yu fig. 1H, 110; see [0016]-[0017]), a second semiconductor chip (Yu fig. 1H. 120; see [0016]-[0017]), a mold layer (Yu fig. 1H, 140; see [0022]), a redistribution layer (Yu fig. 1H, 150; see [0026]), and an adhesive layer (Yu fig. 1H, 180; see [0031]) between a portion of the semiconductor package and a heat dissipation member (Yu fig. 1H, 182; see [0031]).
The adhesive layer of Yu is incorporated into the heat source mark (placed above and included with thermally conductive layer 522 (as shown in Zhang fig. 3)) wherein the combination discloses wherein the heat source mark includes an adhesive layer between the first semiconductor package and the heat dissipation member.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Zhang and Rotem with the adhesive layer of Yu to further reduce the risk of electrostatic discharge between the semiconductor chip and the member for heat dissipation.
Claims 9-10 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang, in view of Rotem, further in view of Chen et al. (US 20230037331 A1), hereinafter referred to as “Chen”.
PNG
media_image7.png
537
1106
media_image7.png
Greyscale
Regarding claim 9, the combined device of Zhang and Rotem discloses the stacked semiconductor package of claim 7, comprising a redistribution portion (Zhang fig. 3, 52; see page 9, lines 1-2) included in the first semiconductor package (see Zhang fig. 3: the first semiconductor package includes electronic integrated circuit 20, first redistribution layer 51, second redistribution layer 52, molding compound 40, and overmolded vias 401).
Zhang and Rotem fail to explicitly disclose wherein the heat source mark is configured as a portion of an outermost wiring layer of the redistribution portion included in the first semiconductor package.
Chen discloses a stacked semiconductor package (see Chen fig. 17F) with thermal dissipation elements (Chen fig. 16A, 81; c.f. Chen fig. 17F; see [0049]) integrated into a redistribution portion (see Chen fig. 16A: the redistribution portion comprises the various wiring features (26, 36, etc.) below package component 50), the thermal dissipation elements including an electrically-isolated wiring portion (Chen fig. 15, 26T/36T/40T; see [0015] and [0020]) that is bonded to a heat dissipation member (Chen fig. 17F, 82T; see [0048]) and disposed above a semiconductor chip (Chen fig. 17F, 50; see [0024]).
The wiring portion of Chen is incorporated into the combined device of Zhang and Rotem, with the outermost wiring layer (Chen fig. 17F, 26T) of said wiring portion being incorporated as the heat source mark of the previous combined device; and wherein the present combination discloses wherein the heat source mark is configured as a portion of an outermost wiring layer of a redistribution portion included in the first semiconductor package.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Zhang and Rotem with the wiring portion of Chen to reduce the overall amount of conductive material used in the device (compared to the thermally conductive feature of Zhang (Zhang fig. 3, 522), the wiring portion of Chen requires comparably less conductive material and, thereby, reduces the cost of production).
Regarding claim 10, Zhang, Rotem, and Chen, disclose the stacked semiconductor package of claim 9, wherein the heat source mark (Chen fig. 17F, 26T) is configured as a floating wiring portion (Chen fig. 15, 26T/36T/40T) that is not connected to any other wire of the redistribution portion (see Chen [0020]: “Due to thermal dissipation block 39 (e.g., thermal dissipation features 26T/36T/40T) being electrically isolated from electrical signal routing laterally (e.g., electrically isolated from back-side interconnect structure 41) and above (e.g., electrically isolated from package component 50 and metal posts 48), thermal dissipation block 39 may be referred to as … electrically floating”).
Regarding claim 18, the combined device of Zhang and Rotem discloses the stacked semiconductor package of claim 17, comprising a redistribution portion (Zhang fig. 3, 52; see page 9, lines 1-2) included in the first semiconductor package (see Zhang fig. 3: the first semiconductor package includes electronic integrated circuit 20, first redistribution layer 51, second redistribution layer 52, molding compound 40, and overmolded vias 401).
Zhang and Rotem fail to explicitly disclose wherein the heat source mark includes an adhesive layer between the first semiconductor package and the heat dissipation member, or the heat source mark is configured as a portion of an outermost wiring layer of a redistribution portion included in the first semiconductor package.
Chen discloses a stacked semiconductor package (see Chen fig. 17F) with thermal dissipation elements (Chen fig. 16A, 81; c.f. Chen fig. 17F; see [0049]) integrated into a redistribution portion (see Chen fig. 16A: the redistribution portion comprises the various wiring features (26, 36, etc.) below package component 50), the thermal dissipation elements including an electrically-isolated wiring portion (Chen fig. 15, 26T/36T/40T; see [0015] and [0020]) that is bonded to a heat dissipation member (Chen fig. 17F, 82T; see [0048]) and disposed above a semiconductor chip (Chen fig. 17F, 50; see [0024]).
The wiring portion of Chen is incorporated into the combined device of Zhang and Rotem , with the outermost wiring layer (Chen fig. 17F, 26T) of said wiring portion being incorporated as the heat source mark of the previous combined device; and wherein the present combination discloses wherein the heat source mark is configured as a portion of an outermost wiring layer of a redistribution portion included in the first semiconductor package.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Zhang and Rotem with the wiring portion of Chen to reduce the overall amount of conductive material used in the device (compared to the thermally conductive feature of Zhang (Zhang fig. 3, 522), the wiring portion of Chen requires comparably less conductive material and, thereby, reduces the cost of production).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang, in view of Rotem, further in view of Chen, further in view of Yu.
PNG
media_image7.png
537
1106
media_image7.png
Greyscale
The combined device of Zhang and Rotem discloses the stacked semiconductor package of claim 11, comprising a redistribution portion (Zhang fig. 3, 52; see page 9, lines 1-2) included in the first semiconductor package (see Zhang fig. 3: the first semiconductor package includes electronic integrated circuit 20, first redistribution layer 51, second redistribution layer 52, molding compound 40, and overmolded vias 401).
Zhang and Rotem fail to disclose wherein the heat source mark is configured as a portion of an outermost wiring layer of a redistribution portion included in the first semiconductor package, and the heat source mark and the heat dissipation member are directly bonded by a hybrid bonding or are bonded using a separate adhesive layer.
Chen discloses a stacked semiconductor package (see Chen fig. 17F) with thermal dissipation elements (Chen fig. 16A, 81; c.f. Chen fig. 17F; see [0049]) integrated into a redistribution portion (see Chen fig. 16A: the redistribution portion comprises the various wiring features (26, 36, etc.) below package component 50), the thermal dissipation elements including an electrically-isolated wiring portion (Chen fig. 15, 26T/36T/40T; see [0015] and [0020]) that is bonded to a heat dissipation member (Chen fig. 17F, 82T; see [0048]) and disposed above a semiconductor chip (Chen fig. 17F, 50; see [0024]).
The wiring portion of Chen is incorporated into the combined device of Zhang and Rotem, with the outermost wiring layer (Chen fig. 17F, 26T) of said wiring portion being incorporated as the heat source mark of the previous combined device; and wherein the present combination discloses wherein the heat source mark is configured as a portion of an outermost wiring layer of a redistribution portion included in the first semiconductor package.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Zhang and Rotem with the wiring portion of Chen to reduce the overall amount of conductive material used in the device (compared to the heat source mark of the previous combined device (Zhang fig. 3, 522), the wiring portion of Chen requires comparably less conductive material and, thereby, reduces the cost of production).
Yu discloses a semiconductor package (Yu fig. 1H, 100; see [0012]) comprising a first semiconductor chip (Yu fig. 1H, 110; see [0016]-[0017]), a second semiconductor chip (Yu fig. 1H. 120; see [0016]-[0017]), a mold layer (Yu fig. 1H, 140; see [0022]), a redistribution layer (Yu fig. 1H, 150; see [0026]), and an adhesive layer (Yu fig. 1H, 180; see [0031]) bonding a portion of the semiconductor package to a heat dissipation member (Yu fig. 1H, 182; see [0031]).
The adhesive layer of Yu is incorporated into the heat source mark (placed above and included with the wiring portion from Chen (Chen fig. 17F, 26T) of the combined device of Zhang, Rotem, and Chen, wherein the present combination discloses wherein the heat source mark and the heat dissipation member are bonded using a separate adhesive layer.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the previous combined device of Zhang, Rotem, and Chen, with the adhesive layer of Yu to further reduce the risk of electrostatic discharge between the semiconductor chip and the member for heat dissipation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNER F COLLINS whose telephone number is (571)272-5187. The examiner can normally be reached M-F, 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached at (571)272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HAMNER FITZHUGH COLLINS IV/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights