DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed July 24, 2025 have been fully considered but they are not persuasive for the reasons set forth below.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 8, and 10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 11,894,305. Although the claims at issue are not identical, they are not patentably distinct from each other because while the claims have some different language, that language does not result in patentable distinction. Detailed as follows:
18/402618
US 11,894,305
1. (Currently Amended) A microelectronic device, comprising: a stack structure comprising:
tiers respectively comprising conductive material and insulative material vertically adjacent the conductive material; and
a staircase structure having steps individually comprising:
a tread comprising a portion of an upper surface of the conductive material of a respective one of the tiers; and
a riser comprising side surfaces of the conductive material and the insulative material of the respective one of the tiers; and
conductive pad structures on the steps of the staircase structure of the stack structure, the conductive pad structures vertically offset and discrete from one another, having a different material composition than the conductive material of the tiers of the stack structure, and individually comprising:
a first portion horizontally overlapping the tread of a respective one of the steps; and
a second portion horizontally overlapping the tread of an additional one of the steps horizontally neighboring and vertically underlying the respective one of the steps.
1. A microelectronic device, comprising: a stack structure comprising tiers each comprising: conductive material comprising alpha phase tungsten; and
insulative material vertically neighboring the conductive material; a staircase structure having steps comprising horizontal ends of at least some of the tiers of the stack structure;
tungsten pad structures on the steps of the staircase structure, at least a majority of each of the tungsten pad structures comprising beta phase tungsten and each of the tungsten pad structures having a horizontal center that is horizontally offset from a horizontal center of one of the steps directly vertically thereunder; and
conductive contact structures on the tungsten pad structures.8. The microelectronic device of claim 1, wherein each of the tungsten pad structures horizontally extends past horizontal boundaries of the one of the steps of the staircase structure directly vertically thereunder.
8. (Original) The microelectronic device of claim 1, further comprising dielectric spacer structures on the steps of the staircase structure of the stack structure, the second portion of respective ones of the conductive pad structures directly vertically adjacent and horizontally overlapping a respective one of the dielectric spacer structures.
2. (Original) The microelectronic device of claim 1, further comprising dielectric spacer structures on the steps of the staircase structure, the dielectric spacer structures horizontally interposed between the tungsten pad structures and the steps of the staircase structure.
10. (Currently Amended) A memory device, comprising: a stack structure comprising: tiers vertically stacked relative to one another and respectively comprising a conductive structure and an insulative structure vertically neighboring the conductive structure; and
a staircase having steps respectively comprising:
a horizontally extending portion comprising part of an upper surface of the conductive structure of a respective one of the tiers; and
a vertically extending portion comprising side surfaces of the conductive structure and the insulative structure of the respective one of the tiers;
conductive pads on the steps of the staircase of the stack structure, the conductive pads vertically offset and discrete from one another, having a different material composition than the conductive structure of the respective one of the tiers of the stack structure, and the conductive pad structures respectively comprising:
a region on the horizontally extending portion of a respective one of the steps; and
an additional region integral with the region and outside of a horizontal area of the horizontally extending portion of the respective one of the steps;
strings of memory cells vertically extending through the stack structure and horizontally offset from the staircase of the stack structure;
a source structure vertically underlying the stack structure and operably coupled to the strings of memory cells;
data lines vertically overlying the stack structure and operably coupled to the strings of memory cells; and
control circuitry vertically underlying the source structure and operably coupled to the source structure, the data lines, and the conductive pads.
11. (Original) A memory device, comprising: a stack structure comprising tiers each comprising alpha phase tungsten material and insulative material vertically neighboring the alpha phase tungsten material;
strings of memory cells vertically extending through the tiers of the stack structure;
a staircase structure horizontally offset from an array of the strings of memory cells and having steps comprising edges of at least some of the tiers of the stack structure;
beta phase tungsten pad structures directly physically contacting the steps of the staircase structure, each of the beta phase tungsten pad structures having a horizontal center spaced apart from a horizontal center of one of the steps directly vertically thereunder; and
conductive contacts directly physically contacting the beta phase tungsten pad structures; access lines coupled to the conductive contacts; data lines vertically offset from the stack structure and coupled to the strings of memory cells; a source structure offset from the stack structure and the data lines and coupled to the strings of memory cells; and complementary metal-oxide-semiconductor (CMOS) circuitry within a horizontal area of the array of the strings of memory cells and vertically offset from the stack structure, the data lines, and the source structure.
In particular of note the US 11,894,305 comparison of claim 1:Tread/riser language does not create a patentable distinction
The present claim recites the staircase steps as including a tread and riser. This is simply a more detailed way of describing the same staircase structure already claimed in US ‘305 Patent as having steps comprising horizontal ends of tiers.
The underlying architecture is the same:
a staircase exposes tier edges,
the step includes an exposed upper portion and side portion,
and the pad sits on that step.
This is not a patentably distinct structural concept.
“Vertically offset and discrete” language in the claim
The claim already recites:
tungsten pad structures on the steps, and
each pad having a horizontal center offset from the step center.
That inherently requires the pads to be separate step-level structures positioned at different vertical locations along the staircase. The present claim’s “vertically offset and discrete from one another” language merely restates that same arrangement. There is not patentable distinction of that language.
Regarding claim 8, depends from claim 1 and US ‘305 Patent claim 2 are directed to the same staircase pad/spacer arrangement. The application claim recites the spacer relationship from the perspective of the pad’s “second portion” overlapping the spacer, while US ‘305 Patent recites the spacer as being horizontally interposed between the pad and the staircase step. These are not patentably distinct structural features, but rather different verbal descriptions of the same geometry.
Claim 10 is rejected under the doctrine of obvious-type double patenting over claim 11 of US ‘305. The claimed memory device of present claim 10 recites the same inventive concept as the earlier claim, namely a stacked memory structure having a staircase region, conductive pad structures positioned on staircase steps, memory strings extending through the stack, and associated source, data line, and control circuitry. Although present claim 10 recites the staircase in terms of a “horizontally extending portion” and a “vertically extending portion,” and recites the conductive pads as including a “region” and an “additional region,” these differences are merely verbal or geometrical rephrasings of the earlier claim’s pad structures directly physically contacting the staircase steps and having a horizontal center spaced apart from the step center directly thereunder. The present claim therefore does not define a patentably distinct invention from claim 11 of US ‘305.
The application claims and the US '305 claims are directed to the same basic invention: a staircase structure in a 3D NAND-type stack having alpha-phase tungsten conductive tiers and beta-phase tungsten pad structures on staircase steps, along with associated spacers, fill, contacts, memory strings, source structures, data lines, and control circuitry. The differences between the claims are limited to minor geometric refinements, alternate claim phrasing, or routine species selections such as dopant lists. Accordingly, the application claims are not patentably distinct from the US '305 claims.
Allowable Subject Matter
Claims 2-7, 9, and 11-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 19 and 20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Applicant’s microelectronic device having a staircase structure with conductive pad structures that are vertically offset and discrete, and that include a first portion horizontally overlapping a tread of a respective step and a second portion horizontally overlapping a tread of an additional, horizontally neighboring and vertically underlying step.
The prior art of record, including the references considered, does not teach or suggest this specific pad arrangement in combination with the claimed staircase structure, particularly where the conductive pad structures have a different material composition than the conductive material of the tiers and span two neighboring treads at different vertical levels in the manner recited.
In particular, while the cited references disclose general staircase-type semiconductor structures and, in some instances, thickened contact portions or cascade-type pad arrangements, they do not disclose the claimed two-step horizontal overlap geometry of the conductive pad structures in the context of the claimed stack structure.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUE A PURVIS whose telephone number is (571)272-1236. The examiner can normally be reached M-F 0830 to 1630.
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/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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