Prosecution Insights
Last updated: April 19, 2026
Application No. 18/402,668

SOCKET DEVICE FOR TESTING ICs

Final Rejection §103
Filed
Jan 02, 2024
Examiner
BARRON, JEREMIAH JOHN
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Jae Baek Hwang
OA Round
2 (Final)
78%
Grant Probability
Favorable
3-4
OA Rounds
2y 4m
To Grant
74%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allow Rate
14 granted / 18 resolved
+9.8% vs TC avg
Minimal -4% lift
Without
With
+-3.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
37 currently pending
Career history
55
Total Applications
across all art units

Statute-Specific Performance

§101
3.4%
-36.6% vs TC avg
§103
52.0%
+12.0% vs TC avg
§102
18.4%
-21.6% vs TC avg
§112
22.7%
-17.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 18 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment The amendment filed on 2026-01-22 has been entered. Claim(s) 1-2, and 4-8 remain pending in this application. Claim(s) 1, 4 have been amended. Claim(s) 3 have been canceled. Claim(s) 8 have been newly added. Response to Arguments Applicant’s arguments with respect to claim(s) 1 and its dependents have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-2, 4-6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Inuma (20230138105-A1) in view of Chung et al. (WO-2023277442-A1 – Refer to attached machine translation for references cited). Regarding Claim 1, Inuma teaches a socket device for testing integrated circuits (ICs) including ground probes (Fig 1: ground probe, 2B) and signal probes (Fig 1: signal probe, 2A), the socket device comprising: an insulating socket body (Fig 1: first-fourth members, 31-34, Para [0037] teaches the members being insulated) having ground holes (Fig 1: hollow portion, 36) to accommodate the ground probes and signal holes (Fig 1: hollow portion, 35) to accommodate the signal probes; a conductive ground plating layer (Fig 1: conductive films, 33a or 34a | Para [0062] teaches they may be grounded) formed on a surface of each of the ground holes (Can be seen in Fig 1); and a conductive shielding element (Fig 1: through-hole, 37) provided to penetrate upper and lower surfaces of the socket body (Can be seen in Fig 1) to shield noise between adjacent signal probes (Para [0058] teaches through-holes, 37, make the signal probes less susceptible to noise). wherein the shielding element comprises: a via hole formed through the upper and lower surfaces of the socket body (Can be seen in Fig 1); Inuma does not teach a solid conductive wire or rod inserted in the via hole. However, Chung teaches a via hole formed through the upper and lower surfaces of the socket body (Can be seen in Fig 4); and a solid conductive wire or rod inserted in the via hole (Fig 4: ground conductive portion, 120). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the socket body of Inuma to include a wire or rod inserted into the via hole as in Chung. A motivation for this modification is to allow for the socket device to be a single short-circuit and provide connection to the devices outside of the socket, as taught by Chung in Fig 1 and Para [0081]. Regarding Claim 2, Inuma further teaches wherein the shielding element is placed between signal holes that are the nearest neighbors to each other (Fig 2 shows an arrangement of shielding elements surrounding a signal probe). Regarding Claim 4, Inuma further teaches the shielding element is electrically connected to the ground plating layer (Fig 1 shows a continuous plating layer from top to bottom of shield element through-hole such that it would be in contact with the ground plating layer, 33a). Regarding Claim 5, Inuma further teaches the socket body comprises: an upper body portion (See annotated Figure 1 of Inuma) provided with a first support portion (See annotated Figure 1 of Inuma) supporting a top of each of the probes (can be seen in Fig 1 that the probe rests on the support portion); and a lower body portion (See annotated Figure 1 of Inuma) provided with a second support portion (See annotated Figure 1 of Inuma) supporting a bottom of each of the probes (can be seen in Fig 1 that the probe rests on the support portion) and assembled with the upper body portion (Can be seen in Fig 1 that upper and lower body portions are together) Regarding Claim 6, Inuma further teaches the upper body portion comprises: a first upper body portion (Fig 1: member, 33) through which a first guide hole is formed where an upper tip of each of the probes protrudes (Fig 1: probe can be seen extending through hole formed in member, 33); and a second upper body portion (Fig 1: member, 31) through which a first receiving hole having a larger inner diameter than the first guide hole and communicating with the first guide hole is formed (Fig 1 shows the hole formed in member, 31, is larger than the one formed in member, 33, and the holes are in communication with each other through the conductive plating), and assembled with the first upper body portion (Can be seen in Fig 1), and the lower body portion comprises: a first lower body portion (Fig 1: member 34) through which a second guide hole is formed where a lower tip of each of the probes protrudes (Fig 1: probe can be seen extending through hole formed in member, 34); and a second lower body portion (Fig 1: member, 32) through which a second receiving hole having a larger inner diameter than the second guide hole and communicating with the second guide hole and the first receiving hole is formed (Fig 1 shows the hole formed in member, 32, is larger than the one formed in member, 34, and the holes are in communication with each other through the conductive plating), and assembled with the second upper body portion and the first lower body portion (Can be seen in Fig 1). Regarding Claim 8, the combination of Inuma in view of Chung, as presented with respect to claim 4, does not explicitly teach the socket body has an outer plating layer formed on the upper and lower surfaces thereof, the outer plating layer being configured to electrically interconnect the conductive ground plating layers of all of the ground holes and all of the shielding elements as a single continuous plating layer. However, Chung further teaches the socket body has an outer plating layer formed on the upper and lower surfaces thereof (Para [0089] teaches the metal frame layer, 131, may be formed on the top and bottom of the frame), the outer plating layer being configured to electrically interconnect the conductive ground plating layers of all of the ground holes and all of the shielding elements as a single continuous plating layer (Can be seen in Figure 2 that all the ground conductive portion, 120, are connected through the metal frame layer, 131). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the socket body of the combination to incorporate the plating layers of Chung. A motivation for this modification is to allow for the socket device to be a single short-circuit and provide connection to the devices outside of the socket, as taught by Chung in Fig 1 and Para [0081]. PNG media_image1.png 722 662 media_image1.png Greyscale Annotated Figure 1 of Inuma Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Inuma in view Chung in view of Kawata et al. (US-20130065455-A1). Regarding Claim 7, Inuma in view of Chung teaches a conductive signal plating layer formed on a surface of each of the signal holes (Fig 1: second conductive film, 33b). Inuma in view of Chung does not teach an insulating layer formed on a surface of the signal plating layer to electrically insulate each of the signal probes and the signal plating layer. However, Kawata teaches an insulating layer (Fig 7: dielectric layer, 2035) formed on a surface of the signal plating layer (Fig 7: conductive portion, 2251) to electrically insulate each of the signal probes and the signal plating layer (Can be seen in Fig 7 that the signal probes, 2003b/d, are electrically insulated from the signal plating layer, 2251). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the signal probe of Inuma in view of Chung to incorporate the shielding structure of Kawata. A motivation for this change is so that the contacts do not touch the conductive portions of the signal hole, as taught by Kawata in Para [0044]. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEREMIAH J BARRON whose telephone number is (571)272-0902. The examiner can normally be reached M-F 09:30-17:30 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak can be reached at (571) 270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JEREMIAH J BARRON/Examiner, Art Unit 2858 /LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858
Read full office action

Prosecution Timeline

Jan 02, 2024
Application Filed
Jul 30, 2025
Non-Final Rejection — §103
Jan 22, 2026
Response Filed
Mar 02, 2026
Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12601758
Socketed Probes
2y 5m to grant Granted Apr 14, 2026
Patent 12601782
PROBE CARD HOLDER FOR WAFER TESTING
2y 5m to grant Granted Apr 14, 2026
Patent 12601773
DETECTION CIRCUIT AND RELATED ELECTRONIC APPARATUS
2y 5m to grant Granted Apr 14, 2026
Patent 12584724
CLEARANCE SENSOR
2y 5m to grant Granted Mar 24, 2026
Patent 12578382
AUTOMATIC TEST EQUIPMENT INCLUDING MULTIPLE PIN ELECTRONICS INTEGRATED CIRCUITS IN FORM OF MODULE
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

3-4
Expected OA Rounds
78%
Grant Probability
74%
With Interview (-3.6%)
2y 4m
Median Time to Grant
Moderate
PTA Risk
Based on 18 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month