DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 9, 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eldridge et al (US 8,373,428 hereinafter Eldridge).
Regarding to claim 1, Eldridge discloses Figs. 5, a testing module for a semiconductor wafer-form package (probe card assembly 500 for wafer-level testing/burn-in of semiconductor wafer 508 as shown in Fig. 5; where the wafer contains unsingulated semiconductor die/packages), comprising: a circuit board structure (502 as shown in Fig. 5), comprising a main region and a peripheral region next to the main region (probe card 502 as shown in Fig. 5, comprising a main region (central area with interposer/space transformer alignment) and a peripheral region next to the main region (outer areas with terminals 510 and mounting hardware); Cols. 16-17),
a plurality of first connectors, disposed over the peripheral region and connected to the circuit board structure (a plurality of first connectors (top-surface terminals 510) as shown in Fig. 5, disposed over the peripheral region and connected to the circuit board structure (probe card 502 with plated copper traces); Col. 25, lines 1- Col. 17, lines 67),
a first connecting structure, vertically distant from the circuit board structure" (a first connecting structure (space transformer substrate 506) as shown in Fig. 5, vertically distant from the circuit board structure (probe card 502 via interposer 504); Col. 16, lines 30-50; Col. 18, lines 10-30, Col. 25, lines 1- Col. 17, lines 67),
a plurality of second connectors, connected to the first connecting structure" (a plurality of second connectors (bottom terminals 520) as shown in Fig. 5, connected to the first connecting structure (space transformer 506 with internal vias/traces 410/412/404); Col. 16, lines 40-60; Col. 18, lines 20-40, Col. 25, lines 1- Col. 17, lines 67),
and a first bridge connector, electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors" (and a first bridge connector (interposer substrate 504 with resilient interconnection elements 514/516) as shown in Figs. 5-6, electrically coupling the circuit board structure (probe card 502) and the first connecting structure (space transformer 506) by connecting the second connectors (bottom terminals 520) and the first connectors (top-surface terminals 510) via plated through-holes and dual-sided resilient elements; Col. 16, lines 10-20; Col. 16, lines 50-67; Col. 17, lines 30-50; Col. 25, lines 1- Col. 17, lines 67; Figs. 5, 6A-6B),
wherein the semiconductor wafer-form package and the first connectors are located at a same side of the circuit board structure" (wherein the semiconductor wafer-form package (wafer 508 with die sites/bond pads 526) and the first connectors (terminals 510) are located at a same side of the circuit board structure (top side of probe card 502, with wafer urged upward to contact probe elements 524 on the same top side); Col. 16, lines 60-67; Col. 19, lines 10-30; Col. 25, lines 1- Col. 17, lines 67; Fig. 5).
Claim 9 is rejected under 35 U.S.C. § 102(a)(1) as anticipated by Eldridge et al.
Similar to claim 1, with third connectors (probe elements 524) removably and directly installed on the package (wafer bond pads; Col. 16, lines 60-67; Fig. 5).
Regarding claim 15, Eldridge discloses Figs. 1-5, a testing module for a semiconductor wafer-form package (probe card assembly 500 for wafer-level testing/burn-in of semiconductor wafer 508 containing unsingulated die/packages as shown in Fig. 5; Col. 1, lines 50-67; Col. 10, lines 15-25; Col. 16, lines 10-20), comprising: a circuit board structure, comprising a main region and a peripheral region next to the main region" (probe card 502 as circuit board structure, comprising a main region (central area with interposer/space transformer alignment) and a peripheral region next to the main region (outer areas with terminals 510 and mounting hardware); Col. 16, lines 30-50; Col. 17, lines 5-20; Fig. 5),
a plurality of first connectors, disposed over the peripheral region and connected to the circuit board structure" (a plurality of first connectors (top-surface terminals 510) disposed over the peripheral region and connected to the circuit board structure (probe card 502 with plated copper traces); Col. 16, lines 30-50; Col. 17, lines 10-30; Fig. 5),
a first connecting structure, vertically distant from the circuit board structure" (a first connecting structure (space transformer substrate 506) vertically distant from the circuit board structure (probe card 502 via interposer 504); Col. 16, lines 30-50; Col. 18, lines 10-30; Fig. 5),
a plurality of second connectors, connected to the first connecting structure" (a plurality of second connectors (bottom terminals 520) connected to the first connecting structure (space transformer 506 with internal vias/traces 410/412/404); Col. 16, lines 40-60; Col. 18, lines 20-40; Fig. 5), and a first bridge connector, electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors" (and a first bridge connector (interposer substrate 504 with resilient interconnection elements 514/516) electrically coupling the circuit board structure (probe card 502) and the first connecting structure (space transformer 506) by connecting the second connectors (bottom terminals 520) and the first connectors (top-surface terminals 510) via plated through-holes and dual-sided resilient elements; Col. 16, lines 10-20; Col. 16, lines 50-67; Col. 17, lines 30-50; Figs. 5, 6A-6B), wherein the semiconductor wafer-form package and the first connectors are located at a same side of the circuit board structure" (wherein the semiconductor wafer-form package (wafer 508 with die sites/bond pads 526) and the first connectors (terminals 510) are located at a same side of the circuit board structure (top side of probe card 502, with wafer urged upward to contact probe elements 524 on the same top side); Col. 16, lines 60-67; Col. 19, lines 10-30; Fig. 5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 10, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over (US 8,373,428 hereinafter Eldridge), in view of Kuo et al. (US 8,841,931 B2).
Eldridge discloses the testing module of claim 1 (as mapped above), wherein the first bridge connector comprises resilient interconnection elements (Col. 16, lines 10-20; Col. 16, lines 50-67, col. 25-27; Figs. 5-6).
Eldridge et al. does not explicitly disclose the bridge as a plurality of parallel conductive wires. However, Kuo et al. teaches a probe card wiring structure wherein the bridge connector comprises a plurality of parallel conductive wires (parallel traces/wires 130/140 as bridge in probe card for electrical coupling; Col. 4, lines 20-40; Col. 5, lines 10-30; Figs. 2-3).
It would have been obvious to modify Eldridge's bridge connector with Kuo's parallel conductive wires to enable high-density, low-impedance routing in wafer testing, improving signal integrity (Kuo et al., Col. 1, lines 20-40; Eldridge et al., Col. 1, lines 50-67).
Claims 3, 11, 17 are rejected under 35 U.S.C. § 103 as unpatentable over Eldridge et al. in view of Kuo et al. (US 8,841,931 B2).
Eldridge et al. discloses the testing module of claim 1, wherein the first connecting structure comprises a substrate (space transformer 506 as circuit board-like structure; Col. 16, lines 30-50; Col. 18, lines 10-30).
Eldridge et al. does not explicitly disclose the structure as a plurality of parallel conductive wires. However, Kuo et al. teaches the first connecting structure comprises a circuit board or a plurality of parallel conductive wires (parallel wires 130/140 or circuit board 110 for connecting; Col. 4, lines 20-40; Figs. 2-3).
It would have been obvious to modify Eldridge et al.'s connecting structure with Kuo et al.'s parallel wires option for flexible, high-density interconnections in probe cards (Kuo et al., Col. 1, lines 20-40).
Claims 4-6, 18 are rejected under 35 U.S.C. § 103 as unpatentable over Eldridge et al. in view of Root et al. (US 9,024,651 B2).
Eldridge et al. discloses the testing module of claim 1, further comprising: a plurality of third connectors (probe elements 524), disposed over and connected to the first connecting structure (space transformer 506), electrically coupled to the second connectors through the structure, configured to transmit electric signals for testing the wafer-form package over the main region (Col. 16, lines 60-67; Col. 19, lines 10-30; Fig. 5), wherein at least one second and one third connector are located at opposite/same sides of the structure (opposite/same sides via bottom/top terminals; Col. 16, lines 40-60), wherein the package comprises fourth connectors (bond pads 526) and at least one socket surrounded by fourth connectors, and third connectors electrically coupled to fourth for temporary connection, overlapped along stacking direction (probe tips overlapping bond pads; Col. 16, lines 60-67).
Eldridge et al. does not explicitly disclose the socket surrounded and direct overlap. However, Root et al. teaches third connectors overlapped with fourth along stacking, with socket surrounded by connectors for temporary connection (probe tips 33 overlapped with pads, socket-like wire guide 20 surrounded; Col. 8, lines 10-50; Figs. 1-2).
It would have been obvious to modify Eldridge et al. with Root et al.'s overlapped socket configuration for precise, temporary wafer contact (Root et al., Col. 1, lines 20-67).
Claims 7, 12, 19 are rejected under 35 U.S.C. § 103 as unpatentable over Eldridge et al. in view of Root et al. (US 9,024,651 B2).
Eldridge et al. discloses the testing module of claim 1, further comprising: a second bridge connector (probe elements 524 as additional bridge), disposed over the main region and electrically connected to the first connecting structure through the package (Col. 16, lines 60-67; Fig. 5), wherein the second bridge connector comprises a substrate with circuitry embedded therein and a plurality of pins disposed over the substrate and electrically connected to the circuitry (space transformer substrate with embedded vias/traces, pin-like resilient tips; Col. 16, lines 30-50; Col. 18, lines 10-30), wherein the package is disposed inside a space confined by the circuit board, first connectors, first bridge, first connecting structure, second connectors, and second bridge (confined probing space; Col. 16, lines 50-67; Fig. 5).
Eldridge et al. does not explicitly disclose pins on substrate. However, Root et al. teaches a second bridge connector with substrate, embedded circuitry, and pins (wire guide 20 as substrate with circuitry, pins/probes 30; Col. 8, lines 10-50; Figs. 1-2).
It would have been obvious to modify Eldridge et al. with Root et al.'s pin-based bridge for enhanced temporary connections (Root et al., Col. 1, lines 20-40).
Claim 14 is rejected under 35 U.S.C. § 103 as unpatentable over Eldridge et al. in view of Chiang (US 6,774,659 B1).
Eldridge et al. discloses the testing module of claim 9/1, further comprising an elastic element (resilient interconnection elements) disposed over the circuit board, wherein the elastic element is sandwiched between the package and the circuit board (resilient between wafer and probe card; Col. 16, lines 10-20; Col. 16, lines 50-67).
Eldridge et al. does not explicitly disclose the elastic sandwiched in insulative housing. However, Chiang teaches an elastic element (insulative housing/elastic layer) sandwiched between package and board for testing (Col. 3, lines 20-40; Col. 4, lines 10-30; Figs. 1-2).
It would have been obvious to modify Eldridge et al. with Chiang's sandwiched elastic for shock absorption and reliable contact during testing (Chiang, Col. 1, lines 10-30).
Allowable Subject Matter
Claims 8, 13, 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claims 8, 13, 20, the prior art alone and/or in combination with the other prior art does not disclose all features as recited in the claims above.
Conclusion
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/TUNG X NGUYEN/ Primary Examiner, Art Unit 2858 11/29/2025