Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al., US Patent Application (20200006486), hereinafter “Chen”.
Regarding claim 1 Chen teaches a method, comprising: forming a fin structure from a substrate the formation of fins 74 in the semiconductor substrate 70. [Chen para 0020]; depositing a first semiconductor material on a first semiconductor layer of the fin structure FIGS. 2A and 2B illustrate a semiconductor substrate 70. The semiconductor substrate 70 may be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. [Chen para 0019]; depositing a second semiconductor material on the first semiconductor material the semiconductor material of the semiconductor substrate may include an elemental semiconductor including silicon (Si) or germanium (Ge); …; or a combination thereof [Chen para 0019]; depositing an interlayer dielectric layer over the second semiconductor material a dielectric layer can be formed over a top surface of the semiconductor substrate 70 [Chen para 0023]; forming an opening in the interlayer dielectric layer to expose the second semiconductor material a dielectric layer can be formed over a top surface of the semiconductor substrate 70; trenches can be etched through the dielectric layer; heteroepitaxial structures can be epitaxially grown in the trenches using a material different from the semiconductor substrate 70; and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form fins. [Chen para 0023]; performing a dopant implantation process to form a doped region, wherein the doped region includes a first portion of the second semiconductor material The semiconductor substrate 70 may be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) [Chen para 0019]; then performing an amorphization process to form an amorphous region, wherein the amorphous region includes a second portion of the second semiconductor material an amorphization implant may be performed. In some examples, the amorphization implant includes implanting an impurity species into the epitaxy source/drain regions 92 to make at least upper portions of the surface dopant regions 104 of the epitaxy source/drain regions 92 amorphous. The upper portions of the surface dopant regions 104 that are made amorphous can extend from respective upper surfaces of the epitaxy source/drain regions 92 to a depth in a range from about 2 nm to about 20 nm, for example. [Chen para 0039]; and performing an annealing process to recrystallize the amorphous region. An anneal can be performed to facilitate the reaction of the epitaxy source/drain regions 92 with the adhesion layer 110 and/or barrier layer 112. … The anneal may further re-crystallize any of the epitaxy source/drain regions 92 that was amorphous. [Chen para 0039]
Regarding claim 2 Chen teaches claim 1 in addition Chen teaches a wherein a height of the first portion of the second semiconductor material is substantially greater than a height of the second portion of the second semiconductor material. FIGS. 10A and 10B further illustrate the formation of surface dopant regions 104 in respective upper portions of the epitaxy source/drain regions 92. [Chen para 0035]
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Regarding claim 3 Chen teaches claim 1 in addition Chen teaches a wherein the doped region includes portions of the first semiconductor material. The semiconductor substrate 70 may be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) [Chen para 0019]
Regarding claim 4 Chen teaches claim 1 in addition Chen teaches a wherein the amorphous region includes the first semiconductor material. The upper portions of the surface dopant regions 104 that are made amorphous can extend from respective upper surfaces of the epitaxy source/drain regions 92 to a depth in a range from about 2 nm to about 20 nm, for example. In some examples, such as for a p-type device, [Chen para 0039]
Regarding claim 5 Chen teaches claim 1 in addition Chen teaches a wherein the fin structure comprises the first semiconductor layer, a second semiconductor layer located below the first semiconductor layer, and a third semiconductor layer located below the second semiconductor layer. Referring to FIG. 3, a bottom sacrificial layer 204, a bottom semiconductor layer 205, and a stack 207 are deposited over the substrate 20. The bottom sacrificial layer 204 may include silicon germanium (SiGe) and the bottom semiconductor layer 205 may include silicon (Si). The stack 207 includes a plurality of channel layers 208 interleaved by a plurality of sacrificial layers 206. Although three (3) sacrificial layers 206 and (3) channel layers 208 are shown in the figures, the present disclosure is not so limited. The numbers of sacrificial layers 206 and the channel layers 208 may be between 2 and 10 according to various design requirements. In some instances, the plurality of channel layers 208 may include silicon (Si) and the plurality of sacrificial layers 206 may include silicon germanium (SiGe). [Chu para 0015]
Regarding claim 6 Chen teaches claim 5 in addition Chen teaches a further comprising depositing a third semiconductor material on the second semiconductor layer and a fourth semiconductor material on the third semiconductor layer, wherein the second semiconductor material is deposited on the third and fourth semiconductor materials. the formation of surface dopant regions 104 in respective upper portions of the epitaxy source/drain regions 92. The surface dopant regions 104 have high surface dopant concentrations at respective upper surfaces of the epitaxy source/drain regions 92. The surface dopant regions 104 are formed by implanting dopants into the upper portions of the epitaxy source/drain regions 92 using plasma doping (PLAD). Example dopants for the surface dopant regions 104 can include or be, for example, boron for a p-type device and phosphorus or arsenic for an n-type device, although other dopants may be used. [Chen para 0035]
Regarding claim 7 Chen teaches claim 6 in addition Chen teaches a wherein the third semiconductor layer is outside of the amorphous region. such as for a p-type device, the epitaxy source/drain regions 92 are Si.sub.xGe.sub.1-x, and germanium is the species implanted to amorphize the upper portions of the surface dopant regions 104 of the epitaxy source/drain regions 92 [Chen para 0092]
Regarding claim 8 Chen teaches a method, comprising: forming a fin structure from a substrate; recessing a portion of the fin structure to expose a portion of the substrate the formation of fins 74 in the semiconductor substrate 70. [Chen para 0020]; depositing a first semiconductor material over the portion of the substrate FIGS. 2A and 2B illustrate a semiconductor substrate 70. The semiconductor substrate 70 may be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. [Chen para 0019]; depositing an interlayer dielectric layer over the first semiconductor material the semiconductor material of the semiconductor substrate may include an elemental semiconductor including silicon (Si) or germanium (Ge); …; or a combination thereof [Chen para 0019];; forming an opening in the interlayer dielectric layer to expose the first semiconductor material a dielectric layer can be formed over a top surface of the semiconductor substrate 70; trenches can be etched through the dielectric layer; heteroepitaxial structures can be epitaxially grown in the trenches using a material different from the semiconductor substrate 70; and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form fins. [Chen para 0023]; performing an amorphization process to form an amorphous region, wherein the amorphous region includes a portion of the first semiconductor material an amorphization implant may be performed. In some examples, the amorphization implant includes implanting an impurity species into the epitaxy source/drain regions 92 to make at least upper portions of the surface dopant regions 104 of the epitaxy source/drain regions 92 amorphous. The upper portions of the surface dopant regions 104 that are made amorphous can extend from respective upper surfaces of the epitaxy source/drain regions 92 to a depth in a range from about 2 nm to about 20 nm, for example. [Chen para 0039]; performing an annealing process to convert a first portion of the amorphous region to a first crystalline region An anneal can be performed to facilitate the reaction of the epitaxy source/drain regions 92 with the adhesion layer 110 and/or barrier layer 112. … The anneal may further re-crystallize any of the epitaxy source/drain regions 92 that was amorphous. [Chen para 0039]; and forming a silicide layer from a second portion of the amorphous region. each conductive feature may further include a silicide region 114 on the respective surface dopant region 104 of the epitaxy source/drain region 92, [Chen para 0040]
Regarding claim 9 Chen teaches claim 8 in addition Chen teaches a wherein the first semiconductor material comprises a second crystalline region located below the first crystalline region. The etch process can be isotropic or anisotropic, or further, may be selective with respect to one or more crystalline planes of the semiconductor substrate 70 [Chen para 0029]
Regarding claim 10 Chen teaches claim 9 in addition Chen teaches a wherein the first crystalline region has a dopant concentration substantially greater than a dopant concentration of the second crystalline region. The high surface dopant concentration at the upper surface of the source/drain region can be an order of magnitude or more greater than a dopant concentration of a remainder of the source/drain region. [Chen para 0012]
Regarding claim 11 Chen teaches claim 9 in addition Chen teaches a wherein the silicide layer has a dopant concentration substantially greater than the dopant concentration of the second crystalline region. dopant region 104 can further have a concentration gradient, where any instance of a dopant concentration along the concentration gradient is greater than the dopant concentration of the remainder of the epitaxy source/drain region 92. [Chen para 0036]
Regarding claim 12 Chen teaches claim 8 in addition Chen teaches a wherein the fin structure comprises a plurality of semiconductor layers. fins 74 may be formed. In other embodiments, a dielectric layer can be formed over a top surface of the semiconductor substrate 70; [Chen para 0023] the formation of gate stacks, or more generically, a gate structure, on the fins 74. The gate stacks are over and extend laterally perpendicularly to the fins 74 [Chen para 0024 ]
Regarding claim 13 Chen teaches claim 12 in addition Chen teaches a further comprising depositing a second semiconductor material on each semiconductor layer of the plurality of semiconductor layers, wherein the first semiconductor material is deposited on the second semiconductor material. Referring to FIG. 3, a bottom sacrificial layer 204, a bottom semiconductor layer 205, and a stack 207 are deposited over the substrate 20. The bottom sacrificial layer 204 may include silicon germanium (SiGe) and the bottom semiconductor layer 205 may include silicon (Si). The stack 207 includes a plurality of channel layers 208 interleaved by a plurality of sacrificial layers 206. Although three (3) sacrificial layers 206 and (3) channel layers 208 are shown in the figures, the present disclosure is not so limited. The numbers of sacrificial layers 206 and the channel layers 208 may be between 2 and 10 according to various design requirements. In some instances, the plurality of channel layers 208 may include silicon (Si) and the plurality of sacrificial layers 206 may include silicon germanium (SiGe). [Chu para 0015]
Regarding claim 14 Chen teaches claim 13 in addition Chen teaches a wherein the amorphous region includes the second semiconductor material in contact with a topmost semiconductor layer of the plurality of semiconductor layers. The upper portions of the surface dopant regions 104 that are made amorphous can extend from respective upper surfaces of the epitaxy source/drain regions 92 to a depth in a range from about 2 nm to about 20 nm, for example. [Chen para 0039];
Regarding claim 15 Chen teaches a semiconductor device structure, the formation of fins 74 in the semiconductor substrate 70. [Chen para 0020] comprising: a plurality of semiconductor layers disposed over a substrate FIGS. 2A and 2B illustrate a semiconductor substrate 70. The semiconductor substrate 70 may be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. [Chen para 0019]; the semiconductor material of the semiconductor substrate may include an elemental semiconductor including silicon (Si) or germanium (Ge); …; or a combination thereof [Chen para 0019]; and a source/drain region disposed adjacent the plurality of semiconductor layers, the formation of epitaxy source/drain regions 92 in the recesses 90 [Chen para 0030] wherein the source/drain region comprises: a first semiconductor material in contact with each semiconductor layer of the plurality of semiconductor layers, The epitaxy source/drain regions 92 may include or be silicon germanium (Si.sub.xGe.sub.1-x, where x can be between approximately 0 and 1), silicon carbide, silicon phosphorus, silicon carbon phosphorus, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, materials for forming a III-V compound semiconductor include InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like. [Chen para 0030] wherein the first semiconductor material in contact with a topmost semiconductor layer of the plurality of semiconductor layers has a first dopant concentration, The epitaxy source/drain regions 92 (or other source/drain region) may have a dopant concentration in a range from about 10.sup.19 cm.sup.−3 to about 10.sup.21 cm.sup.−3. [Chen para 0031] and the first semiconductor material in contact with a semiconductor layer of the plurality of semiconductor layers disposed below the topmost semiconductor layer has a second dopant concentration substantially less than the first dopant concentration the surface dopant region 104 can further have a concentration gradient, where any instance of a dopant concentration along the concentration gradient is greater than the dopant concentration of the remainder of the epitaxy source/drain region 92. [Chen para 0036]; and a second semiconductor material surrounding the first semiconductor material. upper surfaces of the epitaxy source/drain regions 92 to a depth in a range from about 2 nm to about 20 nm, for example. In some examples, such as for a p-type device, the epitaxy source/drain regions 92 are Si.sub.xGe.sub.1-x, and germanium is the species implanted to amorphize the upper portions of the surface dopant regions 104 of the epitaxy source/drain regions 92. [Chen para 0039]
Regarding claim 16 Chen teaches claim 15 in addition Chen teaches a further comprising a silicide layer disposed on the second semiconductor material. each conductive feature may further include a silicide region 114 on the respective surface dopant region 104 of the epitaxy source/drain region 92, [Chen para 0040]
Regarding claim 17 Chen teaches claim 16 in addition Chen teaches a further comprising a first crystalline region disposed below the silicide layer and a second crystalline region disposed below the first crystalline region. The etch process can be isotropic or anisotropic, or further, may be selective with respect to one or more crystalline planes of the semiconductor substrate 70 [Chen para 0029]
Regarding claim 18 Chen teaches claim 17 in addition Chen teaches a wherein a dopant concentration of the first crystalline region is substantially greater than a dopant concentration of the second crystalline region. The high surface dopant concentration at the upper surface of the source/drain region can be an order of magnitude or more greater than a dopant concentration of a remainder of the source/drain region. [Chen para 0012]
Regarding claim 19 Chen teaches claim 15 in addition Chen teaches a wherein the second semiconductor material has a dopant concentration gradient. dopant region 104 can further have a concentration gradient, where any instance of a dopant concentration along the concentration gradient is greater than the dopant concentration of the remainder of the epitaxy source/drain region 92. [Chen para 0036]
Regarding claim 20 Chen teaches claim 15 in addition Chen teaches a further comprising a third semiconductor material disposed over the substrate and a dielectric layer disposed on the third semiconductor material, wherein the second semiconductor material is disposed on the dielectric layer. he dielectric layer 80 may be a gate dielectric, and the gate layer 82 may be a gate electrode. The gate dielectrics, gate electrodes, and mask 84 for the gate stacks may be formed by sequentially forming respective layers, and then patterning those layers into the gate stacks. For example, a layer for the gate dielectrics may include or be silicon oxide, silicon nitride, a high-k dielectric material, the like [Chen para 0025]
Conclusion
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/ROBERT J MICHAUD/Examiner, Art Unit 2622