DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7, 9, 10, 11, 14, 15, 17, & 18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ok (US Pub no. 2022/0139904 A1)
Regarding claim 1, Ok et al discloses A semiconductor memory device comprising: a plurality of first conductive layers (130) aligned in a first direction with a space in between[0045]; a first plug(THV) penetrating the first conductive layers(130)[0072] fig. 11; a second conductive layer (ML62)below the first conductive layers(130)[0075], the second conductive layer (ML62) being coupled to a lower end of the first plug(THV)[0075]; a first transistor(TR-left of THV) below the first conductive layers(130); a second transistor (TR-Right of THV)in a second region between the
first transistor (TR)and a first region below the second conductive layer(ML62), the second transistor (TR-Right of THV)having a gate electrically coupled to the first transistor and a drain
electrically coupled to the first transistor(TR-left of THV) fig .11; and a third transistor(TR-under THV) in the second region, the third transistor (TR-under THV) having a source and a drain electrically coupled to each other fig. 11[0074-0075].
Regarding claim 2, Ok et al discloses wherein the first transistor(TR-left of THV) is electrically coupled to the first plug THV fig. 11[0075].
Regarding claim 3, Ok et al discloses wherein the gate and the drain of the second transistor (TR-Right of THV)are electrically coupled to a gate of the first transistor(TR-left of THV)[0074-0075].
Regarding claim 4, Ok et al discloses wherein the second conductive layer (ML62)extends in a second direction (x), and a source and the drain of the second transistor (TR-Right of THV)are aligned in a third direction intersecting the second direction(z) fig. 11.
Regarding claim 5, Ok et al discloses further comprising: a third conductive layer extending in the third direction and coupled to the second conductive layer, wherein the gate and the drain of the second transistor are coupled to the third conductive layer.
Regarding claim 6, Ok et al discloses wherein the second conductive layer(ML62) extends in a second direction, and the semiconductor memory device further comprises: a third conductive layer(MC61) extending in a third direction intersecting the second direction fig. 11, the third conductive layer (130)being coupled to the first transistor(TR-left of THV)[; and a fourth conductive layer (MC60)below the second conductive layer (ML62)and the third conductive layer(MC61), the fourth conductive layer (MC60)being coupled to the second conductive layer (ML62)and the third conductive layer (MC61)and extending in the third direction, and the gate and the drain of the second transistor (TR-Right of THV)are coupled to the fourth conductive layer(MC60) fig. 11.
Regarding claim 7, Ok et al discloses , wherein the second conductive layer(ML62) and the third conductive layer (patterns of ML62 adjacent) are located at the same position with respect to the first direction fig. 11.
Regarding claim 9, Ok et al discloses wherein the second region (region to the left of THV)is adjacent to the first region(region to the right of THV) fig 11..
Regarding claim 10, Ok et al discloses further comprising: a first semiconductor layer (110U) extending in the first direction(y) in the plurality of first conductive layers(130); and an insulating film (134)between the first semiconductor layer and the first conductive layers(130) fig. 11[0067].
Regarding claim 11, Ok et al discloses A semiconductor memory device comprising: a plurality of first conductive layers (130)aligned in a first direction with a space in between[0045] fig. 11; a plug arrangement portion (THV)below the first conductive layers(130)[0072] fig. 11, the plug arrangement portion(THV) being provided with a first plug extending upward above the first conductive
layers(130) fig. 11; and an antenna element(D40) arrangement portion below the first conductive layers(130) and adjacent to the plug arrangement portion(THV)[0034-0035] fig. 11, the antenna element arrangement
portion(D40) being provided with an antenna element (42)being electrically coupled to an interconnect (ML62)between the first plug(THV) and a transistor(TR) fig .11.
Regarding claim 14 Ok et al discloses wherein the transistor (Tr) is electrically coupled to the first plug(THV) via the interconnect(ML62) fig. 11.
Regarding claim 15, Ok et al discloses A semiconductor memory device comprising: a memory cell array(CAS)[0048]; a plug arrangement portion(THV) below the memory cell array(CAS) fig. 11, the plug arrangement portion (THV) being provided with a first plug electrically coupled to a first interconnect (195) or BL)above the memory cell array(CAS)[0100]; a peripheral circuit portion (PCS)below the memory cell array(CAS)[0036], the peripheral circuit portion(PCS) being provided with a first transistor(TR); and an antenna element arrangement portion (DR)between the plug arrangement portion(THV of TA) and the peripheral circuit portion(PCS-200), the antenna element arrangement portion (DR)being provided with an antenna element (D40)electrically coupled to a second interconnect (ML62)between the first plug (THV)and the first transistor(TR) fig. 11.
Regarding claim 17, Ok et al discloses wherein the first plug (THV)penetrates the memory cell array(CAS) fig. 11.
Regarding claim 18, Ok et al discloses, wherein the first transistor (TR)is electrically coupled to the first plug(THV) via the second interconnect(ML62) fig. 11.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 , 12, 13, & 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ok (US Pub no. 2022/0139904 A1) in view of Nishikawa (US Pub no 2019/0371800 A1).
Regarding claim 8, Ok et al discloses all the claim limitations of claim 1 and further teaches a third conductive layer (ML61)below the second conductive Layer(ML62) and coupled to the second conductive layer(ML62)fig. 11, but fails to teach wherein p x q transistors are aligned in a region of the second region below a region through which the number i at most of conductive layers pass, to form p rows and q columns at the same position as the third conductive layer in the first direction, where i is an integer equal to or greater than 1, and where p and q are integers that satisfy p x q being equal to or greater than i.
However, Nishikawa et al discloses wherein p x q transistors (transistors in diode regions 610 and 620)are aligned in a region of the second region below a region through which the number i at most of conductive layers pass, to form p rows and q columns at the same position as the third conductive layer in the first direction, where i is an integer equal to or greater than 1, and where p and q are integers that satisfy p x q being equal to or greater than I fig. 21B/fig. 21C(fig. 21B show rows and columns of region 610 and 620 which contain transistors) [0172]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ok et al with the teachings of Nishikawa et al to enhance performance of the device.
Regarding claim 12, Nishikawa et al discloses wherein the antenna element arrangement portion (610/620is provided between a plug arrangement portion (through memory contact vias)and the transistor(750)[0079-0080] (fig. 20b.
Regarding claim 13, Ok e al discloses all the claim limitations of claim 11 but fails to teach wherein the antenna element has a drain and a gate, the drain and the gate of the antenna element is electrically coupled to a gate of the transistor via the interconnect
However, Nishikawa et al discloses wherein the antenna element (610/620)has a drain and a gate fig 20B. 21C[0081]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ok et al with the teachings of Nishikawa et al such that the antenna element has a drain and a gate, the drain and the gate of the antenna element is electrically coupled to a gate of the transistor via the interconnect results to enhance the performance of the device.
Regarding claim 16, Ok et al discloses all the claim limitations of claim 15 but fails to teach wherein the antenna element has a drain and a gate, the drain and the gate of the antenna element is electrically connected a gate of the first transistor via
the second interconnect.
Nishikawa et al discloses wherein the antenna element (61/620)has a drain and a gate fig. 21C[0081]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ok et al with the teachings of Nishikawa et al such that the antenna element has a drain and a gate, the drain and the gate of the antenna element is electrically coupled to a gate of the transistor via the interconnect results to enhance the performance of the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM.
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/LATANYA N CRAWFORD EASON/ Primary Examiner, Art Unit 2813
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