DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US Patent Application Publication No. 2023/0033087 to Suk et al.
Regarding claim 1, Suk et al. teach a semiconductor package (Fig. 7B, for example), comprising:
a first redistribution substrate (100);
a first semiconductor chip (200) on the first redistribution substrate;
a second redistribution substrate (600) on the first semiconductor chip (Fig. 7B);
inter-substrate through-electrodes (300) on the first redistribution substrate at one side of the first semiconductor chip and connecting the first redistribution substrate to the second redistribution substrate;
a second semiconductor chip (720) on the first semiconductor chip; and
a heat dissipation structure (790) on the second semiconductor chip.
Allowable Subject Matter
Claims 2 – 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 11 – 20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record does not teach or reasonably suggest a semiconductor package as recited in claims 11 and 16, including respectively, “an interposer chip on the first semiconductor chip and at one side of the second semiconductor chip” or “a memory device on the second redistribution substrate, wherein the memory device and the second semiconductor chip are configured to exchange memory signals without the memory signals passing through the first redistribution substrate.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication No. 2024/0021579 to Mun teaches a semiconductor package including first and second redistribution layers, an upper and lower chip and through electrodes. Mun does not teach a heat dissipation structure on the second chip, an interposer chip on the first semiconductor chip, or a memory device on the second redistribution substrate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS W OWENS whose telephone number is (571)272-1662. The examiner can normally be reached M-F 5:30-1:30.
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DOUGLAS W. OWENS, Esq.
Primary Patent Examiner
Art Unit 2897
/DOUGLAS W OWENS/Primary Patent Examiner, Art Unit 2897